CN101504633B - Multi-channel DMA controller - Google Patents
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Abstract
The invention relates to a multi-channel DMA controller, which comprises a plurality of DMA channel modules and a multiplexing module, wherein each DMA channel module comprises a data buffer memory together with a control module thereof and a set of control registers; the data buffer memories together with the control modules thereof of all channels are connected to the one multiplexing module; furthermore, each channel of the multi-channel DMA controller comprises a DMA interface signal processing module and a bus interface processing module. The multi-channel DMA controller can reduce the overhead for bus arbitration blocks and memory units on SoC. In addition, the controller only needs to increase or decrease the modules of the corresponding channels in order to increase or decrease one DMA channel, thereby having good reusability.
Description
Technical field
The present invention relates to dma controller, relate in particular to a kind of multi-channel DMA controller.
Background technology
Along with the development of SOC(system on a chip) (SOC), in the chips integrated module also more and more, its demand to internal storage access is also increasingly high.Therefore, for the module in the chip provides the efficient of a kind of simple unified memory Accessing Mechanism for chip design, it is more and more important that reliability, reusability all seem.In general; High-speed module adopts Advanced High-performance Bus (AdvancedHigh-performance Bus mostly; AHB) and so on bus visits internal memory, and (direct memory access, DMA) mode visits internal memory and low-speed module is mostly through the direct memory visit.Dma mode also be used between storer and the storer or peripheral hardware and storer between carry out the immediate data visit.
Fig. 1 is the structural representation of low-speed module access memory in the SOC(system on a chip) of prior art.As shown in Figure 1; In the SOC(system on a chip) that adopts AMBA (Advanced Microcontroller Bus Architecture) bus; Each DMA request module all has the dma controller of a correspondence, and each dma controller all has the bus of a direct access memory of ability.When low-speed module need be carried out the DMA transmission, it sent dma request signal to its corresponding dma controller.Dma controller receives after the dma request signal, sends bus request signal to bus arbiter.Bus arbiter receives after the bus request signal; If this moment, bus arbiter did not have the more bus request of high priority; Can after current bus cycles finish, send the DMA response signal to dma controller, just bus control right is transferred to dma controller and is controlled; After dma controller obtains the bus right to use, begin to carry out the DMA transmission.Before the DMA transmission, processor need be configured the control register in the dma controller, promptly obtains the control information of DMA transmission and transmission parameter is carried out initialization.Dma controller adopts APB (Advanced Peripheral Bus; Advanced peripheral bus) reading of data from the low speed DMA request module; And then through AHB (Advanced High performanceBus; Advanced High-performance Bus) etc. high-speed bus visits internal memory, and promptly the data transmission between dma controller and the low speed DMA request module adopts the low speed bus of APB and so on, and the data transmission between dma controller and the internal memory adopts the high-speed bus of AHB and so on.
Owing to the number of the low-speed module that requires the DMA transmission in the SOC chip maybe be many, each dma module is all linked bus arbiter through bus, causes more bus to be directly connected to bus arbiter, makes bus arbiter that unnecessary spending arranged; In addition; All need an independent FIFO storage unit (FIRST IN FIRST OUT in the bus access interface between each dma controller and the bus arbiter; FIFO); These storage unit can't be shared between a plurality of low-speed module, thereby have increased memory spending to a certain extent.
Summary of the invention
In view of this, the invention provides a kind of multi-channel DMA controller, can reduce bus expense and memory spending, and have good reusability.
The present invention provides a kind of multi-channel DMA controller, comprising:
A plurality of DMA channel modules, said each DMA channel module comprises:
Data buffering storage and control module thereof are communicated by letter with outside DMA requesting service, are used to carry out the DMA data transmission; And
The control register module comprises one group of control register, communicates by letter with said data buffering storage and control module thereof, is used for according to the pre-configured data of said control register the DMA data transmission of said data buffering storage and control module thereof being controlled;
Multiplexing module is communicated by letter with storage of data buffering in said each DMA channel module and control module thereof, is used for carrying out the DMA data transmission of said a plurality of DMA channel modules to be connected to external bus interface after multiplexed.
Further, said data buffering storage and control module thereof comprise:
First buffered memory module is used for storing the data of DMA data transmission;
The buffer-stored control module; The data that are used to control from outside DMA requesting service write said first buffered memory module; And the data in said first buffered memory module are when reaching a constant volume; Produce written request signal, and be transferred to external bus interface to said written request signal through said bus multiplexing module; Also be used for controlling and deliver to outside DMA requesting service after reading the data of said first buffered memory module; And the data in said first buffered memory module are when reaching a constant volume; Produce reading request signal, and be transferred to external bus interface to said reading request signal through said multiplexing module.
Further, said each DMA channel module also comprises:
The DMA interface signal processing module; Outside DMA requesting service is communicated by letter with said data buffering storage and control module thereof through said DMA interface signal processing module, and said DMA interface signal processing module is used for the DMA interface signal between synchronous said outside DMA requesting service and the said DMA interface signal processing module.
Further, said each DMA channel module also comprises:
The EBI processing module; Data buffering storage and control module thereof in said each DMA channel module are communicated by letter with said multiplexing module through said EBI processing module, and said EBI processing module is used to change the signal between said buffer-stored and control module and the external bus interface.
Multi-channel DMA controller according to the present invention is compared with prior art: multi-channel DMA controller of the present invention is connected with a plurality of DMA request module through a plurality of DMA interfaces respectively; And has only an EBI between the bus arbitration module of SOC(system on a chip); And the buffer storage unit in a plurality of DMA channels share multiplexing modules, thereby can reduce bus arbitration module and internal memory cost in the SOC(system on a chip).In addition, because each passage of multi-channel DMA controller is relatively independent, if increase/delete a DMA passage, only needs to increase/delete the pairing module of this DMA passage, and need not to revise any logic, reusability is good.
Description of drawings
Fig. 1 is the structural representation of low-speed module access memory in the SOC(system on a chip) of prior art;
Fig. 2 is the connection synoptic diagram of multi-channel DMA controller of the present invention in SOC(system on a chip);
Fig. 3 is the structured flowchart of the multi-channel DMA controller of one embodiment of the invention;
Fig. 4 is the structured flowchart of the multi-channel DMA controller of another embodiment of the present invention;
Embodiment
To combine the accompanying drawing specific embodiments of the invention to explain in more detail below.
Fig. 2 is the connection synoptic diagram of multi-channel DMA controller of the present invention in SOC(system on a chip); As shown in Figure 2; Multi-channel DMA controller directly is connected with a plurality of low speed DMA request module; Set up a plurality of DMA passages, all DMA passages all are connected with the bus arbitration module through an EBI, and other modules in the chip also are connected with the bus arbitration module.Dma controller sends bus request to the bus arbitration module, being connected to internal memory through bus arbitration and after obtaining bus control right through bus, to carry out internal storage access.Should be understood that; Multi-channel DMA controller directly links to each other with the low speed DMA request module; DMA interface can adopt any existing DMA interface, also can define DMA interface as required voluntarily, as long as satisfy the proper communication between DMA request module and the multi-channel DMA controller.
Multi-channel DMA controller directly is connected with a plurality of DMA request module respectively through a plurality of DMA interfaces, sets up a plurality of DMA passages.Fig. 3 is the structured flowchart of the multi-channel DMA controller of one embodiment of the invention; As shown in Figure 3; Each DMA passage comprises a DMA interface signal processing module, data buffer-stored and control module thereof, one group of control register, an EBI processing module, and the EBI processing module of all DMA passages all is connected with a multiplexing module.Multiplexing module is connected with the bus arbitration module through an EBI of SOC(system on a chip).
As shown in Figure 3; The DMA interface signal processing module of each DMA passage is used for belonging to synchronously the DMA request module of different clock-domains and the DMA interface signal between the multi-channel DMA controller; Become the DMA interface signal of multi-channel DMA controller clock zone to the DMA interface conversion of signals of DMA request module input multi-channel DMA controller, the DMA interface conversion of signals of exporting to the DMA request module to multi-channel DMA controller becomes the DMA interface signal of DMA request module clock zone.The DMA interface signal comprises that dma request signal, DMA answer signal and DMA read and write data etc.
As shown in Figure 3; The interface signal processing module of each DMA passage is connected to data buffering storage and control module thereof; Data buffering storage and control module thereof comprise the buffer-stored control module and first buffered memory module, and first buffered memory module can be the Data Buffer Memory of any kind.In one embodiment of the invention, first buffered memory module adopts FIFO (FIFO) storer, and the first buffered memory module FIFO is used for storing the data of DMA data transmission.The control of buffer-stored control module is writing among the first buffered memory module FIFO from DMA request module and the data after interface signal processing module synchronous processing; When the data that write among the first buffered memory module FIFO reach a certain amount of; For example; When the first buffered memory module FIFO was half-full, the buffer-stored control module produced written request signal; The buffer-stored control module is also controlled and is read and after DMA interface signal processing module synchronous processing, deliver to outside DMA request module to the data among the first buffered memory module FIFO; Data read in the first buffered memory module FIFO is empty when a certain amount of; For example; When the first buffered memory module FIFO was half-full, the buffer-stored control module produced reading request signal.
As shown in Figure 3; One group of control register of each DMA passage is connected to data buffering storage and control module thereof; Be provided with the control information and the transmission parameter of DMA transmission in the control register in advance; For example, control information and transmission parameter can comprise: source address and destination address, the DMA of DMA request module and internal memory transmission transmit data length, and the mode of read/write memory is individual character transmission or burst transfer etc.Control register comprises the address register of storage DMA access memory, byte register, status register and the order control register etc. of storage DMA transmission data length.Control information in the control register and transmission parameter can be provided with through software by CPU (CPU) before the DMA transmission carrying out in advance.Data buffering storage and control module thereof are controlled the DMA data transmission of data buffer-stored and control module thereof according to the control information and the transmission parameter that are provided with in advance in the control register.
As shown in Figure 3, the EBI processing module of each DMA passage is connected to data buffering storage and control module thereof, and the EBI processing module of all passages is connected to multiplexing module.The EBI processing module of each DMA passage is used for the signal between translation data buffer-stored and control module and the multiplexing module.The signal that signal between EBI processing module and the multiplexing module and multiplexing module output to external bus interface all meets the bus protocol that external bus interface adopts; That is to say that the EBI processing module is the signal that meets the bus protocol of external bus interface employing to the conversion of signals of data buffering storage and control module output thereof; Comprise that the reading request signal and the written request signal that produce above-mentioned buffer-stored control module convert the signal that meets the external bus interface agreement into, the EBI processing module is the external bus interface signal signal that data buffering storage and control module thereof require through the conversion of signals that multiplexing module is input to data buffering storage and control module thereof also simultaneously.Multiplexing module is used for carrying out the signal of a plurality of DMA passages and data transmission to deliver to an external bus interface after multichannel is selected, and comprises carrying out bus arbitration carry out the bus arbitration module that the multichannel selection is sent to external bus interface and then is sent to SOC(system on a chip) again through the reading request signal of EBI processing module conversion and written request signal.Comprise second buffered memory module in the multiplexing module, be used to store the data of DMA transmission, in one embodiment of the invention, second buffered memory module adopts the FIFO storer.
Should be pointed out that above-mentioned bus protocol can be any bus protocol, for example, ahb bus, AXI bus and AXI_lite bus.Ahb bus is a most important parts in the AMBA2.0 agreement that proposes of ARM company, and the SOC(system on a chip) bus as SOC is mainly used in the connection between the high-performance module.AXI (Advanced eXtensible Interface, advanced extensive interface) bus protocol is a most important parts in the AMBA3.0 agreement that proposes of ARM company, and the AXI bus is a high bandwidth, and the bus of high transfer rate is widely used in embedded system.The signal definition of AXI_lite (simplifying the advanced extensive interface of version) bus protocol is referring to the inventor's application for a patent for invention CN200810116126.X.
Fig. 4 is the structured flowchart of the multi-channel DMA controller of another embodiment of the present invention; As shown in Figure 4; Each DMA passage comprises a data buffer-stored and control module and one group of control register; The EBI processing module of all DMA passages all is connected with a multiplexing module, and multiplexing module is connected with the bus arbitration module through an EBI of SOC(system on a chip).
As shown in Figure 4, multi-channel DMA controller is set up a plurality of DMA passages through a plurality of DMA interfaces.When the DMA request module belonged to identical clock zone with multi-channel DMA controller, storage of the data buffering of multi-channel DMA controller and control module thereof directly linked to each other with a plurality of DMA request module through DMA interface so; Perhaps when DMA request module clock zone and multi-channel DMA controller belong to different clock-domains; But the function that belongs to signal between DMA request module and the multi-channel DMA controller of different clock-domains is synchronously accomplished by independent DMA interface signal processing apparatus; Storage of data buffering in the multi-channel DMA controller and control module thereof are connected with outside independent DMA interface signal processing apparatus through a plurality of DMA interfaces so, are connected with a plurality of DMA request module through the DMA interface signal processing apparatus again.
As shown in Figure 4, the data buffering storage and the control module thereof of each DMA passage comprise the buffer-stored control module and first buffered memory module, and each DMA passage comprises one group of control register, is connected to data buffering storage and control module thereof.The explanation of buffer-stored control module, first buffered memory module and control register as previously mentioned.
As shown in Figure 4, the data buffering storage and the control module thereof of all DMA passages all are connected to multiplexing module.Multiplexing module is used for carrying out the signal of a plurality of DMA passages and data transmission to deliver to an external bus interface after multichannel is selected, and comprises that the bus arbitration module that the reading request signal that produces data buffering storage and control module thereof and written request signal are sent to external bus interface after multiplexed and then are sent to SOC(system on a chip) again carries out bus arbitration.The bus protocol that the EBI signal of multiplexing module output and external bus interface adopt is inconsistent, and the conversion of signals that can in EBI, export multiplexing module is the signal that meets bus protocol.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.
Claims (8)
1. direct memory access dma controller of hyperchannel; It is characterized in that; Said multi-channel DMA controller is connected with a plurality of DMA request module through a plurality of DMA interfaces respectively; And have only an EBI between the bus arbitration module of SOC(system on a chip), and the buffer storage unit in a plurality of DMA channels share multiplexing module; Said multi-channel DMA controller comprises:
A plurality of DMA channel modules, said each DMA channel module comprises:
Data buffering storage and control module thereof are used to carry out the DMA data transmission; Said data buffering storage and control module thereof comprise first buffered memory module and buffering storage control module; Said first buffered memory module is used for storing the data of DMA data transmission; The data that said buffer-stored control module is used to control from outside DMA request module write said first buffered memory module; And the data in said first buffered memory module are when reaching a constant volume; Produce written request signal, and be transferred to external bus interface to said written request signal through said multiplexing module; Also be used for controlling and deliver to outside DMA request module after reading the data of said first buffered memory module; And the data in said first buffered memory module are when reaching a constant volume; Produce reading request signal, and be sent to external bus interface to said reading request signal through said multiplexing module; And
The control register module comprises one group of control register, communicates by letter with said data buffering storage and control module thereof, is used for according to the pre-configured data of said control register the DMA data transmission of said data buffering storage and control module thereof being controlled;
Multiplexing module is communicated by letter with storage of data buffering in said each DMA channel module and control module thereof, is used for carrying out the signal of said a plurality of DMA channel modules and data to be connected to external bus interface after multiplexed.
2. multi-channel DMA controller according to claim 1 is characterized in that, said each DMA channel module also comprises:
The DMA interface signal processing module; Outside DMA request module is communicated by letter with said data buffering storage and control module thereof through said DMA interface signal processing module, and said DMA interface signal processing module is used for the DMA interface signal between synchronous said outside DMA request module and the said DMA interface signal processing module.
3. multi-channel DMA controller according to claim 1 and 2 is characterized in that, said each DMA channel module also comprises:
The EBI processing module; Data buffering storage and control module thereof in said each DMA channel module are communicated by letter with said multiplexing module through said EBI processing module, and said EBI processing module is used to change the signal between said buffer-stored and control module and the multiplexing module.
4. multi-channel DMA controller according to claim 1 is characterized in that, said first buffered memory module is the FIFO storer.
5. multi-channel DMA controller according to claim 1 is characterized in that, also comprises second buffered memory module in the said multiplexing module, is used for storing the data of DMA data transmission.
6. multi-channel DMA controller according to claim 5 is characterized in that, said second buffered memory module is the FIFO storer.
7. multi-channel DMA controller according to claim 3; It is characterized in that the signal of EBI processing module in said each channel module and the signal between the said multiplexing module and the output of said multiplexing module meets identical bus protocol.
8. multi-channel DMA controller according to claim 7 is characterized in that, said bus protocol is AHB, AXI or AXI_lite.
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| CN200910080751A CN101504633B (en) | 2009-03-27 | 2009-03-27 | Multi-channel DMA controller |
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| CN200910080751A CN101504633B (en) | 2009-03-27 | 2009-03-27 | Multi-channel DMA controller |
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| CN101504633B true CN101504633B (en) | 2012-09-05 |
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Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102063396A (en) * | 2009-11-18 | 2011-05-18 | 意法-爱立信公司 | Method and device for transmitting data between master blocks on chip and SOC (System on a Chip) |
| CN101937409B (en) * | 2010-09-02 | 2012-06-27 | 中国电子科技集团公司第三十八研究所 | Time-sharing multiplexing DMA (direct memory access) controller |
| CN102681525B (en) * | 2011-03-15 | 2014-07-30 | 安凯(广州)微电子技术有限公司 | Verification method and system for converter controller |
| CN102231142B (en) * | 2011-07-21 | 2013-12-11 | 浙江大学 | Multi-channel direct memory access (DMA) controller with arbitrator |
| CN103064808A (en) * | 2011-10-24 | 2013-04-24 | 北京强度环境研究所 | Priority adjustable multiple-channel direct memory access (DMA) controller |
| CN104639275B (en) * | 2013-11-11 | 2017-10-10 | 华为技术有限公司 | Multiplexer, Deplexing apparatus, method, Memory Controller Hub, internal memory and system |
| CN103678202B (en) * | 2013-11-26 | 2016-08-17 | 北京时代民芯科技有限公司 | A kind of dma controller of polycaryon processor |
| CN104461967B (en) * | 2014-12-25 | 2018-03-06 | 中国电子科技集团公司第三十八研究所 | It is a kind of to support synchronous and asynchronous transfer mode parallel data grabbing card |
| CN104717433A (en) * | 2015-03-27 | 2015-06-17 | 电子科技大学 | Distributed transmission device for video stream signal processing system |
| CN107391023B (en) * | 2016-05-16 | 2021-01-22 | 深圳市中兴微电子技术有限公司 | Multi-channel data memory and access method and device thereof |
| DE102016211768A1 (en) * | 2016-06-29 | 2018-01-04 | Robert Bosch Gmbh | Memory direct access control device and method of operation therefor |
| CN107783927B (en) * | 2016-08-30 | 2020-11-20 | 安凯(广州)微电子技术有限公司 | Circuit conversion system and method for connecting AXI interface and DMA interface |
| US10241946B2 (en) * | 2017-01-18 | 2019-03-26 | Nxp Usa, Inc. | Multi-channel DMA system with command queue structure supporting three DMA modes |
| CN106951388B (en) * | 2017-03-16 | 2020-06-30 | 湖南博匠信息科技有限公司 | PCIe-based DMA data transmission method and system |
| CN108959107B (en) * | 2017-05-18 | 2020-06-16 | 深圳市中兴微电子技术有限公司 | Sharing method and device |
| CN109992205B (en) * | 2019-03-27 | 2020-06-02 | 无锡海斯凯尔医学技术有限公司 | Data storage device, method and readable storage medium |
| TWI739227B (en) * | 2019-12-03 | 2021-09-11 | 智成電子股份有限公司 | System-on-chip module to avoid redundant memory access |
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| CN1967713A (en) * | 2006-11-27 | 2007-05-23 | 华为技术有限公司 | High-capacity cache memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1967713A (en) * | 2006-11-27 | 2007-05-23 | 华为技术有限公司 | High-capacity cache memory |
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