CN101470459B - Low-voltage low-power consumption CMOS voltage reference circuit - Google Patents
Low-voltage low-power consumption CMOS voltage reference circuit Download PDFInfo
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- CN101470459B CN101470459B CN2007103042190A CN200710304219A CN101470459B CN 101470459 B CN101470459 B CN 101470459B CN 2007103042190 A CN2007103042190 A CN 2007103042190A CN 200710304219 A CN200710304219 A CN 200710304219A CN 101470459 B CN101470459 B CN 101470459B
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Abstract
The invention discloses a low-voltage low-power-consumption CMOS voltage reference circuit, which is used for generating a voltage reference. The CMOS voltage reference circuit comprises a starting circuit 11, a self-bias current source 12, a voltage generator 13 with negative temperature coefficient, a voltage reference regulator 14 and a single-tube current mirror MOS transistor M0. The CMOS voltage reference circuit adopts an MOS transistor operating at a sub-threshold area to generate a voltage with negative temperature coefficient, utilizes a sleeve and a folded structure of the MOS transistor operating at the sub-threshold area to substitute a resistance for amplifying a voltage with positive temperature coefficient, thereby offsetting the voltage with positive temperature coefficient by the voltage with negative temperature coefficient, and generating a temperature-independent voltage reference. The CMOS voltage reference circuit eliminates the use of passive devices and an operation amplifier, wherein the passive devices relate to a resistance, a capacitor and the like, thereby greatly reducing the component number of the circuit and the static operating current, and reducing the power consumption and the area of the circuit.
Description
Technical field
The present invention relates to the cmos voltage reference circuit and the production method thereof in reference circuit engineering field, particularly a kind of low-voltage and low-power dissipation.
Background technology
The reference voltage reference circuit is one of component units indispensable in many mimic channels and the Design of Digital Circuit.Reference source is widely used in the various analog-and digital-circuit owing to the characteristic of its low-temperature coefficient and low supply voltage dependence.
The circuit that traditional band gap reference utilization is directly proportional with absolute temperature is offset the negative temperature characteristic of bipolar transistor base-launch site knot, and output voltage is generally about the band gap voltage 1.25V of silicon.And along with the progress of deep submicron integrated circuit technology, at present main flow or be about to become main flow CMOS technology supply voltage near in addition be lower than 1.25V, seriously like this limited the application of band-gap reference circuit in deep submicron process.
In addition, because passive devices such as traditional band-gap reference employing resistance carry out the baric flow conversion and amplify the voltage with positive temperature coefficient (PTC), make its can with the bipolar transistor base-launch site voltage offset with negative temperature coefficient, and area and saving chip cost in order not take main circuit, these resistance values often are limited within the acceptable scope, also there is a lower limit in the working current of reference circuit like this, makes that the low power dissipation design of reference circuit is difficult unusually.
And along with the develop rapidly of handheld mobile device industry, the Analog Circuit Design of low supply voltage and low-power consumption is just becoming the focus of research.(supply voltage of low-power consumption chip in 2007 will be low to moderate 0.8V for Semiconductor Industry Association, the prediction of SIA) making according to international semiconductor TIA.In addition, the also rapid increase of the cost of chip along with the progress of deep submicron process, these factors have all proposed stern challenge to the design of reference source.
Be that example further specifies the low-voltage and low-power dissipation difficult problem that present benchmark technology is faced with the bandgap voltage reference circuit of generally acknowledging now.The circuit that traditional bandgap voltage reference circuit utilization is directly proportional with absolute temperature is offset the negative temperature characteristic of bipolar transistor base-launch site voltage, thereby obtains constant reference voltage, and output voltage values is generally about the band gap voltage 1.25V of silicon.And bandgap reference voltage can keep stable in the operating temperature range of different supply voltages and process conditions and broad.
In traditional band-gap reference circuit, the general difference that adopts the base that recently amplifies two bipolar transistors-launch site voltage of two different resistance values, the temperature coefficient of itself and single bipolar transistor base-launch site voltage is offseted, obtained having the reference voltage of zero-temperature coefficient like this.
Because the base-launch site voltage of bipolar transistor has negative temperature coefficient, generally speaking, this temperature coefficient is approximately-1.5mV/ ℃.When two bipolar transistors are operated under the unequal current density, the difference of their base-launch site voltage just is directly proportional with absolute temperature, and the temperature coefficient of described voltage is directly proportional with the natural logarithm of their conduction region area.
The ratio of supposing described bipolar transistor conduction region area is 8, and then this temperature coefficient is approximately 0.18mV/ ℃, is 1/8th of the absolute value of the negative temperature coefficient of the base-launch site voltage of above-mentioned bipolar transistor.
The ratio of supposing described bipolar transistor conduction region area again is 48, and then this temperature coefficient is approximately 0.34mV/ ℃, is 1/4th of the absolute value of the negative temperature coefficient of the base-launch site voltage of above-mentioned bipolar transistor.As seen the ratio that only relies on the conduction region area that increases bipolar transistor is difficult to reach the needed gain of reference circuit.
In order to obtain the reference voltage of zero-temperature coefficient, the positive temperature coefficient (PTC) of the difference of the base-launch site voltage of two bipolar transistors of necessary amplification can offset it with the voltage of negative temperature coefficient.Traditional bandgap voltage reference circuit is to adopt the ratio of resistance that this gain is provided, and the use of resistance has increased the power consumption and the area of chip.
In addition, the resistance that provides in the CMOS technology has certain temperature coefficient, thereby influence the performance of output reference voltage, and the Resistance model for prediction general precision that technology manufacturer provides is lower, and therefore traditional bandgap voltage reference circuit performance often is subject to the performance of resistance and the levels of precision of model.
The factor that the reference voltage circuit design must be considered is required size of its circuit or chip area.Usually, the size of reference voltage circuit is decided by the main circuit design of integrated circuit.If can eliminate passive devices such as resistance, reduce the required area of reference voltage circuit, help to make the circuit chip area to minimize or increase to supply the used area of main circuit design, thereby reduce chip cost.
In addition, the general Power Supply Rejection Ratio that adopts operation transconductance amplifier to improve circuit in traditional band-gap reference circuit, but the thing followed can be brought the consideration of circuit stability aspect.Because reference circuit is had relatively high expectations to stability, in order to reach the requirement of high stability, the general electric capacity of introducing in band-gap reference circuit carries out the phase compensation of loop.Extra electric capacity has not only increased the area of circuit, and has reduced the speed of reference circuit greatly.
If can design the voltage reference circuit of passive elements such as realizing need not resistance, electric capacity even operation transconductance amplifier, then can reduce its component number and area greatly, thereby reduce the power consumption and the cost of reference circuit.
Summary of the invention
(1) technical matters that will solve
In view of this, fundamental purpose of the present invention is to provide a kind of cmos voltage reference circuit of low-voltage and low-power dissipation, to reduce the number and the area of forming circuit element, reduces the power consumption and the cost of reference circuit.
(2) technical scheme
In order to achieve the above object, technical scheme of the present invention is achieved in that
A kind of cmos voltage reference circuit of low-voltage and low-power dissipation, be used to produce a reference voltage, this cmos voltage reference circuit comprises a start-up circuit 11, one self-bias current source 12, one has the voltage generator 13 of negative temperature coefficient, one reference voltage regulator 14, and a single tube current mirror MOS transistor M
0
Wherein, described start-up circuit 11 is by transistor M
S0, M
S1And M
S2Constitute; Wherein, PMOS transistor M
S0With nmos pass transistor M
S1Form a basic inverter module, M
S0, M
S1The leakage level be connected respectively with the grid level, source class then respectively with reference power source with reference to ground be connected; Transistor M
S0And M
S1The inverter module of forming has an input port and an output port, and wherein input port is M
S0And M
S1The direct Coupling point of grid level, simultaneously with described self-bias current source 12 in transistor M
C3The grid level directly be connected; Output port is M
S0And M
S1Direct-coupled leakage level is with M
S2The leakage level be connected; P channel enhancement MOS transistor M
S2The grid level and the transistor M in the described self-bias current source 12
C1The grid level directly be connected, source class then with reference to ground be connected;
Described self-bias current source 12 comprises MOS transistor M
C0To M
C6This unit comprises three branch roads, respectively by the direct-coupled PMOS transistor of grid level M
C0, M
C1And M
C2Provide bias current, transistor M
C0To M
C2Source class be connected M with reference power source
C1The grid level with leak level and be connected; PMOS transistor M
C2With nmos pass transistor M
C3Form article one branch road, M
C3The grid level and leak level and M
C2The leakage level directly be connected, source class then with reference to ground be connected; PMOS transistor M
C1With nmos pass transistor M
C4Form the second branch road, M
C4Leakage level and M
C1The leakage level be connected grid level and nmos pass transistor M
C3The grid level directly be coupled, source class then with the 3rd branch road in M
C6The leakage level be connected; PMOS transistor M
C0With nmos pass transistor M
C5, M
C6Form the 3rd branch road, M
C5The grid level and leak level, M
C0Leakage level and M
C6The grid level directly be coupled M
C6The leakage level then with M
C5Source class and M
C4Source class be connected, source class directly with reference to is connected;
Described negative temperature coefficient voltage generator 13 is by nmos pass transistor M
1Constitute, the leakage level of this pipe is connected with the grid level, and with the M of reference voltage regulator 14
2, M
3The grid level and leak level and PMOS transistor M
0The leakage level directly be coupled, source class with reference to ground be connected;
Described reference voltage regulator 14 comprises nmos pass transistor M
2To M
5And transistor calibration arrays M
5aTo M
5c, M wherein
2And M
3The grid level and leak level totally four ports and M
0The leakage level directly be coupled; Transistor M
4The grid level and leak level and be directly coupled to M
5The grid level, M
4To M
5Leakage level and M
2To M
3Source class be connected respectively, source class then with reference to ground be connected; M
3Source class be the output port of circuit; Described transistor M
5aTo M
5cLeakage level and M
5The leakage level directly be coupled, the grid level then inserts switching tube S respectively
5aTo S
5c, the other end of switching tube and M
5The grid level be connected.M
5aTo M
5cThe grid level by other one group of switching tube with directly be connected with reference to ground, source class then directly with reference to is connected;
Described transistor M
0The grid level be connected with the grid level of self-bias current source 12, source class is connected with the reference power source of circuit, the source class of M3 is the output port of circuit.
(3) beneficial effect
From technique scheme as can be seen, the present invention has following beneficial effect:
1, the cmos voltage reference circuit of this low-voltage and low-power dissipation provided by the invention, the transistor for generating that utilization is operated in the subthreshold value workspace has the voltage of negative temperature coefficient, greatly reduce the voltage of bipolar transistor base-emitter in traditional band-gap reference circuit like this, the supply voltage of circuit can be reduced to 0.7V, break through the supply voltage restriction of traditional band-gap reference circuit.
2, the cmos voltage reference circuit of this low-voltage and low-power dissipation provided by the invention, the resistance that utilizes other transistor sleeve that is operated in the subthreshold value workspace and foldable structure to replace in traditional band-gap reference circuit amplifies the voltage with positive temperature coefficient (PTC), eliminated the use of resistance, thereby obtained low-power consumption, the bandgap voltage reference circuit of high integration.
3, the cmos voltage reference circuit of this low-voltage and low-power dissipation provided by the invention, also eliminated the use of operation transconductance amplifier, so just do not need electric capacity to come the phase margin of compensation loop, reduced the area of circuit, compared with traditional bandgap voltage reference circuit and have lower power consumption and cost.
4, the cmos voltage reference circuit of this low-voltage and low-power dissipation provided by the invention, the MOS transistor that employing is operated in sub-threshold region produces the voltage with negative temperature coefficient, utilize the sleeve and the foldable structure of the MOS transistor that is operated in sub-threshold region to replace resistance to amplify voltage simultaneously with positive temperature coefficient (PTC), itself and the voltage with negative temperature coefficient are offseted, thereby produced temperature independent reference voltage.
5, the cmos voltage reference circuit of this low-voltage and low-power dissipation provided by the invention, because reference circuit has been eliminated the use of passive device such as resistance, electric capacity and operational amplifier, reduce the component number and the static working current of circuit greatly, thereby reduced the power consumption and the area of circuit.
Description of drawings
Fig. 1 is the circuit diagram according to low-voltage and low-power dissipation voltage reference circuit of the present invention;
Fig. 2 is the temperature characteristics figure of low-voltage and low-power dissipation voltage reference circuit output reference voltage shown in Figure 1;
Fig. 3 is that low-voltage and low-power dissipation voltage reference circuit output reference voltage shown in Figure 1 is with the mains voltage variations curve map.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
As shown in Figure 1, Fig. 1 is the circuit diagram according to low-voltage and low-power dissipation voltage reference circuit of the present invention, this cmos voltage reference circuit comprises a start-up circuit 11, one self-bias current source 12, one has voltage generator 13, a reference voltage regulator 14 of negative temperature coefficient, and a single tube current mirror MOS transistor M
0
Wherein, described start-up circuit 11 is by transistor M
S0, M
S1And M
S2Constitute; Wherein, PMOS transistor M
S0With nmos pass transistor M
S1Form a basic inverter module, M
S0, M
S1The leakage level be connected respectively with the grid level, source class then respectively with reference power source with reference to ground be connected; Transistor M
S0And M
S1The inverter module of forming has an input port and an output port, and wherein input port is M
S0And M
S1The direct Coupling point of grid level, simultaneously with described self-bias current source 12 in transistor M
C3The grid level directly be connected; Output port is M
S0And M
S1Direct-coupled leakage level is with M
S2The leakage level be connected; P channel enhancement MOS transistor M
S2The grid level and the transistor M in the described self-bias current source 12
C1The grid level directly be connected, source class then with reference to ground be connected.
Described self-bias current source 12 comprises MOS transistor M
C0To M
C6This unit comprises three branch roads, respectively by the direct-coupled PMOS transistor of grid level M
C0, M
C1And M
C2Provide bias current, transistor M
C0To M
C2Source class be connected M with reference power source
C1The grid level with leak level and be connected; PMOS transistor M
C2With nmos pass transistor M
C3Form article one branch road, M
C3The grid level and leak level and M
C2The leakage level directly be connected, source class then with reference to ground be connected; PMOS transistor M
C1With nmos pass transistor M
C4Form the second branch road, M
C4Leakage level and M
C1The leakage level be connected grid level and nmos pass transistor M
C3The grid level directly be coupled, source class then with the 3rd branch road in M
C6The leakage level be connected; PMOS transistor M
C0With nmos pass transistor M
C5, M
C6Form the 3rd branch road, M
C5The grid level and leak level, M
C0Leakage level and M
C6The grid level directly be coupled M
C6The leakage level then with M
C5Source class and M
C4Source class be connected, source class directly with reference to is connected.
Described negative temperature coefficient voltage generator 13 is by nmos pass transistor M
1Constitute, the leakage level of this pipe is connected with the grid level, and with the M of reference voltage regulator 14
2, M
3The grid level and leak level and PMOS transistor M
0The leakage level directly be coupled, source class with reference to ground be connected.
Described reference voltage regulator 14 comprises nmos pass transistor M
2To M
5And transistor calibration arrays M
5aTo M
5c, M wherein
1To M
3The grid level and leak level totally six ports and M
0The leakage level directly be coupled; Transistor M
4The grid level and leak level and be directly coupled to M
5The grid level, M
4To M
5Leakage level and M
2To M
3Source class be connected respectively, source class then with reference to ground be connected; M
3Source class be the output port of reference voltage circuit; Described transistor M
5aTo M
5cLeakage level and M
5The leakage level directly be coupled, the grid level then inserts switching tube S respectively
5aTo S
5c, the other end of switching tube and M
5The grid level be connected.M
5aTo M
5cThe grid level by other one group of switching tube with directly be connected with reference to ground, source class then directly with reference to is connected.
Described transistor M
0The grid level be connected with the grid level of self-bias current source 12, source class is connected with the reference power source of circuit, the source class of M3 is the output port of circuit.
The present invention also provides a kind of method that is used to produce reference voltage, may further comprise the steps:
When voltage reference circuit powered on, start-up circuit 11 started self-bias current source 12;
Self-bias current source 12 provides direct current biasing for voltage generator 13 and the reference voltage regulator 14 with negative temperature coefficient;
Voltage generator 13 and reference voltage regulator 14 with negative temperature coefficient produce a reference voltage with negative temperature coefficient respectively, the temperature coefficient approximately equal of its temperature coefficient and MOS transistor threshold voltage, the difference of temperature coefficient are the voltage with positive temperature coefficient (PTC);
Two differences with reference voltage of negative temperature coefficient that produce are amplified by reference voltage regulator 14, and its temperature coefficient is adjusted to suitable value by the MOS transistor of sleeve and foldable structure;
The reference voltage addition with negative temperature coefficient with value after regulating and reference voltage regulator 14 generations can obtain reference voltage.
In conjunction with Fig. 1 reference voltage circuit of the present invention is carried out detailed explanation more below.
Auto bias circuit in the described voltage reference circuit adopts the current source structure that adopts in the document " E.M.Camacho-Galeano; C.Galup-Montoro; M.C.Schneider; " CMOS CurrentReference Without Resistance, " IEEE Trans.Circuits and System II, vol.52; no.2; pp.61-65, Feb., 2005. ".Provide the temperature characterisitic of electric current in order to obtain this current source, the present invention has following derivation:
Because transistor M
C1And M
C2Be operated in the saturation region, therefore have:
I
MC3/I
MC4＝S
MC2/S
MC1 (1)
Wherein S is the channel width and the length ratio of MOS transistor, simultaneously because transistor M
C3, M
C4Be operated in sub-threshold region, then have:
I
MC3＝uC
dV
T 2×S
MC3×exp((V
31-V
th，MC3)/(r×V
T)) (2)
I
MC4＝uC
dV
T 2×S
MC4×exp((V
31-V
32-V
th，MC4)/(r×V
T))(3)
In described formula (2) and (3), I is for flowing through transistorized electric current, and B equals the mobility that transistor u is a minority carrier, C
dBe the depletion-layer capacitance under the grid, V
TBe thermal voltage, equal 26mV, V at normal temperatures
ThBe the threshold voltage of MOS transistor, r is the subthreshold value slope factor, V
31, V
32Be the magnitude of voltage of node 31,32, above-mentioned two formulas be transformed into:
r×V
T×ln(I
M3/(uC
dV
T 2S
M3))＝V
31-V
th，MC3 (4)
r×V
T×ln(I
M4/(uC
dV
T 2S
M4))＝V
31-V
32-V
th，MC4 (5)
(3) formula-(4) formula can get:
(4)-(5), bring (1) formula again into, can get:
V
32＝r×V
T×ln((S
MC2×S
MC4)/(S
MC3×S
MC1)) (6)
Because M
C5Be operated in the saturation region, M
C6Be operated in linear zone, at this moment have:
I
MC5＝0.5×B
MC5×S
MC5(V
33-V
32-V
TH，MC5)
2 (7)
I
MC6＝r×B
MC6×S
MC6×V
32×(V
33-V
TH，MC6-0.5×r×V
32)(8)
Wherein B equals the product of u and Cox, and u is the mobility of charge carrier rate, and Cox is the specific capacitance of grid oxide layer, and (7) formula is transformed into:
V
33-V
TH，MC5＝SQRT(2×I
MC5/B
MC5/S
MC5)+V
32 (9)
SQRT () is a square root function, brings (9) formula into (8) formula, has simultaneously:
I
MC6＝(1+S
MC1/S
MC0)×I
MC5 (10)
Can get:
(1+S
MC1/S
MC0)×I
MC5＝r×S
MC6×B
MC6×V
32(SQRT(2×I
MC5/B
MC5/S
MC5)-(0.5×r-1)×V
32) (11)
Arrangement formula (11) obtains an I
MC5Be the linear equation in two unknowns of unknown number, can obtain through after the conversion of a series of complexity:
I
MC5＝S
MC6×V
31 2×(SQRT(2×S
MC6/S
MC5)+SQRT(2×r
2×S
MC6/S
MC5-4×(1+S
MC1/S
MC0)×r×(0.5×r-1)))2/4/(1+S
MC1/S
MC0)
2 (12)
Because formula (12) is too complicated, in order to simplify the calculating of back, because transistorized mobility is directly proportional with the m power of temperature, m is the temperature factor of mobility, approximates-1.5, and V
31Be directly proportional with the first power of temperature, so we with (12) equivalence are:
I
MC5～T
(2+m) (13)
Obtain the M that flows through thus
C5Electric current differential form as shown in the formula:
d(I
MC5)/dT＝(2+m)/T×I
MC5 (14)
Described voltage reference circuit adopts the MOS transistor that is operated in sub-threshold region to replace bipolar transistor to produce the voltage with negative temperature characteristic.As shown in Figure 1, MOS transistor M
1Be operated in sub-threshold region, when flowing through M
1Enough hour of electric current, V is arranged this moment
31≈ V
Th, M1, concrete derivation is as described below:
Transistor M
1Be operated in weak inversion regime, and when its gate source voltage approached threshold voltage, the E.K.V model by MOS transistor had:
I
M1＝2×r×S
M1×u
0×(T/T
0)m×C
ox×V
T 2×(ln(1+exp((V
21-V
th)/2/r/V
T)))
2
(15)
u
0Carrier mobility during for normal temperature is simultaneously according to transistor M
4Be operated in dark sub-threshold region, then have:
IM4＝2×r×S
M4×u
0×(T/T
0)M×C
ox×V
T 2×exp((V
22-V
th)/r/V
T) (16)
Because the image current pipe M of self-bias current source (12)
0Offer voltage generator (13) and reference voltage regulator (14) direct current biasing, then have with negative temperature coefficient:
I
M1+(1+S
M5/S
M4)×I
M4＝I
M0 (17)
Deduct formula (17) by formula (13), the temperature coefficient that obtains node 21 is:
dV
21/dT＝((1+A)×k+(1+A/(1+r))×(V
21-V
th，M1)/T-r×A/(1r)×V
th，M1/T)/(1+A/(1+r)) (18)
Wherein k is the temperature coefficient of threshold voltage, and A equals:
A＝(I
M0/I
M1-1)(1+exp((V
21-V
TH，M1)/2/r/V
T))ln(1+exp((V
21-V
th，m1)/2/r/VT))
(19)
Formula (19) formula is too complicated, but when flowing through M
1Electric current much smaller than the M that flows through
2And M
3Electric current sum and V
21Less than M
1Threshold voltage V
THThe time, formula (18) can become by abbreviation:
dV
21/dT≈k (20)
K in the formula (20) is the temperature coefficient of threshold voltage and is constant, so the voltage of node 21 approximates metal-oxide-semiconductor M
1Threshold voltage and temperature coefficient for negative.
Consider the transistor M that flows through
2And M
4Electric current equate then to have:
I
M2＝uC
dV
T 2S
M2×exp((V
21-V
22-V
th，M2)/(r×V
T)) (21)
I
M4＝uC
dV
T 2S
M3×exp((V
22-V
th，M3)/(r×V
T)) (22)
C in the formula
dBe the electric capacity of depletion layer, so have:
V
22＝(V
th，M1-r×V
T×ln(S
4/S
2))/(1+r) (23)
Consider transistor M again
2, M
3Situation, down two formulas are arranged:
I
M2＝uC
dV
T 2S
M2×exp((V
21-V
22-|V
th，M2|)/(r×V
T)) (21)
I
M3＝uC
dV
T 2S
M3×exp((V
21-V
23-|V
th，M3|)/(r×V
T)) (22)
And have: I
M2/ I
M3=S
M4/ S
M5(23)
Association type (20)-(22) finally obtain:
V
23＝V
TH，M1/(1+r)+V
T×ln(S
M3/S
M5×SQRT(S
M4/S
M2)) (24)
And node 23 is exactly an output reference voltage.
The purpose of start-up circuit is that DC channel is provided when powering on for system, eliminates the degeneracy point, described in " analog cmos integrated circuit (IC) design " that its principle is shown with Behzad Razavi.And transistor M
5A-M
5CPurpose be to overcome technology to float, finish laggard trip temperature coefficient calibration at chip, improved the performance of reference circuit like this.
The present invention adopts the transistorized gate source voltage that is operated in sub-threshold region to replace the base-emitter voltage of bipolar transistor in traditional band-gap reference circuit to produce the voltage with negative temperature characteristic, the temperature coefficient of this voltage has only 1/3rd of bipolar transistor base-emitter voltage, has reduced to provide the difficulty of negative temperature coefficient voltage gain in the reference circuit so greatly.
For the gain of difference that two transistorized gate source voltages that are operated in sub-threshold region are provided, circuit of the present invention adopts transistorized sleeve and the foldable structure (M that is operated in sub-threshold region
2, M
3And M
4) realize, thereby reduced the lower limit of reference circuit supply voltage.
Model with UMC 0.18um CMOS mixed signal technology is an example, according to above-mentioned derivation, the output current of current source is 0.8 to receive ampere, according to above-mentioned derivation, the channel length and the width that calculate M1 are respectively 40u and 3u, the channel length of M2 and M3 and width are respectively 1u/2u and 1u/48u, M4 and M5 channel length and width are respectively 0.5u/8u and 0.5u/6u, the temperature characteristics figure of the reference circuit of emulation this moment as shown in Figure 2, temperature coefficient is 25ppm/ ℃ between-20 ℃ to 120 ℃, ppm represents 1,000,000/, reference circuit can be worked under 3V at 0.63V, the about 227mV of output reference voltage, 0.004 square millimeter of domain area occupied, only consumed the dc power of 36nW under the operating voltage of 0.7V, this is the voltage reference reference circuit of the minimum work power consumption of present report.Owing to need not any operational amplifier, make the Power Supply Rejection Ratio of this circuit a little less than traditional band-gap reference circuit, Power Supply Rejection Ratio is-46dB at frequency 10Hz place.
So far, be appreciated that the voltage reference circuit of this low-voltage and low-power dissipation provided by the invention.For MOS transistor, when leakage current remains unchanged, be operated in transistorized gate source voltage approximately linear reduction within the specific limits of weak inversion regime along with the rising of temperature.Utilize this characteristic, the present invention adopts the MOS transistor that is operated in sub-threshold region to produce the voltage with negative temperature coefficient, utilize the sleeve and the foldable structure of the MOS crystal that is operated in sub-threshold region to replace resistance to amplify voltage simultaneously with positive temperature coefficient (PTC), itself and the voltage with negative temperature coefficient are offseted, thereby produced temperature independent reference voltage.Reference circuit of the present invention has been owing to eliminated the use of passive device such as resistance, electric capacity and operational amplifier, thereby reduced the power consumption and the area of circuit greatly.
Fig. 2 is the temperature characteristics figure of low-voltage and low-power dissipation voltage reference circuit output reference voltage shown in Figure 1.The figure shows the fluctuation of institute's invention circuit output voltage with variation of ambient temperature, temperature range is-20 ℃ to 120 ℃, in this temperature range, voltage changes between 0.226V and 0.227V, temperature coefficient in the relevant temperature scope is 25ppm/ ℃, ppm represents 1,000,000/, institute's invention circuit has only consumed the dc power of 36nW under the operating voltage of 0.7V.
Fig. 3 is that low-voltage and low-power dissipation voltage reference circuit output reference voltage shown in Figure 1 is with the mains voltage variations curve map.The technology that adopts is with described in Fig. 2.Response when the figure shows output reference voltage and from 0V to 5V, changing with supply voltage.When supply voltage rises from 0V, output reference voltage is also along with rising; When supply voltage was elevated to 0.7V, output reference voltage rose to 0.227V, and kept substantially constant subsequently, until supply voltage rises to 3.5V; When supply voltage continued to raise, output reference voltage also broke away from stable work area thereupon, and beginning raises faster.In the mains voltage variations scope of 3.5V, voltage changes in (under the room temperature) between 0.227V and the 0.238V at 0.7V, and amplitude of variation is 11mV, and the supply voltage rejection coefficient is 4mV/V.
Above-described specific embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is specific embodiments of the invention; be not limited to the present invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (1)
1. the cmos voltage reference circuit of a low-voltage and low-power dissipation, be used to produce a reference voltage, it is characterized in that, this cmos voltage reference circuit comprises a start-up circuit (11), one self-bias current source (12), one has the voltage generator (13) of negative temperature coefficient, a reference voltage regulator (14), and a single tube current mirror MOS transistor M
0
Wherein, described start-up circuit (11) is by transistor M
S0, M
S1And M
S2Constitute; Wherein, PMOS transistor M
S0With nmos pass transistor M
S1Form a basic inverter module, M
S0, M
S1The leakage level be connected respectively with the grid level, source class then respectively with reference power source with reference to ground be connected; Transistor M
S0And M
S1The inverter module of forming has an input port and an output port, and wherein input port is M
S0And M
S1The direct Coupling point of grid level, simultaneously with described self-bias current source (12) in transistor M
C3The grid level directly be connected; Output port is M
S0And M
S1Direct-coupled leakage level is with M
S2The leakage level be connected; P channel enhancement MOS transistor M
S2The grid level and the transistor M in the described self-bias current source (12)
C1The grid level directly be connected, source class then with reference to ground be connected;
Described self-bias current source (12) comprises MOS transistor M
C0To M
C6This unit comprises three branch roads, respectively by the direct-coupled PMOS transistor of grid level M
C0, M
C1And M
C2Provide bias current, transistor M
C0To M
C2Source class be connected M with reference power source
C1The grid level with leak level and be connected; PMOS transistor M
C2With nmos pass transistor M
C3Form article one branch road, M
C3The grid level and leak level and M
C2The leakage level directly be connected, source class then with reference to ground be connected; PMOS transistor M
C1With nmos pass transistor M
C4Form the second branch road, M
C4Leakage level and M
C1The leakage level be connected grid level and nmos pass transistor M
C3The grid level directly be coupled, source class then with the 3rd branch road in M
C6The leakage level be connected; PMOS transistor M
C0With nmos pass transistor M
C5, M
C6Form the 3rd branch road, M
C5The grid level and leak level, M
C0Leakage level and M
C6The grid level directly be coupled M
C6The leakage level then with M
C5Source class and M
C4Source class be connected, source class directly with reference to is connected;
Described negative temperature coefficient voltage generator (13) is by nmos pass transistor M
1Constitute, the leakage level of this pipe is connected with the grid level, and with the M of reference voltage regulator (14)
2, M
3The grid level and leak level and PMOS transistor M
0The leakage level directly be coupled, source class with reference to ground be connected;
Described reference voltage regulator (14) comprises nmos pass transistor M
2To M
5And transistor calibration arrays M
5aTo M
5c, M wherein
2And M
3The grid level and leak level totally four ports and M
0The leakage level directly be coupled; Transistor M
4The grid level and leak level and be directly coupled to M
5The grid level, M
4To M
5Leakage level and M
2To M
3Source class be connected respectively, source class then with reference to ground be connected; M
3Source class be the output port of circuit; Described transistor M
5aTo M
5cLeakage level and M
5The leakage level directly be coupled, the grid level then inserts switching tube S respectively
5aTo S
5c, the other end of switching tube and M
5The grid level be connected; M
5aTo M
5cThe grid level by other one group of switching tube with directly be connected with reference to ground, source class then directly with reference to is connected;
Described transistor M
0The grid level be connected with the grid level of self-bias current source (12), source class is connected with the reference power source of circuit, the source class of M3 is the output port of circuit.
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| CN2007103042190A CN101470459B (en) | 2007-12-26 | 2007-12-26 | Low-voltage low-power consumption CMOS voltage reference circuit |
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|---|---|---|---|
| CN2007103042190A CN101470459B (en) | 2007-12-26 | 2007-12-26 | Low-voltage low-power consumption CMOS voltage reference circuit |
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| CN101470459B true CN101470459B (en) | 2011-06-08 |
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