CN101459116B - Shallow groove isolation construction manufacturing method - Google Patents
Shallow groove isolation construction manufacturing method Download PDFInfo
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- CN101459116B CN101459116B CN2007100945699A CN200710094569A CN101459116B CN 101459116 B CN101459116 B CN 101459116B CN 2007100945699 A CN2007100945699 A CN 2007100945699A CN 200710094569 A CN200710094569 A CN 200710094569A CN 101459116 B CN101459116 B CN 101459116B
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Abstract
A manufacturing method of a shallow trench isolation structure comprises steps of providing a semiconductor substrate, sequentially forming a pad silicon oxide layer and a hard mask layer on the semiconductor substrate, arranging a trench in the semiconductor substrate and openings corresponding to the position of the trench in the pad silicon oxide layer and the hard mask layer, providing an insulation layer in the trench and the openings and on the hard mask layer, removing the insulation layer on the hard mask layer through the flattening process, executing annealing process on the insulation layer in the trench and the openings, and finally removing the hard mask layer and the pad silicon oxide layer. The manufacturing method of a shallow trench isolation structure can reduce or eliminate the weak point.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of manufacture method of fleet plough groove isolation structure.
Background technology
Along with the semiconductor integrated circuit manufacturing technology to high-tech node development, the isolation technology between semiconductor device and the device also by original silicon carrying out local oxide isolation (Local Oxidation ofSilicon, LOCOS) develop into shallow trench isolation from.Shallow trench isolation is from by forming groove on Semiconductor substrate, and the technology of fill insulant forms in groove.Publication number is the manufacture method that the Chinese patent application file of CN 1649122A discloses a kind of fleet plough groove isolation structure.Fig. 1 to Fig. 7 is each step corresponding structure generalized section of manufacture method of the disclosed fleet plough groove isolation structure of described Chinese patent application file.
As shown in Figure 1, Semiconductor substrate 12 is provided, on described Semiconductor substrate 12, form pad oxide (Pad Oxide) 12A, then on described pad oxide 12A, form silicon nitride layer 14, on described silicon nitride layer 14, form the second hard mask layer 14B, form photoresist layer 16A on the described second hard mask layer 14B, the described photoresist layer 16A of patterning forms the opening 16B that the described second hard mask layer 14B is exposed in the bottom.
As shown in Figure 2, the second hard mask layer 14B, silicon nitride layer 14 and the pad oxide 12A of the described opening 16B of etching bottom form opening 16C, and the surface of described Semiconductor substrate 12 is exposed in the bottom of described opening 16C.
As shown in Figure 3, remove described photoresist layer 16A, the Semiconductor substrate 12 of the described opening 16C of etching bottom forms groove 18 in described Semiconductor substrate 12.
Then, as shown in Figure 4, form pad silicon oxide layer (LinearOxide) 20 on described groove 18 surfaces.
As shown in Figure 5, silicon oxide layer deposited 22 in described groove 18.Carry out the annealing in process that is about 500 to 1100 degree then, to discharge the stress that depositing operation produces.
As shown in Figure 6, remove the described second hard mask layer 14B by cmp and go up unnecessary silicon oxide layer 22 and the described second hard mask layer 14B.
Remove described silicon nitride layer 14 and pad oxide 12A by wet etching, form fleet plough groove isolation structure as shown in Figure 7.
Yet, in the manufacture method of described fleet plough groove isolation structure, after finishing cmp, can make the adhesion characteristics variation of the interface of oxide layer 22 and silicon nitride layer 14, can produce cavity (Weak Point) defective at intersection, cavity blemish 50 as shown in Figure 8, described cavity blemish is exaggerated in the technology of follow-up removal silicon nitride layer 14 and pad oxide 12A, thereby can form depression at the edge of the fleet plough groove isolation structure that forms, reduce insulation property, and produce other parasitic effectiveness, the electrical stability of the semiconductor device that influence forms.
Summary of the invention
The invention provides a kind of manufacture method of fleet plough groove isolation structure, the manufacture method of fleet plough groove isolation structure of the present invention can reduce or eliminate cavity blemish.
The manufacture method of a kind of fleet plough groove isolation structure provided by the invention comprises:
Semiconductor substrate is provided, on described Semiconductor substrate, is formed with pad silicon oxide layer and hard mask layer successively; In described Semiconductor substrate, have groove, in described pad silicon oxide layer and hard mask layer, have opening with the corresponding position of groove; In described groove, opening and on the hard mask layer, has insulating barrier; Remove insulating barrier on the described hard mask layer by flatening process; After finishing described flatening process, the insulating barrier in described groove and the opening is carried out annealing process;
Remove described hard mask layer and pad silicon oxide layer.
Optionally, describedly be annealed into the annealing of rapid thermal annealing or boiler tube.
Optionally, described annealing is carried out in nitrogen or inert gas environment.
Optionally, the temperature of described annealing is 900 to 1200 ℃.
Optionally, the temperature of described annealing is 1050 ℃.
Optionally, the time of described annealing is 10 to 30s.
Optionally, further comprise: before flatening process, described insulating barrier is carried out annealing process.
The present invention also provides a kind of manufacture method of fleet plough groove isolation structure, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, is formed with pad silicon oxide layer and hard mask layer successively;
Formation runs through the opening of described hard mask layer and pad silicon oxide layer, and forms groove in the Semiconductor substrate of described open bottom;
Form pad silicon oxide layer in described flute surfaces;
Depositing insulating layer in described groove, opening and on the hard mask layer;
Remove insulating barrier on the described hard mask layer by planarization;
Finish after the described flatening process, the insulating barrier in described groove and the opening is carried out annealing process;
Remove described hard mask layer and pad silicon oxide layer.
Optionally, describedly be annealed into the annealing of rapid thermal annealing or boiler tube.
Optionally, described annealing is carried out in nitrogen or inert gas environment.
Optionally, the temperature of described annealing is 900 to 1200 ℃.
Optionally, the time of described annealing is 10 to 30s.
Optionally, further comprise: before flatening process, after the depositing insulating layer, described insulating barrier is carried out annealing process.
Optionally, the method for depositing insulating layer is low-pressure chemical vapor deposition or aumospheric pressure cvd or high density plasma chemical vapor deposition.
Compared with prior art, one of them in the technique scheme has following advantage:
After finishing flatening process, insulating barrier in described groove and the opening is carried out annealing process, by annealing process described insulation layer structure is reformed, can repair the cavity blemish of insulating barrier and hard mask layer intersection, cavity blemish is eliminated or minimizing, thereby can be eliminated or reduce the defective of the fleet plough groove isolation structure top depression of formation; In addition, annealing process can also further discharge the stress in the insulating barrier; Help improving the insulation isolation effect of the fleet plough groove isolation structure of formation, improve the stability of semiconductor device that forms.
Description of drawings
Fig. 1 to Fig. 7 is each step corresponding structure generalized section of manufacture method of existing a kind of fleet plough groove isolation structure;
Fig. 8 is the generalized section of the cavity blemish that forms of the manufacture method of existing fleet plough groove isolation structure;
Fig. 9 is the flow chart of the embodiment of fleet plough groove isolation structure of the present invention;
Figure 10 is the cross-sectional view with Semiconductor substrate of pad silicon oxide layer, hard mask layer and insulating barrier;
Figure 11 is the cross-sectional view with Semiconductor substrate of pad silicon oxide layer and hard mask layer;
Figure 12 is the cross-sectional view after forming patterns of openings on the hard mask layer shown in Figure 11;
Figure 13 is the cross-sectional view form opening in hard mask layer shown in Figure 12 and pad silicon oxide layer after;
Figure 14 is a cross-sectional view behind the formation groove in semiconductor structure shown in Figure 13;
Figure 15 is the generalized section after flute surfaces shown in Figure 14 (i.e. bottom and sidewall) forms pad silicon oxide layer;
The generalized section of the structure of Figure 16 after to insulating barrier planarization shown in Figure 10;
Figure 17 is the generalized section of the structure after removing hard mask layer shown in Figure 16 and filling up silicon oxide layer.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
Fleet plough groove isolation structure is used for the semiconductor device of semiconductor integrated circuit and the isolation between the device.Provide a kind of manufacture method of fleet plough groove isolation structure in the embodiments of the invention: at first, Semiconductor substrate is provided, on described Semiconductor substrate, be formed with pad silicon oxide layer and hard mask layer successively, in described Semiconductor substrate, has groove, in described pad silicon oxide layer and hard mask layer, have opening, on described opening, groove and hard mask layer, have insulating barrier with the corresponding position of groove.
Then, remove insulating barrier on the described hard mask layer by flatening process, described flatening process can be a cmp.
After finishing described flatening process, the insulating barrier in described groove and the opening is carried out annealing process.
Then, remove described hard mask layer and pad silicon oxide layer, promptly form fleet plough groove isolation structure by wet etching.
In the manufacture method of the fleet plough groove isolation structure of described embodiment, after finishing flatening process, insulating barrier in described groove and the opening is carried out annealing process, can eliminate or reduce the cavity blemish of insulating barrier and hard mask layer intersection, thereby can eliminate or reduce the defective of the fleet plough groove isolation structure top depression of formation, help improving the fleet plough groove isolation structure insulation isolation effect of formation, improve the stability of semiconductor device that forms.
Be described in detail below in conjunction with flow chart and profile manufacture method the fleet plough groove isolation structure of described embodiment.
Fig. 9 is the flow chart of the embodiment of fleet plough groove isolation structure of the present invention.Figure 10 to Figure 17 is the generalized section of the structure relevant with each step of embodiment of fleet plough groove isolation structure of the present invention.
As shown in Figure 9, step S100 provides Semiconductor substrate, is formed with pad silicon oxide layer and hard mask layer on described Semiconductor substrate successively; In described Semiconductor substrate, have groove, in described pad silicon oxide layer and hard mask layer, have opening with the corresponding position of groove; In described groove, opening and on the hard mask layer, has insulating barrier.
Figure 10 is the cross-sectional view with Semiconductor substrate of pad silicon oxide layer, hard mask layer and insulating barrier.Cross-sectional view as shown in figure 10.Have pad silicon oxide layer 102 and hard mask layer 104 on the Semiconductor substrate 100, in described hard mask layer 104 and pad silicon oxide layer 102, has opening (not indicating), has groove (not indicating) in the Semiconductor substrate 100 of described open bottom, have pad silicon oxide layer 106 in described flute surfaces, in described groove and opening, on the mask layer 104, be formed with insulating barrier 120.
Among the embodiment therein, the technology that forms structure shown in Figure 10 is as follows:
Figure 11 is the cross-sectional view with Semiconductor substrate of pad silicon oxide layer and hard mask layer.As shown in figure 11, provide Semiconductor substrate 100, on described Semiconductor substrate 100, have pad silicon oxide layer 102 and hard mask layer 104.
Described Semiconductor substrate 100 can be a kind of in monocrystalline silicon, polysilicon, the amorphous silicon, described Semiconductor substrate 100 also can be a kind of in silicon Germanium compound, the silicon gallium compound, described Semiconductor substrate 100 can comprise silicon on epitaxial loayer or the insulating barrier (Silicon On Insulator, SOI) structure.
Described pad silicon oxide layer 102 is 5 to 50nm, and the method that forms described pad oxide 102 can be that high temperature furnace pipe oxidation, rapid thermal oxidation, original position steam produce a kind of in the oxidizing process.
Described pad oxide 102 is as the adhesion layer between hard mask layer 104 and Semiconductor substrate 100 surfaces, be used to increase the caking property between hard mask layer 104 and Semiconductor substrate 100 surfaces, and the stress between balance hard mask layer 104 and Semiconductor substrate 100 surfaces.
In addition, the method that forms described pad oxide 110 also can be chemical vapour deposition (CVD).
Described hard mask layer 104 is a silicon nitride, and its thickness is 30 to 300nm; The method that forms described hard mask layer 104 can be chemical vapour deposition (CVD).
Described hard mask layer 104 is on the one hand as the hard mask of etching groove in described Semiconductor substrate 100, on the other hand as the layer that stops of the cmp planarization of the insulating material of filling in groove.
In other embodiments, described hard mask layer 104 also can be a multilayer.
Figure 12 is the cross-sectional view after forming patterns of openings on the hard mask layer shown in Figure 11.
As shown in figure 12, spin coating photoresist layer 110 on described hard mask layer 104; Form patterns of openings 112 by exposure imaging technology, the surface of described hard mask layer 104 is exposed in the bottom of described patterns of openings 112.
In other embodiments, before the described photoresist layer 110 of spin coating, can form anti-reflecting layer on described hard mask layer 104, described anti-reflecting layer can be an inorganic material, for example silicon oxynitride, or organic material; And then form photoresist layer 110 on described anti-reflecting layer, and exposure imaging forms patterns of openings 112.
Figure 13 is the cross-sectional view form opening in hard mask layer shown in Figure 12 and pad silicon oxide layer after.
As shown in figure 13, the hard mask layer 104 and the pad oxide 102 of the described patterns of openings of etching 112 bottoms form opening 114.
The surface of described Semiconductor substrate 100 is exposed in the bottom of described opening 114.Described etching is the plasma dry etching, and etching gas can be CF
4
Figure 14 is a cross-sectional view behind the formation groove in semiconductor structure shown in Figure 13.
As shown in figure 14, the Semiconductor substrate 100 of the described opening of etching 114 bottoms forms groove 116 in described Semiconductor substrate 100.
The method of the described groove 116 of etching is the plasma dry etching, and etching gas can be Cl
2Or HBr, or the mist of HBr and other gas, for example can be HBr and O
2, Cl
2Mist, or HBr and NF
3, He mist.
The degree of depth of the groove 116 that etching forms is by the time control of etching.
Etching forms the technology of described groove 116 and can carry out respectively in different etching apparatuss with the technology that etching forms described opening 114, also can original position carry out in same etching apparatus.Original position carries out improving productive rate.
If etching forms the technology of described groove 116 and carries out respectively in different etching apparatuss with the technology that etching forms described opening 114, can before etching forms described groove 116, remove described photoresist layer 110, also can after the etching of finishing described groove 116, remove described photoresist layer 110 by the oxygen gas plasma ashing;
If original position is carried out, after the etching of finishing described groove 116, remove described photoresist layer 110.
Figure 15 is the generalized section after flute surfaces shown in Figure 14 (i.e. bottom and sidewall) forms pad silicon oxide layer.
As shown in figure 15, clean the surface of described groove 116, generate pad silicon oxide layer 118 with thermal oxidation method at described groove 116 inwalls then with hydrofluoric acid solution.
Cleaning by described hydrofluoric acid solution, can remove the natural oxidizing layer that described groove 116 surfaces generate, help forming the high pad silicon oxide layer of density 118, make described pad silicon oxide layer 118 as the comparatively stable interlayer of characteristic between the insulating barrier of Semiconductor substrate 100 and filling in described groove 116, and increase adhesiveness between the two, reduce device leakage current in the Semiconductor substrate 100 when work.
In addition, described hydrofluoric acid solution cleans the part pad oxide 102 that also can remove described groove 116 top, make described pad oxide 102 sidewalls a little contraction be arranged to described hard mask layer 104 bottoms, thereby the corner of described groove 116 top is exposed, when carrying out thermal oxidation and generate described pad silicon oxide layer 118, can make the corner at the top of described groove 116 have comparatively level and smooth profile.Described level and smooth profile can reduce stress build up on the one hand, can reduce when device is worked charge carrier on the other hand and gather influence to opening feature.
The technology that thermal oxidation method generates described pad silicon oxide layer 118 can be to carry out in 900 to the 1200 dried oxygen environment of spending in temperature, and the thickness of the pad silicon oxide layer 118 of formation is about 10 to 60nm.
Described thermal oxidation method also can be a wet-oxygen oxidation, and for example original position steam produces oxidation, repeats no more here.
In a further embodiment, described substrate silicon oxide layer 118 can be a multilayer, can be the stacked structure of silicon oxide layer and silicon oxynitride layer also, repeats no more here.
In a further embodiment, after the formation pad silicon oxide layer 118, can carry out annealing processs, be released in the stress that produces when forming pad silicon oxide layer 118 described substrate silicon oxide layer 118.Described annealing can be boiler tube annealing or rapid thermal annealing.
Form insulating barrier 120 on described pad silicon oxide layer 118, in the opening 114 and on the described hard mask layer 104, promptly form cross-sectional view as shown in figure 10, described insulating barrier 120 can be silica or silicon oxynitride.Insulating barrier described in the present embodiment 120 is a silica.
The method that forms described insulating barrier 120 can be low-pressure chemical vapor deposition or aumospheric pressure cvd or high density plasma CVD.
After forming described insulating barrier 120, can carry out annealing process to described insulating barrier 120, the stress that produces when being released in depositing insulating layer 120, described annealing can be boiler tube annealing or rapid thermal annealing.
Step S110 removes insulating barrier on the described hard mask layer by flatening process.
The generalized section of the structure of Figure 16 after to insulating barrier planarization shown in Figure 10.
As shown in figure 16, the described insulating barrier 120 of planarization is removed the insulating barrier 120 on the described hard mask layer 104, and the insulating barrier that keeps in described groove 116 and the opening 114 is 120a.
Described planarization can be a cmp.
Step S120, finish described flatening process after, the insulating barrier in described groove and the opening is carried out annealing process.
After finishing flatening process, described insulating barrier 120a is carried out annealing process, described annealing can be rapid thermal annealing or boiler tube annealing.Described annealing is carried out in nitrogen or inert gas environment, and described inert gas can be helium or argon gas.
The temperature of annealing is 900 to 1200 ℃, and is concrete, can be 1050 ℃.The time of annealing is 10 to 30s.
Pass through annealing process, described insulation layer structure is reformed, repair behind the cmp cavity blemish that produces at insulating barrier 120a and hard mask layer 104 interface places, cavity blemish is eliminated or minimizing, therefore thereby can eliminate or reduce and the defective of the fleet plough groove isolation structure top depression that forms, in addition, annealing process can also further discharge the stress in the insulating barrier; Help improving the insulation isolation effect, improve the stability of semiconductor device that forms.
Step S130 removes described hard mask layer and pad silicon oxide layer.
Figure 17 is the generalized section of the structure after removing hard mask layer shown in Figure 16 and filling up silicon oxide layer.
Remove described hard mask layer 104 with the phosphoric acid solution etching; Before with the described hard mask layer of phosphoric acid solution etching, can clean the surface of described hard mask layer 104 earlier with hydrofluoric acid solution, residual behind the removal cmp at the oxide of covering layer 104 surface firmly.
Then, remove described pad oxide 102 with the hydrofluoric acid solution etching.Form fleet plough groove isolation structure as shown in figure 17.
Because before removing hard mask layer 104 and pad silicon oxide layer 102, described insulating barrier 120a is carried out annealing process, can repair the cavity blemish of insulating barrier 120a and hard mask layer 104 intersections, thereby behind wet etching hard mask layer 104 and pad silicon oxide layer 102, can alleviate or eliminate the defective that depression is formed on the fleet plough groove isolation structure top that forms.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (9)
1. the manufacture method of a fleet plough groove isolation structure is characterized in that, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, is formed with pad silicon oxide layer and hard mask layer successively; In described Semiconductor substrate, have groove, in described pad silicon oxide layer and hard mask layer, have opening with the corresponding position of groove; In described groove, opening and on the hard mask layer, has insulating barrier;
Remove insulating barrier on the described hard mask layer by flatening process;
After finishing described flatening process, the insulating barrier in described groove and the opening is carried out annealing process, wherein, the temperature of described annealing is 1050 to 1200 ℃, and the time of annealing is 10 to 30s;
Remove described hard mask layer and pad silicon oxide layer.
2. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: describedly be annealed into rapid thermal annealing or boiler tube annealing.
3. the manufacture method of fleet plough groove isolation structure as claimed in claim 2, it is characterized in that: described annealing is carried out in nitrogen or inert gas environment.
4. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that: further comprise: before flatening process, described insulating barrier is carried out annealing process.
5. the manufacture method of a fleet plough groove isolation structure is characterized in that, comprising:
Semiconductor substrate is provided, on described Semiconductor substrate, is formed with pad silicon oxide layer and hard mask layer successively;
Formation runs through the opening of described hard mask layer and pad silicon oxide layer, and forms groove in the Semiconductor substrate of described open bottom;
Form pad silicon oxide layer in described flute surfaces;
Depositing insulating layer in described groove, opening and on the hard mask layer;
Remove insulating barrier on the described hard mask layer by planarization;
Finish after the described flatening process, the insulating barrier in described groove and the opening is carried out annealing process, wherein, the temperature of described annealing is 1050 to 1200 ℃, and the time of annealing is 10 to 30s;
Remove described hard mask layer and pad silicon oxide layer.
6. the manufacture method of fleet plough groove isolation structure as claimed in claim 5 is characterized in that: describedly be annealed into rapid thermal annealing or boiler tube annealing.
7. the manufacture method of fleet plough groove isolation structure as claimed in claim 6, it is characterized in that: described annealing is carried out in nitrogen or inert gas environment.
8. the manufacture method of fleet plough groove isolation structure as claimed in claim 5 is characterized in that, further comprises: before flatening process, after the depositing insulating layer, described insulating barrier is carried out annealing process.
9. the manufacture method of fleet plough groove isolation structure as claimed in claim 5, it is characterized in that: the method for depositing insulating layer is low-pressure chemical vapor deposition or aumospheric pressure cvd or high density plasma chemical vapor deposition.
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|---|---|---|---|
| CN2007100945699A CN101459116B (en) | 2007-12-13 | 2007-12-13 | Shallow groove isolation construction manufacturing method |
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| CN101459116B true CN101459116B (en) | 2010-06-09 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9184088B2 (en) | 2011-01-25 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a shallow trench isolation (STI) structures |
| US9209280B2 (en) | 2010-04-28 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
| US9564529B2 (en) | 2010-05-06 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure and structure formed |
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| US8461015B2 (en) * | 2009-07-08 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | STI structure and method of forming bottom void in same |
| US8623728B2 (en) | 2009-07-28 | 2014-01-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming high germanium concentration SiGe stressor |
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| US9040393B2 (en) | 2010-01-14 | 2015-05-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming semiconductor structure |
| CN102403258A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Preparation method for shallow groove isolation structure |
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| CN102610552A (en) * | 2012-03-14 | 2012-07-25 | 上海华力微电子有限公司 | Method for improving STI (shallow trench isolation) characteristic by aid of metal hard mask |
| CN103594413A (en) * | 2012-08-14 | 2014-02-19 | 中芯国际集成电路制造(上海)有限公司 | A method for manufacturing a shallow trench isolating structure |
| CN103681450B (en) * | 2012-09-18 | 2016-10-05 | 中芯国际集成电路制造(上海)有限公司 | The forming method of semiconductor device |
| CN104425353B (en) * | 2013-08-20 | 2019-12-27 | 中芯国际集成电路制造(上海)有限公司 | Polishing method of through silicon via |
| CN109755171A (en) * | 2017-11-06 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | The forming method of groove and the forming method of fleet plough groove isolation structure |
| CN116525456A (en) * | 2023-07-03 | 2023-08-01 | 粤芯半导体技术股份有限公司 | MOSFET device manufacturing method based on TDDB optimization |
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| US6207535B1 (en) * | 2000-01-24 | 2001-03-27 | United Microelectronics Corp. | Method of forming shallow trench isolation |
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| US5786262A (en) * | 1997-04-09 | 1998-07-28 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-planarized gapfilling for shallow trench isolation |
| US6207535B1 (en) * | 2000-01-24 | 2001-03-27 | United Microelectronics Corp. | Method of forming shallow trench isolation |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9209280B2 (en) | 2010-04-28 | 2015-12-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping fin field-effect transistors |
| US9450097B2 (en) | 2010-04-28 | 2016-09-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods for doping Fin field-effect transistors and Fin field-effect transistor |
| US9564529B2 (en) | 2010-05-06 | 2017-02-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure and structure formed |
| US11855210B2 (en) | 2010-05-06 | 2023-12-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for fabricating a strained structure and structure formed |
| US9184088B2 (en) | 2011-01-25 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of making a shallow trench isolation (STI) structures |
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| CN101459116A (en) | 2009-06-17 |
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