CN101458511A - Hardware interpolation method based on programmable logic device - Google Patents

Abstract

The invention discloses a hardware interpolation method based on programable logic device which includes a microprocessor sending control information to the programable logic device, the programable logic device converts the control signal into a serialization control signal for controlling motor driver, the programable logic device receives a control, data and address signal sent by the microprocessor and returns to a state sign, uses two-stage cache to the signal and sends control pulse synchronously, ensures uniform action of the motor, the control pulse is generated in the programable logic device according with special arithmetic for realizing control to the motor driver; the method can program or repeatedly program to the programable logic device for reconstructing logic function which makes hardware flexible as software that is easy to amend and upgrade. The method can make circuit has advantages of simple structure, no discrete component, convenient to amend logic and stronger interference free performance.

Description

Hardware interpolation method based on programmable logic device (PLD)

Technical field

The present invention relates to a kind of hardware interpolation method based on programmable logic device (PLD).

Background technology

Present many digital control systems are controlled rotating speed of motor and direction to pulse, direction signal after ovennodulation as the control signal of control step motor and motor servo driver, realize the motion of numerically-controlled machine.As stepper motor driver, have three control input ends: stepping pulse signal, direction level signal, enable level signal.When control circuit carries out corresponding control to these three input ends, can realize the control of speed, direction etc. to stepper motor.But these pulse-generating circuits of past all are to adopt small-sized discrete component overlap joint to form, and there is that the pulse waveform pattern is more single, the rising edge of pulse and negative edge is precipitous inadequately, require when very narrow defective such as the difficult realization of circuit when pulse width.

Summary of the invention

Technical matters to be solved by this invention provides a kind of hardware interpolation method based on programmable logic device (PLD), and this method makes things convenient for the reconfigurable circuit logic function under the situation that does not change system hardware, realizes the pulse control of digital control system.

For solving the problems of the technologies described above, the hardware interpolation method that the present invention is based on programmable logic device (PLD) comprises that employing parallel transfer mode sends control information to the microprocessor of programmable logic device (PLD), by programmable logic device (PLD) control signal is converted into the serial control signal of controlling motor driver, this method comprises the steps:

Step 1, programmable logic device (PLD) receive control signal, data-signal and the address signal that microprocessor sends, and generate an interpolation cycle simultaneously;

Step 2, above-mentioned signal is adopted the two-stage buffered, and in an interpolation cycle, to calculating through the pulsewidth interpolations such as signal work of two-stage buffering, its algorithm is:

A base value at first is set, after the additive operation of finishing integrand value and accumulated value, accumulation result and base value is compared, judge pulse output,

Function is at [t ₀, t _r] definite integral, be function at this interval area, $s={\∫}_0^{\mathrm{tr}}\mathrm{ydt}.$ If from t=0, a series of uniformly-spaced values of taking from variable t are △ t, as enough hour of △ t, can get $s=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{y}_i\mathrm{\Δt},$ Y is the constantly corresponding value of t herein, and t is a time value, if get △ t=1, i.e. and pulse equivalency δ, then $s=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{y}_i,$ The integral operation of function has become the accumulating operation of variable, if enough hour of δ, the error that the summation operation that then adds up replaces integral operation to introduce can be no more than the error that is allowed.

Step 3, programmable logic device (PLD) return state sign are in microprocessor, in order to judge whether signal has entered buffer zone separately, and will the signal after interpolation is calculated to change into frequency even, etc. each feeding pulse of dutycycle, provide the direction signal of motor simultaneously.

Because the hardware interpolation method based on programmable logic device (PLD) of the present invention has adopted technique scheme, promptly the gating pulse that draws by special algorithm by the programmable logic device (PLD) generation realizes the control to motor driver; This method can be programmed to programmable logic device (PLD) or programming repeatedly for the reconstruct logic function under the situation that does not change Circuits System design or wiring board, make hardware become as software flexible and be easy to revise, upgrading.Adopt programmable logic device (PLD) to realize that the hardware interpolation utensil has characteristics such as discrete component simple in structure, no, logic Modification convenience, strong anti-interference performance.

Description of drawings

The present invention is described in further detail below in conjunction with drawings and embodiments:

Fig. 1 is this pulse algorithm principle figure based on the hardware interpolation method of programmable logic device (PLD),

Fig. 2 is this linear interpolation trajectory diagram based on the hardware interpolation method pulse algorithm of programmable logic device (PLD),

Fig. 3 is this logic theory block diagram based on the hardware interpolation method of programmable logic device (PLD).

Embodiment

The hardware interpolation method that the present invention is based on programmable logic device (PLD) comprises that employing parallel transfer mode sends control information to the microprocessor of programmable logic device (PLD), by programmable logic device (PLD) control signal is converted into the serial control signal of controlling motor driver, this method comprises the steps:

Step 1, programmable logic device (PLD) receive control signal, data-signal and the address signal that microprocessor sends, and generate an interpolation cycle simultaneously;

Step 2, above-mentioned signal is adopted the two-stage buffered, and in an interpolation cycle, to calculating through the pulsewidth interpolations such as signal work of two-stage buffering, its algorithm is:

A base value at first is set, after the additive operation of finishing integrand value and accumulated value, accumulation result and base value is compared, judge pulse output,

As shown in Figure 1, function is at [t ₀, t _r] definite integral, be function at this interval area, $s={\∫}_0^{\mathrm{tr}}\mathrm{ydt}.$ If from t=0, a series of uniformly-spaced values of taking from variable t are △ t, as enough hour of △ t, can get $s=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{y}_i\mathrm{\Δt},$ Y is the constantly corresponding value of t herein, and t is a time value, if get △ t=1, i.e. and pulse equivalency δ, then $s=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}{y}_i,$ The integral operation of function has become the accumulating operation of variable, if enough hour of δ, the error that the summation operation that then adds up replaces integral operation to introduce can be no more than the error that is allowed.

Step 3, programmable logic device (PLD) return state sign are in microprocessor, in order to judge whether signal has entered buffer zone separately, and will the signal after interpolation is calculated to change into frequency even, etc. each feeding pulse of dutycycle, provide the direction signal of motor simultaneously.

So-called interpolation is meant the process of closeization of data.Under the situation of digital control system being imported limited coordinate points (for example starting point, terminal point), computing machine is according to the feature (straight line, circular arc, ellipse etc.) of line segment, use certain algorithm, automatically between limited coordinate points, generate a series of coordinate data, be closeization of data, thereby automatically each coordinate axis is carried out pulse distribution, finish the track operation of whole line segment, to satisfy the requirement of machining precision.

As a kind of concrete interpolation mode, digital integration linear interpolation track is established and is wanted processing linear OA as shown in Figure 2, starting point O (0,0), terminal point A (5,2).If integrand register JV, the capacity of remainder register JR and terminal point counter JE is the triad register, then accumulative frequency N=2 ³=8, before the interpolation, JE, JRX, the equal zero clearing of JRY.

Its calculation step is as shown in the table:

The present invention receives and obtains each amount of feeding in the interpolation cycle after microprocessor calculates by rough interpolation, convert it into frequency evenly, etc. the feeding pulse of dutycycle, export to each motor driver.

For achieving the above object, based on very-high-speed hardware descriptive language (Very High Speed IntegratedCircuit Hardware Description Language), utilize CPLD (CPLD) or on-the-spot gate array (FPGA) to realize hardware interpolation device circuit, interpolation function is designed to a standard module, its transplantability is strong, improved processing speed, and reduced the area of hardware circuit, guaranteed the reliability of system, can upgrade to it simultaneously, thereby realize open completely and restructural.

As shown in Figure 3, with two is example, the X-axis that microprocessor sends, Y-axis data process MUX are sent into separately the first impact damper X1, Y1, (1 expression impact damper has data to put zone bit FLAGX=' 1 ', FLAGY=' 1 ' simultaneously, ' 0 ' expression is empty), judge whether X-axis, Y-axis impact damper zone bit FLAG_B are ' 0 ', then the data among the first impact damper X1, the Y1 are delivered to second impact damper for ' 0 ', put zone bit FLAG_B=' 1 ' simultaneously, FLAGX=' 0 ', FLAGY=' 0 '.FLAG_B=' 1 ' is used for synchronous judgement, represents that each axis data is ready to, and next step rising edge at interpolation cycle EN is sent into X, Y-axis data etc. in the pulsewidth DDA module, simultaneously FLAG_B=' 0 '.Calculate through interpolation etc. pulsewidth DDA module, with data conversion become frequency evenly, etc. feeding pulse PULSEX, the PULSEY of dutycycle, simultaneously with the most significant digit of data bit direction signal DIRX, DIRY, export to the motor driver of X-axis and Y-axis as motor.Also have a ternary control logic module, an interpolation cycle EN generation module in the programmable logic device (PLD).Ternary control logic module effect is that Data transmission and return state signal are given processor, and status signal is used for judgment data and whether has sent to separately buffer zone.The effect of interpolation cycle EN generation module is to generate fixing interpolation cycle signal.

Input signal is arranged in Fig. 3, output signal, two-way signaling and internal signal, it is respectively:

Input signal clock signal: CLK

Global reset signal: RESET

Chip selection signal: CS

Address signal 0:A0

Address signal 1:A1

Read signal: RD

Write signal: WR

The pulse signal of output signal X-axis: PULSEX

The direction signal of X-axis: DIRX

The pulse signal of Y-axis: PULSEY

The direction signal of Y-axis: DIRY

Two-way signaling data input/output signal: DATA

Internal signal clock division signal: CLK_SIG_OUT

Set time generates signal: EN

Data input signal: DATAIN

The state flag bit of X-axis: FLAGX behind level cache

After latching, send into the data of X-axis: D_SIGX

State flag bit behind L2 cache: FLAG_B

Behind level cache, send into the data of X-axis: D_BUFX

Behind L2 cache, send into the data of X-axis: D_OUTX

The state flag bit of Y-axis: FLAGY behind level cache

After latching, send into the data of Y-axis: D_SIGY

Behind level cache, send into the data of Y-axis: D_BUFY

Behind L2 cache, send into the data of Y-axis: D_OUTY

In logic theory block diagram shown in Figure 3, with two be example, setting DATAIN is 8 bits, wherein most significant digit DATAIN[7] be the direction position, DATAIN[6..0] be data bit.The CLK signal is produced by external crystal-controlled oscillation, also can be sent by microprocessor.EN is used to set the set time, and its pulse width is set by counter, by changing the counter data figure place, can change cycle and the dutycycle of EN flexibly.CS, A0 and A1 are given by microprocessor, as " A1﹠amp; A0 "＜=when " 00 ", input data " DATAIN " are sent into X-axis impact damper, " A1﹠amp; A0 "＜=when " 01 ", input data " DATAIN " are sent into the Y-axis impact damper.When beginning, the data of sending into the X-axis impact damper are " 10010000 ", the data of sending into the Y-axis impact damper are " 00010100 ", EN in cycle length in regulation, the pulse number of X-axis pulse output " PULSEX " output is " 0010000 ", be metric 16, it is metric 20 that the pulse number of Y-axis pulse output " PULSEY " output is that " 0010100 " is, and pulse output evenly.Because setting the pulse direction position is the most significant digit of data bit, thus " DIRX "＜=' 1 ', " DIRY "＜=' 0 ', " DIRX " is shown as high level, and " DIRY " is shown as low level.By changing the value of input data " DATAIN ", can change the output pulse number and the direction of X-axis, Y-axis.By setting address bit " A1﹠amp; A0 "＜=" 10 ", " A1﹠amp; A0 "＜=" 11 " can realize interlocks simultaneously such as 3,4, as number of axes greater than 4, as long as corresponding extended address position.

This method utilizes programmable logic device (PLD) to realize hardware interpolation device circuit, and interpolation function is designed to a standard module, discrete component simple in structure, no, convenient, the strong anti-interference performance of logic Modification.

It adopts the interpolation of hardware equal time, and the pulse number of interpolation distributes in an interpolation cycle.Compare with traditional hardware interpolation device, adopt the equal time interpolation, continuity and synchronous requirement the to data than higher, and carry out interpolation operation behind speed, starting point and the terminal point coordinate that traditional hardware interpolation device reception upper computer software sends, the mode that interpolation finishes to adopt interruption or poll in the back notifies host computer to carry out the operation of interpolation next time.

The hardware of this method is realized the double buffering synchronizing circuit.Adopt double-damping structure, data transmission is continuous, reliable, and speed is fast, need not interrupt control, has alleviated the workload of software.Synchronizing function is used to judge whether the data of each receive, and output to motor driver after receiving together, can control multi-axle motor synchronous operation accurately like this.

Pulsewidth DDA algorithms such as employing.Etc. pulsewidth DDA algorithm by earlier with data shift, carry out * 2 operations after, again through traditional DDA interpolation calculate the back output frequency evenly, etc. the pulsed frequency of dutycycle.Realize simply having eliminated the truncation error of pulse.

Claims (1)

1, a kind of hardware interpolation method based on programmable logic device (PLD), comprise and adopt the parallel transfer mode to send control information to the microprocessor of programmable logic device (PLD), control signal is converted into the serial control signal of control motor driver by programmable logic device (PLD), it is characterized in that: this method comprises the steps

Step 1, programmable logic device (PLD) receive control signal, data-signal and the address signal that microprocessor sends, and generate an interpolation cycle simultaneously;

Step 2, above-mentioned signal is adopted the two-stage buffered, and in an interpolation cycle, to calculating through the pulsewidth interpolations such as signal work of two-stage buffering, its algorithm is:

A base value at first is set, after the additive operation of finishing integrand value and accumulated value, accumulation result and base value is compared, judge pulse output,

Function is at [t ₀, t _r] definite integral, be function at this interval area, $s={\∫}_0^{\mathrm{tr}}\mathrm{ydt}.$ If from t=0, a series of uniformly-spaced values of taking from variable t are △ t, as enough hour of △ t, can get $s=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}\mathrm{yi\Δt},$ Y is the constantly corresponding value of t herein, if get △ t=1, i.e. and pulse equivalency δ, then $s=\underset{i=0}{\overset{n}{\mathrm{\Σ}}}\mathrm{yi},$ The integral operation of function has become the accumulating operation of variable, if enough hour of δ, the error that the summation operation that then adds up replaces integral operation to introduce can be no more than the error that is allowed;

Step 3, programmable logic device (PLD) return state sign are in microprocessor, in order to judge whether signal has entered buffer zone separately, and will the signal after interpolation is calculated to change into frequency even, etc. each feeding pulse of dutycycle, provide the direction signal of motor simultaneously.

Images