CN101431417B - Network processor and its electricity-saving method - Google Patents
Network processor and its electricity-saving method Download PDFInfo
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- CN101431417B CN101431417B CN2007101850925A CN200710185092A CN101431417B CN 101431417 B CN101431417 B CN 101431417B CN 2007101850925 A CN2007101850925 A CN 2007101850925A CN 200710185092 A CN200710185092 A CN 200710185092A CN 101431417 B CN101431417 B CN 101431417B
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Abstract
A network processor and a method to save electricity which includes the following steps: receiving network signal by receiving circuit; comparing voltage level with critical value of the network signal to output the comparison result; controlling clock signal used by network data processing unit according to the comparison result. Disable the clock signal to stop clock signal from being output to network data processing unit when voltage level lower than critical value; Enable the clock signal to output the clock signal to network data processing unit when voltage level not lower than the critical value.
Description
Technical field
The invention relates to a kind of processor and electricity saving method thereof, be meant a kind of network processing unit and electricity saving method thereof especially.
Background technology
Many devices (for example: computer, storage device, printer etc.) are joined together to form a network usually, to carry out the exchange of data.Each network equipment is to set up with other network equipment and keep online by network processing unit and cable.For making battery-powered network equipment, if not and other network equipment set up when online, still, will quicken the power drain of battery to the network processing unit continued power of its use.And for not being to use battery powered network equipment, the power consumption that reduces network processing unit can reduce the heat of generation.
Consult Fig. 1, United States Patent (USP) has disclosed a kind of known network equipment No. 6993667.This network equipment comprises physical layer (Physical Layer) 2.This physical layer 2 comprises physical layer circuit 21, power-saving circuit 22, receiver 23 and conveyer 24, and can operate under first battery saving mode and second battery saving mode.
Under this first battery saving mode, when this receiver 23 detects online activity, this power-saving circuit 22 makes the electric power of this physical layer 2 promote (Power Up), come to set up and keep online with other network equipment (figure does not show), otherwise this power-saving circuit 22 makes the electric power of the part except this power-saving circuit 22 and this receiver 23 in this physical layer 2 reduce (Power Down).
Under this second battery saving mode, this power-saving circuit 22 periodically makes the electric power of this conveyer 24 open, and produces link pulse (Link Pulse).
Therefore, whether this physical layer 2 can exist to come automatic decision whether to save power consumption according to online activity.
Yet this kind electricity saving method is to close the required power supply of network processing unit, therefore needs the higher power-saving circuit 22 of design one cover complexity to control battery saving mode, in addition, when carrying out the electric power lifting, also need spend the long time, could be with the service restoration of integral body.
In addition, see also Fig. 2, Fig. 2 is another kind of known network equipment, and it comprises RJ45 connectivity port 11, network processing unit 12 and south bridge 13.The plug that this RJ45 connectivity port 11 can the sensing cable (figure does not show), and when sensing, send signal to this south bridge 13.The signal that this south bridge 13 is sent according to this RJ45 connectivity port 11 when this cable is pulled out, makes the power cut (Power Off) of this network processing unit 12, and when this cable is plugged, makes the electric power of this network processing unit 12 open (PowerOn).Therefore, by this RJ45 connectivity port 11, the power consumption that can save this network processing unit 12.
Yet this kind network equipment must use the plug of special RJ45 connectivity port 11 ability detection streamers, will make cost increase.
Summary of the invention
Therefore, one of purpose of the present invention is to provide a kind of clock signal of closing function that has, to reach the network processing unit of low power consumption.
Therefore, one of purpose of the present invention is to provide a kind of electricity saving method of network processing unit, utilizes the received voltage level of network processing unit, judges whether to stop clock signal, to reduce the power consumption of network processing unit.
The present invention discloses a kind of network processing unit, this network processing unit comprises: pass to receive circuit, is used for transmitting and receiving network signal, and the relatively voltage level and the critical value of this network signal, with the output comparative result, and this biography receipts circuit is to work in first clock signal; Network data processing unit, be coupled to this biography and receive circuit, be used for handling this biography and receive this network signal that circuit received, and this network data processing unit is to work in the second clock signal, wherein, the frequency of the frequency of this second clock signal and this first clock signal is inequality; And the clock signal control unit, be coupled to this biography and receive circuit and this network data processing unit, be used for according to this comparative result to control this second clock signal; Wherein, when this voltage level during less than this critical value, this this second clock signal of clock signal control unit forbidden energy, make this second clock signal stop to export to this network data processing unit, and when this voltage level is not less than this critical value, this this second clock signal of clock signal control unit activation makes this second clock signal export this network data processing unit to.
The present invention also discloses a kind of electricity saving method of network processing unit, and this method comprises: by receiving circuit to receive network signal; The relatively voltage level of this network signal and critical value are with the output comparative result; And according to this comparative result with the employed clock signal of Control Network data processing unit; Wherein, when this voltage level during less than this critical value, this clock signal of forbidden energy, make this clock signal stop to export to this network data processing unit, and when this voltage level was not less than this critical value, this clock signal of activation made this clock signal export this network data processing unit to.
Description of drawings
Fig. 1 is a calcspar, and a kind of known network equipment is described;
Fig. 2 is a block diagram, and another kind of known network equipment is described;
Fig. 3 is a calcspar, and first and second embodiment of network processing unit of the present invention is described; And
Fig. 4 is a calcspar, and the 3rd embodiment of network processing unit of the present invention is described.
[main element symbol description]
31 physical layers, 41 physical layers
311 pass receipts circuit 411 passes the receipts circuit
312 physical medium articulamentums, 412 physical medium articulamentums
313 Physical Coding Sublayers, 413 Physical Coding Sublayers
32 medium access control layers, 42 medium access control layers
33 quick peripheral component interconnect interface 43 quick peripheral component interconnect interfaces
34 clock signal control units, 44 clock signal control units
36 basic input output systems, 45 state buffers
47 drivers
Embodiment
About aforementioned and other technology contents, characteristics and effect of the present invention, in the following detailed description that cooperates with reference to three graphic embodiment, can clearly present.
Consult Fig. 3, Fig. 3 is first embodiment of network processing unit of the present invention, this network processing unit is the Ethernet processor, and comprise physical layer 31, medium access control (Media Access Control, MAC) layer 32, quick peripheral component interconnection (Peripheral ComponentInterconnect-Express, PCI-E) interface 33 and clock signaling control unit 34.This physical layer 31 comprises passing receives circuit 311, physical medium connection (Physical Media Attachment, PMA) layer 312 and Physical Coding Sublayer (Physical Coding Sub-layer, PCS) 313.Wherein, it is to operate in first clock signal that this biography is received circuit 311, this physical medium articulamentum 312 and this Physical Coding Sublayer 313 are to operate in the second clock signal, this medium access control layer 32 and this quick peripheral component interconnect interface 33 are to operate in the 3rd clock signal, and this first, second and the signal frequency of the 3rd clock signal different, and generally speaking, the frequency of this second clock signal is greater than the frequency of this first clock signal.
According to the first embodiment of the present invention, it is that built-in comparator (figure does not show) comes the receiving network data signal that this biography is received circuit 311, and this network data signals is a differential wave, then, this comparator compares the differential mode voltage of this network data signals with the critical voltage of being scheduled to, and the output comparative result is to this clock signal control unit 34.With an embodiment, when the differential mode voltage of this network data signals during less than this critical voltage, this biography is received 311 generations of circuit, first logical value and is sent in this clock signal control unit 34 as this comparative result, then, if this first logical value time of keeping greater than the scheduled time after (expression does not have the link pulse and inputs to this biographys receipts circuit 311), this the second and the 3rd clock signal of 34 forbidden energy of this clock signal control unit (Disable), to enter battery saving mode, and basic input output system (the Basic Input/Output System of generation index signal notice computer system end, BIOS) 36, otherwise, when the differential mode voltage of network data signals is not less than this critical voltage, this biography is received 311 generations of circuit, second logical value and is sent in this clock signal control unit 34 as this comparative result, 34 of this clock signal control units produce index signal again and notify this basic input output system 36 at this moment, send feedback signal to this clock signal control unit 34 by this basic input output system 36 again, make this second and the 3rd clock signal of these clock signal control unit 34 activations (Enable), the running that recovers this network processing unit.
Present embodiment is by making different elements based on different clock signal operations, do not detecting when online, can only keep the element that needs operation, and the employed clock signal of element that will need not operate is closed, for example: the biography that operates according to this first clock signal is received circuit 311 and still keep operate as normal under battery saving mode, and this physical medium articulamentum 312 and this Physical Coding Sublayer 313 employed second clock signals or this medium access control layer 32 can be closed under battery saving mode with these quick peripheral component interconnect interface 33 employed the 3rd clock signals, to reduce power consumption.
In the present embodiment, this clock signal control unit 34 is that (GeneralPurpose Input/Output GPIO) notifies this basic input output system 36, but not as limit by general input and output.
According to one embodiment of the invention, this clock signal control unit 34 comprises phase-locked loop (Phase-Locked Loop, PLL) (figure does not show) and relevant logic control circuit (figure does not show), when this biography receipts circuit 311 does not receive the link pulse, this logic control circuit can be closed this phase-locked loop, with this second clock signal of forbidden energy and the 3rd clock signal to save power consumption.In addition, according to another embodiment of the present invention, this clock signal control unit 34 also can be realized by Clock gating (Clock Gating) circuit (figure does not show) and relevant logic control circuit (figure does not show), when this biography is received circuit 311 and is not received the link pulse, this Clock gating then this second clock signal of forbidden energy and the 3rd clock signal to save power consumption.Yet the clock signal control unit 34 among the embodiment does not exceed with this phase-locked loop and this Clock gating.
In addition, it should be noted that, network processing unit of the present invention does not exceed with this Ethernet processor, it also can be the network processing unit of other kind, and the interface of its use does not also exceed with this quick peripheral interconnection interface 33, also can be the interface of other kind, for example: peripheral component interconnection (PeripheralComponent Interconnect, PCI) interface.
In addition, second embodiment according to network processing unit of the present invention, it also can be linked up by the quick peripheral interconnection interface 33 of south bridge (figure does not show) and this, make this quick peripheral interconnection interface 33 and this medium access control layer 32 enter the L2 battery saving mode, promptly when this biography receipts circuit 311 does not detect the link pulse, this this second clock signal of clock signal control unit 34 forbidden energy, and notify these basic input output system 36 these physical layers 31 to enter battery saving mode, then, this basic input output system 36 is notified this south bridge, this south bridge is linked up with this quick peripheral interconnection interface 33 again, make this quick peripheral interconnection interface 33 and this medium access control layer 32 enter the L2 battery saving mode, the L2 battery saving mode is known to those skilled in the art to be known, so do not give unnecessary details in addition at this.
In the present embodiment, this clock signal control unit 34 is to notify this basic input output system 36 by general input and output, but also can be to notify this basic input output system 36 by this quick peripheral interconnection interface 33, and not as limit.
See also Fig. 4, Fig. 4 is the 3rd embodiment of network processing unit of the present invention, and different is that this network processing unit has comprised state buffer 45 more and the computer system end is a battery saving mode of controlling this network processing unit by driver (Driver) 47 with first and second embodiment.
At first, it is by the differential mode voltage of more received network data signals and the critical voltage of being scheduled to that this biography is received circuit 411, whether receives the link pulse with decision, and comparative result is stored in this state buffer 45.Because the computer system end has driver 47, stored logical value in this state buffer 45 of inspection/poll (Polling) at set intervals, if check that this logical value is represented as when not linking pulse, this clock signal control unit 44 stops this second clock, and these driver 47 notice south bridges (figure does not show), at this moment, this south bridge is linked up with this quick peripheral interconnection interface 43, make this quick peripheral interconnection interface 43 and this medium access control layer 42 enter the L2 battery saving mode, otherwise, if when the logical value in driver 47 these state buffers 45 of inspection of computer system end has been represented as the link pulse, this clock signal control unit 44 recovers this second clock, and makes this quick peripheral interconnection interface 43 and this medium access control layer 42 break away from the L2 battery saving mode.
In these embodiment of the present invention, be to utilize this biography to receive the original online measuring ability of circuit to judge whether to stop this second or the 3rd clock signal automatically, perhaps make this quick peripheral interconnection interface and this medium access control layer enter the L2 battery saving mode, to save power consumption.Because therefore the plug that the present invention must not use special RJ45 connectivity port to come detection streamer can not make cost increase.
The above person of thought, only be embodiments of the invention, when not limiting scope of the invention process with this, promptly the simple equivalent of being done according to claim scope of the present invention and invention description content generally changes and modifies, and all still belongs in the scope that claim of the present invention contains.
Claims (20)
1. network processing unit comprises:
Pass to receive circuit, be used for transmitting and receiving network signal, and the relatively voltage level and the critical value of this network signal, with the output comparative result, and should biography receipts circuit be to work in first clock signal;
Network data processing unit, be coupled to this biography and receive circuit, be used for handling this biography and receive this network signal that circuit received, and this network data processing unit is to work in the second clock signal, wherein, the frequency of the frequency of this second clock signal and this first clock signal is inequality; And
The clock signal control unit is coupled to this biography and receives circuit and this network data processing unit, is used for according to this comparative result to control this second clock signal;
Wherein, when this voltage level during less than this critical value, this this second clock signal of clock signal control unit forbidden energy, make this second clock signal stop to export to this network data processing unit, and when this voltage level is not less than this critical value, this this second clock signal of clock signal control unit activation makes this second clock signal export this network data processing unit to.
2. network processing unit according to claim 1, wherein, when this voltage level surpasses preset time less than this critical value, this this second clock signal of clock signal control unit forbidden energy.
3. network processing unit according to claim 1, wherein, the frequency of this second clock signal is greater than the frequency of this first clock signal.
4. network processing unit according to claim 1, wherein, this network data processing unit is the physical medium articulamentum.
5. network processing unit according to claim 1, wherein, this network data processing unit is a medium access control layer.
6. network processing unit according to claim 1 also comprises:
Buffer is used for temporary status signal, and wherein, when this voltage level during less than this critical value, this status signal is set to first logical value, and when this voltage level was not less than this critical value, this status signal was set to second logical value.
7. network processing unit according to claim 1, be to be coupled to computer system, this computer system has basic input output system, when this voltage level during less than this critical value, this network processing unit sends index signal to this basic input output system, make this basic input output system output control signals to this clock signal control unit, with this second clock signal of forbidden energy.
8. network processing unit according to claim 7 is to notify this basic input output system by general input and output.
9. network processing unit according to claim 1, wherein, this clock signal control unit is a clock gating circuit.
10. network processing unit according to claim 1, wherein, this clock signal control unit is the phase-locked loop.
11. network processing unit according to claim 1, wherein, this network signal is a differential wave, and this voltage level is the differential mode voltage of this differential wave.
12. the electricity saving method of a network processing unit comprises:
By receiving circuit to receive network signal;
The relatively voltage level of this network signal and critical value are with the output comparative result; And
According to this comparative result with the employed clock signal of Control Network data processing unit;
Wherein, when this voltage level during less than this critical value, this clock signal of forbidden energy, make this clock signal stop to export to this network data processing unit, and when this voltage level was not less than this critical value, this clock signal of activation made this clock signal export this network data processing unit to.
13. the electricity saving method of network processing unit according to claim 11, wherein, when this voltage level surpasses preset time less than this critical value, this clock signal of forbidden energy.
14. the electricity saving method of network processing unit according to claim 11 also comprises:
When this voltage level during, send index signal to basic input output system less than this critical value.
15. the electricity saving method of network processing unit according to claim 11 also comprises:
Temporary this comparative result is to buffer; And
Whether this buffer of poll determine this clock signal of forbidden energy.
16. the electricity saving method of network processing unit according to claim 11, wherein, this network signal is a differential wave, and this voltage level is the differential mode voltage of this differential wave.
17. the electricity saving method of network processing unit according to claim 11, wherein, this clock signal of forbidden energy is by closing the phase-locked loop with this clock signal of forbidden energy.
18. the electricity saving method of network processing unit according to claim 11, wherein, this clock signal of forbidden energy is with this clock signal of forbidden energy by clock gating circuit.
19. the electricity saving method of network processing unit according to claim 11, wherein, this network data processing unit is the physical medium articulamentum.
20. the electricity saving method of network processing unit according to claim 11, wherein, this network data processing unit is a medium access control layer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007101850925A CN101431417B (en) | 2007-11-08 | 2007-11-08 | Network processor and its electricity-saving method |
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| CN2007101850925A CN101431417B (en) | 2007-11-08 | 2007-11-08 | Network processor and its electricity-saving method |
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| CN101431417A CN101431417A (en) | 2009-05-13 |
| CN101431417B true CN101431417B (en) | 2011-02-09 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1057652A2 (en) * | 1999-05-26 | 2000-12-06 | Seiko Epson Corporation | Printer and charging device |
| US6230276B1 (en) * | 1999-02-01 | 2001-05-08 | Douglas T Hayden | Energy conserving measurement system under software control and method for battery powered products |
| CN1431790A (en) * | 2001-11-30 | 2003-07-23 | 日本电气株式会社 | Power saving method of mobile terminal |
| CN1190930C (en) * | 2000-11-03 | 2005-02-23 | 维斯海半导体有限公司 | Energy saving method for radio receiving carrier modulation data |
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2007
- 2007-11-08 CN CN2007101850925A patent/CN101431417B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6230276B1 (en) * | 1999-02-01 | 2001-05-08 | Douglas T Hayden | Energy conserving measurement system under software control and method for battery powered products |
| EP1057652A2 (en) * | 1999-05-26 | 2000-12-06 | Seiko Epson Corporation | Printer and charging device |
| CN1190930C (en) * | 2000-11-03 | 2005-02-23 | 维斯海半导体有限公司 | Energy saving method for radio receiving carrier modulation data |
| CN1431790A (en) * | 2001-11-30 | 2003-07-23 | 日本电气株式会社 | Power saving method of mobile terminal |
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| CN101431417A (en) | 2009-05-13 |
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