CN101426134A - Hardware device and method for video encoding and decoding - Google Patents
Hardware device and method for video encoding and decoding Download PDFInfo
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- CN101426134A CN101426134A CN 200710094187 CN200710094187A CN101426134A CN 101426134 A CN101426134 A CN 101426134A CN 200710094187 CN200710094187 CN 200710094187 CN 200710094187 A CN200710094187 A CN 200710094187A CN 101426134 A CN101426134 A CN 101426134A
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Abstract
The invention discloses a hardware device for video encoding/decoding, whose line conversion module and row conversion module are in a concurrent one-dimensional cosine transform structural form. The hardware device for video encoding/decoding includes: four parallel arithmetic shift adders, the output terminal of each shift adder is respectively in direct connection with an accumulator and is connected to another accumulator through an inverter. The present invention also discloses a method for video encoding/decoding, includes: performing a two-dimension cosine transform of an image data by performing line conversion process and row conversion process to the quantized data to be processed, wherein the line conversion module and row conversion module are in a concurrent one-dimensional cosine transform; performing eight times of multiply operation and additive operation, for realizing one-dimensional cosine transform of a block row or line after eight clock periods. The invention has features of high hardware processing data throughput rate, capability of completing the two-dimension conversion of a video macro block in no less than 600 clock cycles, capability of realizing high definition video real time encoding/decoding under low clocking frequency, simple hardware implementation, smaller size, and capability of supporting process to various dimensions of data blocks without increasing the control logic complexity.
Description
Technical field
The present invention relates to a kind of hardware unit that is used for coding and decoding video, the invention still further relates to a kind of method that is used for coding and decoding video based on said apparatus.
Background technology
Ahmed, Natarajan and Rao have at first proposed the DCT algorithm in 1974.From that time, it becomes image and the most popular algorithm of video coding, is widely used in the encryption algorithm of various video formats JPEG for example, MPEGx, H26x, VCl and AVS etc.It has following several having a few, and the first, through after the conversion, it can concentrate on low frequency component with the main information of image, and breaks correlation of data.The second, it can effectively utilize software or hardware to realize.People begin one's study very early its quick implementation algorithm and realization technology, and these methods also have pluses and minuses separately.
Present existing implementation method comprises that based on the fast algorithm of butterfly computation and distributed concurrent operation etc. the foothold of these algorithms also all is to reduce addition and multiplying in the calculating process, particularly reduces or avoid the multiplying of consumes resources.
Utilize the architectural feature of cosine transform battle array based on the fast algorithm of butterfly computation, by merging identical arithmetic element, simplified the computation complexity of conventional computing greatly, yet for hardware is realized, its data flow of this method is an irregularity, the control logic more complicated.Its structure is all fixed for every kind of conversion simultaneously, and its flexibility is just poor, at present popular coding standard, VCl just has 8 x, 8,8 x, 4,4 x 8,4 four kinds of different alternative types of 4 x, H264 also has 8 x 8 and 4 two kinds of alternative types of 4 x.So butterfly computation lacks flexibility, because be difficult to shared processing unit.The distributed parallel computing just was suggested before two more than ten years, and was widely used in the hard-wired mechanism.Because the DCT computing needs a large amount of multiplying and add operation, the main starting point of distributed algorithm is at first calculated all possible coefficient exactly in the middle of calculating process, and they are kept among ROM or the RAM, obtain final result then by tabling look-up, so just can be converted to the displacement addition to the multiplying of complexity, also reduce the number of times of multiply-add operation simultaneously.Yet its shortcoming is to need more processing unit, additionally also has the memory cell of a storage intermediate object program, realizes that area is bigger; It can not well compatible different alternative types equally.
Summary of the invention
Technical problem to be solved by this invention provides a kind of hardware unit that is used for coding and decoding video, it can improve the speed of hardware handles, satisfy the needs of HD video encoding and decoding, realize simple, and conversion process that can compatible different size vedio data piece.For this reason, the present invention also will provide a kind of method that is used for coding and decoding video based on said apparatus, can only use several simple processing units, and processing unit itself has only simple addition and shifting processing, directly calculate the coefficient after the image transitions, finish two-dimensional cosine transform video image.
In order to solve above technical problem, the invention provides a kind of hardware unit that is used for coding and decoding video, comprise successively connecting: the forward direction ping-pong buffer, carry out buffer memory when being used to read pending quantized data; The line translation module is used for that the data of preceding paragraph ping-pong buffer are carried out line translation and handles; Middle ping-pong buffer is used for the data after the line translation resume module are carried out buffer memory; The rank transformation module is used for that the data through line translation of middle ping-pong buffer are carried out rank transformation and handles; Ping-pong buffer is used for the dateout after handling is carried out buffer memory as a result; Wherein line translation module is connected with the rank transformation control module with the line translation control module respectively again with the rank transformation module, and this line translation control module and rank transformation control module are controlled the data processing of line translation module and rank transformation module respectively; Line translation module and rank transformation module are one dimension cosine transform version, and its circuit comprises: the displacement adder of four concurrent operations is used to realize the multiplying to a view data; Output of each displacement adder directly connects an accumulator respectively and is connected another accumulator by an inverter, the result of each time multiplying that is used to add up.
The present invention also provides a kind of method that is used for coding and decoding video based on said apparatus, and pending quantized data is handled the two-dimensional cosine transform of realizing a view data through line translation processing and rank transformation; Wherein, line translation processing and rank transformation are treated to parallel one dimension cosine transform, comprise: with the delegation of one 8 * 8 vedio data or 8 data coefficients of row, be shifted with the displacement adder, control the quantitative value that each data coefficient is shifted by coefficient index, realize 8 multiplyings; The result that will get multiplying with 8 accumulators adds up respectively, finishes the data processing of delegation or row; Finish the one dimension cosine transform of one 8 * 8 vedio data row or column through 8 clock cycle.
Because the hardware unit that is used for coding and decoding video of the present invention utilizes the characteristic of the symmetry of the characteristics of coding standard conversion coefficient of various main flows and conversion battle array, hardware configuration is simple to be realized easily.The method that is used for coding and decoding video of the present invention is in addition only used several simple processing units, and processing unit itself has only simple addition and shifting processing, can improve the speed of hardware handles, satisfies the needs of HD video encoding and decoding.It is the video image blocks data transaction of the compatible different size of caching data block that the present invention also has an important characteristic, and the alternative types cost is very little.
Description of drawings
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail.
Fig. 1 is the system construction drawing that is used for the hardware unit of coding and decoding video of the present invention;
Fig. 2 is the graph of a relation of different size data block of the present invention corresponding data in buffer memory;
Fig. 3 is an one dimension cosine converting circuit structure chart of the present invention.
Embodiment
The system configuration that is used for the hardware unit of coding and decoding video of the present invention as shown in Figure 1 comprises successively connecting: forward direction ping-pong buffer, line translation module, middle ping-pong buffer, rank transformation module, ping-pong buffer as a result; Wherein line translation module is connected with the rank transformation control module with the line translation control module respectively again with the rank transformation module.By adopting the method for independently one dimension cosine line translation and rank transformation parallel pipeline processing, improve the speed of hardware handles, satisfy the needs of HD video encoding and decoding.
When in the DCT algorithm vedio data piece being carried out line translation and rank transformation, the formula of data is behind the computational transformation:
Wherein, A
kBe the data coefficient of inputted video image data, its value is generally constant, X
kIt is the vedio data of input.Above-mentioned equation can be expressed in matrix as:
If A (1)
1A
2A
LBe the binary system signed integer of N bit, then formula (1) can be converted into:
In formula (2), order matrix
A is called the adder array matrix, can finds that the A matrix only contains ' 0 ', ' 1 ' two kinds of elements, examination popular encoding and decoding standard at present can find that the A matrix still is a sparse matrix, promptly the vectorial most elements of the row in the matrix is ' 0 '.Each element of Y vector is exactly a few element sum in the X vector like this, the calculating of Y is as long as addition and two kinds of computings of displacement just can realize, and implementation structure can be simple especially, consider the symmetry of trigonometric function simultaneously, we can only use than routine and lack the processing that half parallel processing element is realized being shifted and added.
Analysis by front sum of products computing, analyze the coefficient matrix of conversion of the video encoding and decoding standard of present main flow simultaneously, can find that coefficient is fairly simple, the present invention utilizes this characteristics, and the method that adopts displacement to add has replaced the add operation of taking advantage of in the common cosine transform.As shown in Figure 3, be the hardware structure diagram of one dimension cosine transform, its circuit comprises: the displacement adder of four concurrent operations is used to realize the multiplying to a view data; The input of each displacement adder connects coefficient A1, A2, A3 and the A4 of view data respectively, and output directly connects an accumulator respectively and is connected another accumulator ACCU by an inverter, the result of each time multiplying that is used to add up.
The method that is used for coding and decoding video of the present invention is that pending quantized data is handled the two-dimensional cosine transform of realizing a view data through line translation processing and rank transformation; Wherein, line translation processing and rank transformation are treated to parallel one dimension cosine transform, comprise: with the delegation of one 8 * 8 vedio data or 8 data coefficients of row, be shifted with the displacement adder, control the quantitative value that each data coefficient is shifted by coefficient index, realize 8 multiplyings; Result with described multiplying adds up respectively with 8 accumulators, finishes the data processing of delegation or row; Finish the one dimension cosine transform of one 8 * 8 vedio data through 8 clock cycle.Above-mentioned processing method to video image promptly is applicable to the black and white video image, also is applicable to color video frequency image.
Another emphasis of the present invention is the conversion of different size data block, in order to make one dimension cosine transform structure better as much as possible, easier 8 x 8 that are applicable to, 8 x 4, the map function of 4 x, 8,4 x 4, at first, we are example with the H264 standard, and H264 supports the conversion of 8 x 8 and 4 x 4 simultaneously.
H264 4 x 4 conversion:
Fi0＝di0+di2+di1+(di3>>1)
Fi1＝di0-di2+(di1>>1)-di3
Fi2＝di0-di2-(di1>>1)+di3
Fi3＝di0+di2-di1-(di3>>1)
H264 8 x 8 conversion:
e
I1=-d
I3+ d
I5-d
I7-(d
I71), wherein, i is 0 to 7 integer
e
I3=d
I1+ d
I7-d
I3-(d
I31). wherein, i is 0 to 7 integer
e
I5=-d
I1+ d
I7+ d
I5+ (d
I51). wherein, i is 0 to 7 integer
e
I7=d
I3+ d
I5+ d
I1+ (d
I11), wherein, i is 0 to 7 integer
gi0＝di0+di2+di1+(di3>>1)+ei7-(ei1>>2)
gi1＝di0-di2+(di1>>1)-di3+(ei3>>2)-ei5
gi2＝di0-di2-(di1>>1)+di3+ei3+(ei5>>2)
gi3＝di0+di2-di1-(di3>>1)+ei1+(ei7>>2)
gi4＝di0+di2-di1-(di3>>1)-ei1-(ei7>>2)
gi5＝di0-di2-(di1>>1)+di3-ei3-(ei5>>2)
gi6＝di0-di2+(di1>>1)-di3-(ei3>>2)+ei5
gi7＝di0+di2+di1+(di3>>1)-ei7+(ei1>>2)
Above-mentioned formula is that we have done suitable distortion to the conversion in the standard, makes it can satisfy the structure that we propose in form.Contrast variation is Fi0 and gi0 as a result, Fi1 and gi1, and Fi2 and gi2, Fi3 and gi3 can find that 4 x, 4 conversion are easy to be planned to a kind of special case of 8 x, 8 conversion, this just shares the good condition of having created for structure.And the hardware implementation structure of the one-dimensional transform that the present invention proposes is very easy to accomplish this point especially.Secondly, examination has the VCl standard of four kinds of variations again, can observe similar result equally.
Video encoding and decoding standard is divided into the basic size block of 8 x, 8 pixel units or 4 x, 4 pixel units with an image, with basic block (8 x 8 or 4 x 4) or the standard that has, also continues to segment out the conversion of 8 x 4 and 4 x 8 such as VCl in basic block then.The present invention has taken into account the demand of the mapping hardware realization of similar this standard, and as a basic transforming object, 8 x, 4,4 x 8 of other types and 4 x 4 are by the specific type of appropriate processing as 8 x, 8 conversion with one 8 x 8 pixel blocks.
As shown in Figure 2, the present invention to row (row) the input data of conversion before carrying out carry out map operation one time, make the subsequent conversion module handle the data of input with uniform way.Forward direction ping-pong buffer of the present invention, middle ping-pong buffer and as a result ping-pong buffer be the storage organization of 8 * 8 block caches, to be transformed when obtaining, according to the size of present input data piece, if 4 of 8 x 8 or 8 x, then deposit in the buffer memory, shown in preceding two row among Fig. 2 by input sequence.If current is 4 x 8, then will imports data and shown in the third line of Fig. 2, shine upon.If current block is 4 x 4, then will imports data and shown in the fourth line of Fig. 2, shine upon.The purpose of doing like this is can read with uniform way when second goes on foot the reading of data conversion.
Cosine transform can be broken correlation of data, the main information of image is concentrated on low frequency component, for the compression of image is laid a good foundation.Row-column transform among the present invention is parallel running, and line translation is to a piece, no matter is that the row among 8 x, 8,8 x, 4,4 x, 8,4 x 4 carries out the one dimension cosine transform; Rank transformation carries out the one dimension cosine transform to the row in the piece.Elaborate with a specific embodiment below.
One dimension cosine line translation operation: the forward direction ping-pong buffer write several in, the line translation module reads previous ready prepd 8 x, 8 data blocks, we are transformed to example with 8 x 8, be illustrated in figure 3 as the hardware implementation structure of one-dimensional transform, A is the coefficient of cosine transform, be constant, coefficient index is the variable of corresponding each constant coefficient position, and Y is the result of conversion.For the image pixel of each input, utilize the symmetry of trigonometric function, we use the displacement of 4 concurrent operations to add logic and realize 8 traditional multiplyings, and the number that obtains then enters accumulator and carries out accumulating operation.After data line in the piece was all through unit shown in Figure 3, we just can obtain 8 coefficients after the one dimension line translation.Said method is for 8 x, 4 data blocks, 4 x, 8 data blocks, and 4 x, 4 data blocks have compatibility.
Ping-pong buffer in the middle of the result of one dimension cosine line translation is stored in the example that is transformed to of 8 x 8, is per 8 clock cycle to obtain 8 data after the conversion still.Give the address of each data allocations according to the position of place frequency domain behind the one-dimensional transform so at middle ping-pong buffer.Equally for 8 x, 4 data blocks, 4 x, 8 data blocks, 4 x, 4 data blocks have compatibility.Simultaneously, it is pointed out that this part operation is that next line with current block is the operation that overlaps.
The operation of one dimension cosine rank transformation.This part operation and aforesaid cosine line translation operation parallel processing.Operating process and cosine line translation class of operation seemingly, difference is just carried out conversion to the row of a piece.
Claims (7)
1, a kind of hardware unit that is used for coding and decoding video comprises successively connecting:
The forward direction ping-pong buffer carries out buffer memory when being used to read pending quantized data;
The line translation module is used for that the data of described preceding paragraph ping-pong buffer are carried out line translation and handles;
Middle ping-pong buffer is used for the data after the described line translation resume module are carried out buffer memory;
The rank transformation module is used for that the data through line translation of ping-pong buffer in the middle of described are carried out rank transformation and handles;
Ping-pong buffer is used for the dateout after video image is handled is carried out buffer memory as a result;
Described line translation module is connected with the rank transformation control module with the line translation control module respectively again with the rank transformation module, and described line translation control module and rank transformation control module are controlled the data processing of described line translation module and rank transformation module respectively;
It is characterized in that described line translation module and described rank transformation module are one dimension cosine transform version, its circuit comprises:
The displacement adder of four concurrent operations is used to realize the multiplying to a view data;
The output of described each displacement adder directly connects an accumulator respectively and is connected another accumulator by an inverter, the result of each time multiplying that is used to add up.
2, the hardware unit that is used for coding and decoding video as claimed in claim 1 is characterized in that, described forward direction ping-pong buffer, middle ping-pong buffer and as a result ping-pong buffer be the storage organization of 8 * 8 block caches.
3, the hardware unit that is used for coding and decoding video as claimed in claim 1 is characterized in that, described line translation module and rank transformation module are parallel pipeline structure.
4, a kind of method that is used for coding and decoding video is handled the two-dimensional cosine transform of realizing a view data with pending quantized data through line translation processing and rank transformation; It is characterized in that, described line translation processing and rank transformation are treated to parallel one dimension cosine transform, comprise: with the delegation of one 8 * 8 vedio data or 8 data coefficients of row, be shifted with the displacement adder, control the quantitative value that each data coefficient is shifted by coefficient index, realize 8 multiplyings; Result with described multiplying adds up respectively with 8 accumulators, finishes the data processing of delegation or row; Finish the one dimension cosine transform of one 8 * 8 vedio data row or column through 8 clock cycle.
5, the method that is used for coding and decoding video as claimed in claim 4, it is characterized in that, described line translation processing and rank transformation all carry out metadata cache when handling reading of data and dateout, described metadata cache comprises data block is converted to 8 * 8 metadata cache forms.
6, the method that is used for coding and decoding video as claimed in claim 5 is characterized in that, described metadata cache comprises to be changeed 8 * 4 data blocks, 4 * 8 data blocks or 4 * 4 data blocks are converted to 8 * 8 metadata cache forms.
7, the method that is used for coding and decoding video as claimed in claim 4 is characterized in that, the described method that is used for coding and decoding video is applicable to black and white video image and color video frequency image.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102075762A (en) * | 2010-12-31 | 2011-05-25 | 北京大学深圳研究生院 | Inter-frame predictor circuit for video encoder and method for implementing same |
| CN102075765A (en) * | 2010-12-31 | 2011-05-25 | 北京大学深圳研究生院 | Chroma interpolation circuit for video codec and realization method thereof |
| CN102395031A (en) * | 2011-11-23 | 2012-03-28 | 清华大学 | Data compression method |
| CN102857756A (en) * | 2012-07-19 | 2013-01-02 | 西安电子科技大学 | Transfer coder adaptive to high efficiency video coding (HEVC) standard |
| CN106355195A (en) * | 2016-08-22 | 2017-01-25 | 中国科学院深圳先进技术研究院 | The system and method used to measure image resolution value |
| CN107066239A (en) * | 2017-03-01 | 2017-08-18 | 智擎信息系统（上海）有限公司 | A kind of hardware configuration for realizing convolutional neural networks forward calculation |
| CN112449199A (en) * | 2020-11-19 | 2021-03-05 | 河南工程学院 | One-dimensional DCT/IDCT converter for parallel bit vector conversion and partial product addition |
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2007
- 2007-11-01 CN CN 200710094187 patent/CN101426134A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102075762A (en) * | 2010-12-31 | 2011-05-25 | 北京大学深圳研究生院 | Inter-frame predictor circuit for video encoder and method for implementing same |
| CN102075765A (en) * | 2010-12-31 | 2011-05-25 | 北京大学深圳研究生院 | Chroma interpolation circuit for video codec and realization method thereof |
| CN102075765B (en) * | 2010-12-31 | 2012-12-05 | 北京大学深圳研究生院 | Chroma interpolation circuit for video codec and realization method thereof |
| CN102075762B (en) * | 2010-12-31 | 2012-12-05 | 北京大学深圳研究生院 | Inter-frame predictor circuit for video encoder and method for implementing same |
| CN102395031A (en) * | 2011-11-23 | 2012-03-28 | 清华大学 | Data compression method |
| CN102395031B (en) * | 2011-11-23 | 2013-08-07 | 清华大学 | Data compression method |
| CN102857756A (en) * | 2012-07-19 | 2013-01-02 | 西安电子科技大学 | Transfer coder adaptive to high efficiency video coding (HEVC) standard |
| CN102857756B (en) * | 2012-07-19 | 2015-04-08 | 西安电子科技大学 | Transfer coder adaptive to high efficiency video coding (HEVC) standard |
| CN106355195A (en) * | 2016-08-22 | 2017-01-25 | 中国科学院深圳先进技术研究院 | The system and method used to measure image resolution value |
| CN107066239A (en) * | 2017-03-01 | 2017-08-18 | 智擎信息系统（上海）有限公司 | A kind of hardware configuration for realizing convolutional neural networks forward calculation |
| CN112449199A (en) * | 2020-11-19 | 2021-03-05 | 河南工程学院 | One-dimensional DCT/IDCT converter for parallel bit vector conversion and partial product addition |
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