CN101420620B - Encoded bit number estimation method in AVS video coding and apparatus thereof - Google Patents
Encoded bit number estimation method in AVS video coding and apparatus thereof Download PDFInfo
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Abstract
The invention discloses a coding bit number estimation method and a coding bit number estimation device in AVS video coding, belonging to the field of video coding and decoding. The method is as follows: quantization coefficients of a transform block are firstly grouped to be input and output in two register groups in parallel; then coding coefficient (run, level) of each group of the quantization coefficients is simultaneously calculated in the same clock; the coding and the calculation of the coding bit number are respectively carried out on run and level of the coding coefficients (run, level); and the bit number of the Golomb coding is finally summed to obtain the coding bit number of the coding coefficients (run, level) of the whole transform block. The device comprises a data storage module, a scanning module, a Golomb module and a bit number summing module which are sequentially connected. Compared with the prior art, the method eliminates the traditional serial scanning and the table looking-up. The data processing capacity of the device is 8 times of that of the traditional method, and the area is about one third of that of the traditional method.
Description
Technical field
The present invention relates to coded-bit number estimation method and device thereof in a kind of AVS video coding, this method is mainly used in the message source process field, especially the coding and decoding video field.
Background technology
In coding and decoding video, estimation and mode decision part all exist to be accepted or rejected the video of different mode.Second generation audio and video standard has proposed the cost function C=D+ λ R based on RDO (Rate-Distortion Optimization).Wherein D represents the distortion factor of video, the needed bit number of R presentation code video, and λ represents the weight factor of D and R, is Lagrangian constant.
The AVS standard is the novel video coding technique that has independent property right and autonomous innovation technology, and video section (AVS-P2) has formally become national standard at present.The AVS video coding has adopted 16x16,16x8,8x16,8x8, direct and intra6 kind predictive coding pattern.Because the pattern of prediction is various, in real-time coding, will handle lot of data information in the unit interval.Although hardware-acceleratedly can bring advantage on the execution speed, also face the challenge of time and area for the Video processing of high definition size to whole encoder.The present invention is the important step during the AVS encoder hardware quickens to realize, in the encoder, the complexity of RDO accounts for 40% of whole encoder complexity greatly, and this process mainly is that the data of various predictive modes are handled, and calculates the cost of every kind of predictive mode.
In the first generation audio and video standard, people have only considered the distortion factor D of video, and decide this to adopt the sort of predictive mode with the size of D, though this decision-making mode has been brought very big raising to video quality, simultaneously also increased load, be unfavorable for transmission to channel width.In second generation audio and video standard, the thought that has adopted picture quality and channel width to combine has proposed the notion of RDO.D weighs video quality with the distortion factor, and bit number R weighs shared channel width, the raising of both very big degree of combination the overall performance of encoder.R adopts is that the technology of entropy coding is encoded the data of every kind of pattern according to the method for entropy coding, calculates every kind of needed bit number of pattern with this.The raising that the decision-making technique of RDO has been brought performance to whole encoder, the high complexity of RDO realization simultaneously also makes people have certain scruples.When entropy coding calculated R, AVS had adopted the 2D-VLC technology, with the easiest appearance (run, level) combination has been added up into 19 forms, and these forms also need to spend the cost of great number when hardware is realized.Cost function C=D+ λ R is the cost function that is used for estimating various predictive modes, and it has only needed the true cost of close approximation just, does not need real D and R.The present invention has adopted a kind of new method to approach R, and this method has solved the RDO oversize and too much problem of hardware resource consuming time substantially.
Summary of the invention
The present invention is directed to the RDO module of AVS standard, provide a kind of efficient hardware to quicken to realize.Main purpose of the present invention is to provide coded-bit number estimation method and the device thereof in a kind of AVS video coding, to improve the speed of encoder, reduces hardware spending, thereby reaches the real-time of coding.In addition, the present invention is a module during our designed encoder hardware is realized, this module can be used for estimation and two parts of the mode decision in later stage in early stage.
Wherein, mode decision accounts for 30% of whole encoder complexity, and its effect is a cost of calculating every kind of pattern, selects the pattern of the pattern of cost minimum as last coding.Here cost function is defined as: C=D+ λ R, and the wherein distortion of D presentation code, R represents the needed bit wide of coefficient (bit number).The calculating of bit wide R is relevant with entropy coder, but does not in fact really produce code stream output.Just because of this, the present invention has adopted a kind of new approximate R of method to approach real R.
Technical scheme of the present invention is:
Coded-bit number estimation method in a kind of AVS video coding the steps include:
1) the quantization parameter grouping with transform block walks abreast input and output in two registers group;
2) calculate in the same clock every group of quantization parameter code coefficient (run, level);
3) to code coefficient (run, level) run in and level encode respectively, calculate the number of coded bits of this code coefficient;
4) add number of coded bits with above-mentioned code coefficient, obtain code coefficient (run, number of coded bits level) of whole transform block.
The parallel input and output of described quantization parameter grouping in the method for two registers group are:
1) the behavior unit of described quantization parameter with the place transform block divided into groups;
2) in a clock, deposit one group of quantization parameter in a registers group;
3) this transform block is input to this registers group by group is all parallel after, at next clock from this registers group according to the order of zig-zag by the parallel output of group quantization parameter, begin another registers group of the parallel input of follow-up grouping quantization parameter from this clock simultaneously;
4) repetition above-mentioned steps 1)～3), realize the ping-pong operation of two registers group.
Code coefficient (the run of every group of quantization parameter of described calculating, level) method is: quantization parameter in the parallel distance of swimming scan register group, respectively to each non-zero quantized coefficients produce a code coefficient (run, level) right, it is right that zero coefficient is produced (0, a 0) code coefficient.
The level value of described code coefficient is the absolute value of quantization parameter; The rum value calculating method of described code coefficient is: set a variable base0 and be used for being used to write down the number at every group of quantization parameter end adjacent 0 and the line number that a counter counter is used to write down this transform block to run value assignment, a variable basel; Counter=0, base0=0;=0 o'clock, if basel=8, if the base0=base0+basel of next group quantization parameter was basel!=8, the base0=base1 of next group quantization parameter.
At first judge described code coefficient in the described method to whether being zero, to described non-zero code coefficient to encoding.
It is described that (run when level) run in and level encode respectively, adopts 2 rank Golomb coding to the brightness data in the code coefficient, and the chroma data in the code coefficient is adopted 0 rank Golomb coding to code coefficient.
Adopt formula Golomb (run)=Golomb (2run+60)-Golomb (59) to calculate the bit number of described run value in the described method; Adopt formula Golomb (level) to calculate the bit number of described level value.
Number of coded bits estimation unit in a kind of AVS video coding is characterized in that comprising successively the data memory module, scan module, the Golomb module that connect, bit number adds and module;
Described data memory module is used to store the quantization parameter after the quantification, and it comprises that two storage matrix are used for realizing the ping-pong operation of data input and output;
Described scan module is used for the dateout of described data memory module is carried out zig-zag scanning, obtain each pixel code coefficient (run, level) right;
Described Golomb module is used to calculate code coefficient (run, number of coded bits level) of described scan module output;
Described bit number add with module be used to add with the Golomb coding after number of coded bits, obtain the bit number of whole transform block.
Described Golomb module comprises 3 MUX, 1 shift unit, 3 adders and 2 cascade comparators, its annexation is: the selection signal input part of described 3 MUX is connected with the data type data wire respectively, and the input of a described MUX MUX0 is connected with 61 inputs with data 64 respectively, the input of a described MUX MUX1 is connected with 4 with data 1 respectively, and a described MUX MUX2 is connected with-11 with data-9 respectively; Described shift unit input is connected with the run value output of described code coefficient; The output of described shift unit output and described MUX MUX0 is connected with an adder input respectively, and this adder output is connected with a described cascade comparator input terminal; The level value output of described MUX MUX1 output and described code coefficient is connected with another described adder input respectively, and this adder output is connected with another described cascade comparator input terminal; Described 2 cascade comparator output terminals are connected with remaining another described adder input respectively with described MUX MUX2 output.
Described MUX is the constant selector, and the selection signal of described constant selector is the data type signal; Described data type comprises chroma data and brightness data.
The method of hardware designs of the present invention is:
1) Bing Hang processes pixel: the present invention adopts the parallel structure of 8 pixels when calculating bit number R.Utilize the registers group of 2 8x8, the data after quantizing are carried out ping-pong operation, all be 8 pixel inputs and 8 pixel outputs, to guarantee carrying out smoothly of streamline at every turn.
2) parallel zig-zag scans: traditional zig-zag carries out serial scan according to the order of zig-zag, and the present invention proposes a kind of hardware implementation method of and line scanning.Make corresponding to each clock of hardware all can have 8 to (run, level) output.
3) to 2) it is described that (run, level) carry out the Golomb coding: (run's method of traditional calculations bit number level) encodes according to the step of entropy coding, obtains every pair of (run, level) needed bit number with all.And the present invention has omitted the intermediate steps of most of entropy coding, directly with (run level) carries out the Golomb coding, has saved a large amount of hardware costs.
4) to 3) described (run, level) bit number behind the coding is regulated: because the present invention adopted 3) bit number of described method design factor, with real bit number certain difference is arranged, in order to make the result can approach real bit number more, the present invention is to 3) described Golomb coding done a little special constraints, comprise: only the coefficient of non-zero is encoded, brightness data adopts 2 rank Golomb coding, chroma data adopts 0 rank Golomb coding, the bit number that the bit number of run equals direct coding 2run+60 deducts the bit number of direct Golomb coding 59, be Golomb (run)=Golomb (2run+60)-Golomb (59), the bit number of level equals the bit number of direct Golomb coding level, i.e. Golomb (level).
5) the present invention changes traditional look-up method when specific implementation Golomb encodes, in conjunction with (run, size of data level) adopt the cascade comparator to substitute and table look-up, and have improved speed, have reduced hardware resource.
Module hardware device of the present invention comprises: data memory module, and scan module, the Golomb module, bit number adds and module.
1) data memory module of the present invention is mainly used to the coefficient after buffer memory quantizes.Mainly the data BUFF by 2 8x8 carries out ping-pong operation, mode of operation be one of them BUFF when the input data, another one BUFF dateout, by the time behind 8 clocks, just the data processing of whole transform block is intact, and ping-pong operation is finished in the input and output of two BUFF of exchange.Import according to pixel order during input, export according to zig-zag order during output.
2) scan module of the present invention is mainly used to 9) dateout carry out zig-zag scanning, obtain each pixel (run, level).For size is 0 pixel, is designated (0,0).The present invention scans the pixels of 8 parallel inputs simultaneously, through export simultaneously after this resume module 8 to (run, level).Traditional scan method, a record size are not equal to 0 pixel, and (run level), do not deal with equaling 0 pixel, and traditional zig-zag can only serial scan.Therefore this algorithm has brought high efficiency data processing speed to whole system.
3) Golomb module of the present invention is mainly used to calculate every pair of (run, number of coded bits level).The part invention is used MUX when hardware is realized, substituted traditional Golomb look-up table, has improved speed, has saved hardware resource simultaneously.On the algorithm, with the bit number of the next approximate coding run of Golomb (2run+60)-Golomb (59), the bit number of coding level then directly uses Golomb (level) approximate.Compare with traditional algorithm, omit the most of module in the entropy coding process, saved a large amount of hardware resources.
4) bit number of the present invention add with module be used to add with the Golomb coding after bit number, obtain the bit number R of whole transform block.
Good effect of the present invention is:
In second generation video standard, the notion of having introduced RDO has improved the overall performance of video significantly, yet the cost of RDO has also accounted for 40% of whole encoder, and the designer is felt confused when using RDO.R in the RDO design is the bit number of coding, and conventional method is to utilize the entropy coding direct coding to obtain bit number.In the AVS standard, only the complexity of entropy coding is just very high, so the bit number how to obtain encoding with simpler method has just become the hot issue of studying in the video field.(run, method level) have been removed traditional serial scan and have been tabled look-up to the present invention proposes a kind of parallel direct coding.Data-handling capacity of the present invention is 8 times of conventional method, and area is about 1/3 of conventional method.
Description of drawings
Fig. 1. the RDO schematic diagram of traditional AVS;
Fig. 2. traditional AVS calculates the schematic diagram of bit number R;
Fig. 3. schematic diagram of the present invention;
Fig. 4. the schematic diagram of data memory module;
(a) the ping-pong operation schematic diagram of storage matrix,
(b) normal zig-zag scanning sequency,
(c) corresponding address of Buff_register,
Fig. 5. Run-Length Coding hardware pipeline structure;
The hardware pipeline structure chart of Fig. 6 .Golomb coding;
Fig. 7. bit number adds the hardware structure diagram with module.
Embodiment
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
In order to handle in real time the data of giving RDO, the present invention has adopted the parallel structure of 8 pixels when hardware is realized, and economize on hardware cost and minimizing pipeline depth to greatest extent.Excessive and the not enough problem of clock cycle of area when realizing in order to solve RDO hardware, the present invention uses and revises and replace having done on traditional algorithm, proposed some approximate schemes, these schemes comprise: parallel zig-zag scanning, replace the Golomb form with selector; Utilize Golomb respectively to run on the algorithm, level encodes the traditional entropy coding of close approximation to (run, level) right coding.
See also Fig. 3 schematic diagram of the present invention.When calculating bit number R, the inventor is by a large amount of tests and checking, find respectively to run, level encode the gained bit number with utilize entropy coding to (run, level) the encode bit number of gained is very approaching, just utilize this conclusion to carry out hardware designs in the present invention, saved hardware resource greatly.According to the processing sequence of data flow, data memory module, scan module, the Golomb module, bit number adds with module and below will be described in detail each module that relates to.
1. data memory module:
Data bit width behind the change quantization is 12, based on the parallel structure of 8 pixels, the data of each 8x8 piece are advanced into register with one at every turn, in order to guarantee carrying out smoothly of 8 parallel pipelines, this module has adopted the registers group of two 8x8, utilize the ping-pong operation principle, once with per 8 clocks conversion of input and output.The following describes the transformational structure of storage matrix inside.As shown in Figure 4.
The ping-pong operation pattern: in shown in Fig. 4 (a), when storage matrix A imports, the data of output storage matrix B, in like manner, and when output storage matrix A, the data of input storage matrix B, circulation of per 8 clocks just guarantees carrying out smoothly of streamline.Based on the present invention is the data input that walks abreast, and for fear of in the conflict of carrying out order on the Run-Length Coding, we just deposit data in registers group according to the order of data successively when storage, during output just the ordering according to zig-zag export.The parallel processing that this mode of marshal data has again solved data well.Shown in Fig. 4 (b), zig-zag is 0,1,8,16,9,2,3,10,17,24 in proper order ..., corresponding respectively register matrix position is 0,1,2,3,4,5,6,7,8,9 ..., shown in Fig. 4 (c).With one of them matrix is example, and the clock arrangement of data flow is described: first clock, will export the data of 0,1,8,16,9,2,3,10 these 8 address correspondences; Second clock will export 17,24,32,25,18,11,4,5 The 8th clock will export 53,60,61,54, the data of 47,55,62,63 address correspondences; To the 9th clock, the data of another one matrix have been imported and have been finished, and can forward the output of another matrix to.
2. scan module
The Run-Length Coding algorithm structure as shown in Figure 5, this module functions is exactly that the number in the registers group is carried out Run-Length Coding, scan matrix each the number, to the coefficient of each non-zero, produce respectively one (run, level) right.
Level is the absolute value of input coefficient, can directly ask the coefficient of input to thoroughly deserve.Key is to ask run, because data are parallel inputs, so will construct the reference variable of a run, be made as base0, tentation data is 8 parallel inputs, is designated as { a0, a1, a2, a3, a4, a5, a6, a7}, base0 is used for representing the number of a0 preceding adjacent 0, if a0 is not equal to 0 like this, the run of a0 equals base0; Known the run of a0, with the a0 in the delegation, a1, a2, a3, a4, a5, the run of a6 and a7 just can in the hope of, so, the parallel processing of data just can realize, the interior data that just can handle delegation of clock.
The calculating of base0 is carried out in the following manner:
Parallel be input as example with 8, a counter counter from 0 to 7 at first will be arranged, what be used for representing input in this section clock is the data of same block.Clearly, when counter=0, base0=0; Other the time base0 then be the amount of a variation, for this reason, can define another one variable base1, in 8 data of this row that base1 represents to import, adjacent zero the number at end.For 8 numbers of input, for example: for 0,12,3,0,0,4., 0,0; Basel=2.For 1,0,3,0,0,0,3,7; Base1=0.For 0,0,0,0,0,0,0,0; Base1=8.Base0 can be definite so in sum, counter=0, base0=0;=0 o'clock, if basel=8, if the base0=base0+base1 of next line was base1!=8, the base0=base1 of next line
As shown in Figure 5, the hardware configuration of whole module roughly can be divided into 4 level production lines, with the 8 parallel examples that are input as 4 grades of fluvial processeses is described:
The first order, main some parallel comparators and a counter controls.Use 8 comparators to compare with 0 respectively, judge that whether level equals 0, is designated as sign_zero[0～7]; Counter counter is the umber of beats of input valid data, and per 8 bats are the data of same block8x8.
The second level mainly comprises the comparator of 1 cascade, finishes and looks for 1 logic function.By from sign_zero[0] to sign_zero[7] look for 1 logic can obtain the coefficient of last non-zero each row.Just obtain behind last nonzero coefficient of this row zero number, remembered base1.
The third level mainly comprises 1 selector.Be used for constructing the run value of every first coefficient of row, be designated as base0[5:0]; When counter=0, base0=0, if other the time base1!=8, base0=base1, if base1==8, base0=8+base0.
The fourth stage, mainly comprise 8 comparators, be used for obtaining each coefficient (run, level), here be noted that traditional zig-zag, only the encode coefficient of non-zero is 8 parallel structures because adopt here, so when the coefficient of input equals zero, note (run=0, level=0), also participate in coding, the bit number that needs of only encoding equals 0.Run value base0 before 3rd level has been known first coefficient of every row is in conjunction with sign_zero[7:0], be easy to obtain by comparator, this each coefficient of row (run, level).
3.Golomb module
This module is mainly used to calculate every pair of (run, bit number level).The present invention encodes to run and level separately, calculates then that (run, level) right bit number is by approaching entropy coding to (run, level) right number of coded bits after adjusting.The algorithm adjustment mainly comprises: coding during brightness data with the 2 rank Golomb sign indicating numbers calculating bit number of encoding, during the coding colors degrees of data with the zeroth order Golomb sign indicating number calculating bit number of encoding; The bit number that calculates run is that the bit number with the 2*run+60 that encodes deducts 59 bit number.When utilizing Golomb to calculate bit, the information bit of Golomb sign indicating number has following rule:
M＝floorlog
2(codenum+2
k)，
Wherein, k represents the coding exponent number of Golomb sign indicating number, the numerical value that CodeNumber indicates to encode, the information bit figure place that the M presentation code obtains.Thereby the needed total bit number of coding CodeNumber is:
M_stream＝2M+1-k
On hardware was realized, the present invention optimized, and directly the comparator with cascade has substituted traditional Golomb code table.As shown in Figure 6, mainly be divided into 4 pipelining-stages.
The first order mainly comprises 3 parallel MUX and 1 shift unit.Data_type represents the data type of transform block, adopts 2 rank Golomb coding sign indicating number when for brightness data, so MUX0 gating 64, MUX1 gating 4, MUX2 gating-9 adopts 0 rank Golomb coding when for chroma data, so MUX0 gating 61, MUX1 gating 1, MUX2 gating-11.Shift unit is finished 2*run.
The second level mainly comprises 2 adders.Finish c_run=2*run+60+1＜＜k and c_level=level+1＜＜k.
The third level mainly comprises the comparator of 2 cascades.The bit number of finishing c_run and c_level calculates.Based on the characteristics of Golomb coding, to the cascade of c_run and c_level big-endian relatively, the bit number of this coefficient that can obtain encoding.
The fourth stage mainly comprises 1 adder, finish coding run and level and, i.e. m_run+m_level.
4. bit number adds and module
The bit number that the main effect of this module is used for finishing to all pixels of current 8x8 piece sums up, and tries to achieve the bit number of current block.Because the design is the parallel structures of 8 pixels, so this module has the input of 8 pixels, hardware is divided into level Four when realizing to be finished, as shown in Figure 7.
The first order mainly comprises 4 adders, finishes 8 pixels addition in twos of bit number separately of data.What the design adopted is that pixel R0 adds R1, and R2 adds R3, and R4 adds R5, and R6 adds R7.Certainly other combination also is fine.
The second level mainly comprises 2 adders, finishes four adder output results' of the first order combination in twos.
The third level mainly comprises 1 adder, the bit number of finishing 8 pixels of current line add and.
The fourth stage mainly comprises 1 adder and 1 selector.The pixel of finishing current block 8 row adds up, and the output of selector control current block bit number is arranged.
Claims (6)
1. the coded-bit number estimation method in the AVS video coding the steps include:
1) the quantization parameter grouping with transform block walks abreast input and output in two registers group; Its method is:
A) the behavior unit of described quantization parameter with the place transform block divided into groups;
B) in a clock, deposit one group of quantization parameter in a registers group;
C) this transform block is input to this registers group by group is all parallel after, at next clock from this registers group according to the order of zig-zag by the parallel output of group quantization parameter, begin another registers group of the parallel input of follow-up grouping quantization parameter from this clock simultaneously;
D) repeat above-mentioned steps a)～c), realize the ping-pong operation of two registers group;
2) the code coefficient run and the level of every group of quantization parameter of calculating in the same clock; The code coefficient run of every group of quantization parameter of described calculating and the method for level are: quantization parameter in the parallel distance of swimming scan register group, respectively each non-zero quantized coefficients is produced a code coefficient to run and level, zero coefficient is produced a code coefficient to 0 and 0;
3) code coefficient run and level are encoded respectively, wherein, the brightness data in the code coefficient is adopted 2 rank Golomb coding, the chroma data in the code coefficient is adopted 0 rank Golomb coding; Then, adopt formula Golomb (run)=Golomb (2run+60)-Golomb (59) to calculate the bit number of described run value, adopt formula Golomb (level) to calculate the bit number of described level value;
4) add number of coded bits with above-mentioned code coefficient, obtain the code coefficient run of whole transform block and the number of coded bits of level.
2. the method for claim 1 is characterized in that the absolute value of the level value of described code coefficient for quantization parameter; The run value calculating method of described code coefficient is: set a variable base0 and be used for being used to write down the number at every group of quantization parameter end adjacent 0 and the line number that a counter counter is used to write down this transform block to run value assignment, a variable base1; During counter=0, base0=0; =8, the base0=base1 of next group quantization parameter.
3. the method for claim 1 is characterized in that at first judging described code coefficient to whether being zero, to described non-zero code coefficient to encoding.
4. the number of coded bits estimation unit in the AVS video coding is characterized in that comprising the data memory module, scan module, the Golomb module that connect successively, bit number adds and module;
Described data memory module is used to store the quantization parameter after the quantification, and it comprises that two storage matrix are used for realizing the ping-pong operation of data input and output;
Described scan module is used for the dateout of described data memory module is carried out zig-zag scanning, exports quantization parameter according to the order of zig-zag by organizing to walk abreast; And, respectively each non-zero quantized coefficients is produced a code coefficient to run and level by quantization parameter in the parallel distance of swimming scan register group, zero coefficient is produced a code coefficient to 0 and 0;
Described Golomb module is used for code coefficient run and level are encoded respectively, wherein, the brightness data in the code coefficient is adopted 2 rank Golomb coding, and the chroma data in the code coefficient is adopted 0 rank Golomb coding; Then, adopt formula Golomb (run)=Golomb (2run+60)-Golomb (59) to calculate the bit number of described run value, adopt formula Golomb (level) to calculate the bit number of described level value;
Described bit number add with module be used to add with the Golomb coding after number of coded bits, obtain the bit number of whole transform block.
5. device as claimed in claim 4, it is characterized in that described Golomb module comprises 3 MUX, 1 shift unit, 3 adders and 2 cascade comparators, its annexation is: the selection signal input part of described 3 MUX is connected with the data type data wire respectively, and wherein the input of a MUX MUX0 is connected with 61 inputs with data 64 respectively, the input of one MUX MUX1 is connected with 4 with data 1 respectively, and a MUX MUX2 is connected with-11 with data-9 respectively; Described shift unit input is connected with the run value output of described code coefficient; The output of described shift unit output and described MUX MUX0 is connected with an adder input respectively, and this adder output is connected with a described cascade comparator input terminal; The level value output of described MUX MUX1 output and described code coefficient is connected with another described adder input respectively, and this adder output is connected with another described cascade comparator input terminal; Described 2 cascade comparator output terminals are connected with remaining another described adder input respectively with described MUX MUX2 output.
6. device as claimed in claim 5 is characterized in that described MUX is the constant selector, and the selection signal of described constant selector is the data type signal; Described data type comprises chroma data and brightness data.
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