CN101393604B - Image sampling control system and method for CMOS optical sensor - Google Patents
Image sampling control system and method for CMOS optical sensor Download PDFInfo
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Abstract
The invention discloses an image sampling control system for a CMOS optical sensor, which comprises a CMOS optical sensor (210), a main processor (230), a data memory (240), an internal bus (250) and a CMOS image sampling controller (220), wherein the CMOS optical sensor (210) is connected with a control port (223), the control port (223) is connected with a sampling controller (222) and a buffer(224), the sampling controller (222) is connected with a decoder (221) and a bridge connector (226), the decoder (221) is connected with the bridge connector (226) and a storage controller (225), thestorage controller (225) is connected with the buffer (224), the buffer (224) is connected with the bridge connector (226), and the bridge connector (226) is connected with the inside bus (250). The image sampling control system has good rapidity and can greatly reduce the cost.
Description
Technical field
The present invention relates to a kind of CMOS optical sensor image sampling control system and method.
Background technology
The CMOS optical sensor is a kind of emerging sensitive component, and along with the development of technology, it is aspect chromaticity, noise and susceptibility, all not second to the CCD device, and long service life, cheap.Application constantly enlarges.
Because it is more extensive that the CMOS optical image sensor is used at video field, existing at present various CMOS control chips at Video Applications, or the technology such as control interface and the product of integrated CMOS emerges in chip, as the ZC030X and the VC032X series of Vimicro.These control chips are primarily aimed at Video Applications, and the image of being exported all adopts fixing VGA form, do not possess such as image size, sampling location, monochrome or coloredly select, sampling frame number setting etc. is at the different application environment, the function of flexible configuration.Limited the CMOS optical sensor in the non-video Application for Field.
The fingerprint identification technology that belongs to Biometric biological identification Biometric field, when using the CMOS optical sensor to the finger imaging, do not require color video frequency image output, need only monochrome image, but require speed fast, resource overhead is little or the like, and above-mentioned special integrated circuit or control interface all can not satisfy the fingerprint image sample requirement.
In order to address this problem, in the image sampling of most of built-in optical fingerprint modules, adopt port simulation or interrupt mode.The port simulation is that the CMOS normal working frequency is reduced to 2～3M by 24M, only in the clock signal moment of regulation, from port the view data of CMOS output is sampled, and sample rate has only about per second 3 frames; The external interrupt mode is the pixel signal that goes to respond CMOS output with external interrupt, though interrupt response is faster than port corresponding speed, frequency of operation only is 1/5th～6 of a normal working frequency still at 5～6M.For example adopt the DSP5503 of TI, with interrupt mode 9 two field pictures of can only sampling.Far can not reach the standard speed of per second 30 frames.Though can adopt system resource abundant, the chip that arithmetic speed is high solves the problems referred to above, the system cost costliness loses more than gain.
Summary of the invention
In order to overcome the deficiency that rapidity is poor, cost is high of the image sampling system that has the built-in optical fingerprint module, the invention provides a kind of rapidity is good, reduce cost greatly CMOS optical sensor image sampling control system and method.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of CMOS optical sensor image sampling control system, comprise CMOS optical sensor 210, primary processor 230, data-carrier store 240 and internal bus 250, described CMOS optical sensor 210 connects internal bus 250, described internal bus 250 is connected with primary processor 230, described primary processor 230 is connected with data-carrier store 240, described sampled-data control system also comprises cmos image sampling controller 220, and described cmos image sampling controller 220 comprises:
Sampling parameter, sample pattern information, and accept the sampling execution state information that control port 223 feeds back;
As preferred a kind of scheme: described sampling controller 222 comprises: sampling parameter module 2221, in order to deposit the reference position of sampled images, default sampling line number, current sampling line number, default sampling columns, current sampling columns, default sampling frame number, current sampling frame number; Sampling pattern module 2222 is used to determine to full row or interlacing pixel, still is full row or every the row pixel sampling; And in interlacing with under row sampling situation, selected is the odd number or the data of even number row and column pixel; Port status module 2223 is used for reflecting in real time the information from a relevant pixel sampling of control port 223 is finished, delegation's image sampling is finished and two field picture sampling is finished; Sampling enable module 2224 is used for pixel sampling, row sampling, three kinds of sampling patterns of frame sampling are enabled, and stipulates the level signal feature that above-mentioned three kinds of sampling patterns enable to begin and the level signal feature of end.
As preferred another kind of scheme: described sampling pattern module 2222 adopts one 32 bit register to realize that the content of being controlled comprises: image sampling enables, data-moving request, row synchronizing signal are selected, line synchronizing signal is selected, row sampling pattern, row sampling pattern, partiting row sampling pattern, select every row sampling pattern and pixel clock PCLK significant level.
As preferred another scheme: described bridge 226 is an interface circuit, and the concrete regulation of described interface circuit is a table 1:
| Signal | Direction | Note |
| cisc_reset | Input | Sampling controller resets |
| cisc_csn | Input | Sampling controller enables |
| cisc_clock | Input | The synchronous logic clock |
| cisc_read | Input | Read gate |
| cisc_write | Input | Write gate |
| cisc_addr[2:0] | Input | Address bus |
| cisc_data[31:0] | I/O | Data bus |
| cisc_ready | Output | Bus is ready |
| cisc_int_req | Output | Interrupt request |
Table 1.
Further, described sampling parameter module 2221 comprises: address register, in order to deposit the reference position of sampled images; The row sample register is in order to deposit default sampling line number, current sampling line number; The row sample register is in order to deposit default sampling columns, current sampling columns; The frame sampling register is in order to deposit default sampling frame number, current sampling frame number.
Further again, described sampling pattern module 2222 contains the controlling of sampling register.
Described port status module 2223 contains status register.
Further, described sampling enable module 2224 comprises: enable register is used for pixel sampling, row sampling, three kinds of sampling patterns of frame sampling are enabled; Enable to begin register, in order to the level signal feature of stipulating that above-mentioned three kinds of sampling patterns enable to begin; Enable end register, in order to the level signal feature of stipulating that above-mentioned three kinds of sampling patterns enable to finish.
A kind of CMOS optical sensor image sampling control method, this method comprises the steps:
1) reference position of default sampled images, sampling line number, sampling columns, sampling frame number, and these parameters are stored in the related register of sampling parameter 2221;
2) determine the requirement of sampled images tone, promptly make a kind of selection: 1 full color in following three kinds of alternativess; Any in the 2RGB three primary colors; In the 3RGB three primary colors any two kinds;
3), find out the corresponding pass that this tone and CMOS optical sensor pixel distribute according to the tone that described selection determined; Be converted into full row be listed as sampling entirely, with the multiple sampling pattern of the initial interlacing of odd or even row or column every the row sampling, and described sampling pattern parameter is stored in the related register of sampling pattern 2222;
4) size of decision buffer 224 buffer zones is stored in it in data depth register 2251 of memory controller 225;
5) control port 223 is enabled;
6) make control port 223,, in the presence of the synchronizing signal that CMOS optical sensor 210 is exported, the view data of CMOS optical sensor 210 outputs is sampled according to the parameter that sampling parameter 2221, sampling pattern 2222 provide;
7) control port 223 is in sampling process, and the situation of will sampling is in real time write in people's port state register 2223 with code form, and described sampling situation comprises: pixel sampling is finished, delegation's image sampling is finished and two field picture sampling is finished;
8) under primary processor 230 control, buffer 224 is accepted image sampling data that CMOS optical sensor 210 transmits via control port 223 as buffering, then with the monoblock data by bridge 226, via internal bus 250, be sent to data-carrier store 240.
Technical conceive of the present invention is: with the mode that increases hardware resource, solve existing CMOS optical sensor in the image sampling process hardware sampling pattern dullness, do not possess configurability, cause in the big data quantity sampling process under embedded or system-on-a-chip environment the software and hardware resources unbalanced technical bottleneck of loading.
Beneficial effect of the present invention mainly shows: 1, rapidity good, reduce cost greatly; 2, the cpu resource and the additional period of pure software sampling additive decrementation have been saved; 3, the IP logic is simple, is convenient to be integrated into embedded system, and even in the system-on-a-chip.
Description of drawings
Fig. 1 is a synoptic diagram of gathering fingerprint image with the CMOS optical sensor;
Fig. 2 is a kind of CMOS optical sensor pel array distribution schematic diagram;
Fig. 3 is the system architecture synoptic diagram of the technical solution used in the present invention;
Fig. 4 is the interface signal of bridge in the preferred embodiment and moves towards design;
Fig. 5 is in the technical solution used in the present invention, about the sampling controller partial detailed designs, and the annexation between sampling controller and the control interface;
Fig. 6 is the CMOS optical sensor that adopts HV7131R in the preferred embodiment, the flow process of adopting one 200 * 180 pixel monochrome image under red illumination.
Embodiment
Below in conjunction with accompanying drawing the present invention is further described.
With reference to Fig. 1～Fig. 6, a kind of CMOS optical sensor image sampling control system, comprise CMOS optical sensor 210, primary processor 230, data-carrier store 240 and internal bus 250, described CMOS optical sensor 210 connects internal bus 250, described internal bus 250 is connected with primary processor 230, described primary processor 230 is connected with data-carrier store 240, described sampled-data control system also comprises cmos image sampling controller 220, described cmos image sampling controller 220 comprises: code translator 221, be used to accept primary processor 260 via internal bus 240, the control information that bridge 230 is sent passes to sampling controller 222 and memory controller 225 after the decoding; Sampling controller 222 is used for control port 223 is enabled or the forbidden energy operation.Enable the back and send sampling parameter, sample pattern information, and accept the sampling execution state information of control port 223 feedbacks to control port 223; Control port 223 is used for sampling parameter, sample pattern information according to sampling controller 222, under the cooperation of the synchronizing signal that CMOS optical sensor 210 is exported, the view data of output is simultaneously sampled; Buffer 224 is used to accept the image sampling data that CMOS optical sensor 210 transmits via control port 223; Memory controller 225 comprises the data depth register 2251 of a size that is used for determining buffer 224 buffer zones and one and is used to determine whether the OIER 2252 that allows buffer to enter interrupt service routine and move the monoblock sampled data; Bridge 226 is used for setting up the bidirectional information passage between cmos image sampling controller 220 and internal bus 250;
Described CMOS optical sensor 210 is connected with described control port 223, described control port 223 is connected with buffer 224 with described sampling controller 222, described sampling controller 222 is connected with bridge 226 with code translator 221, described code translator 221 is connected with memory controller 225 with bridge 226, described memory controller 225 is connected with buffer 224, described buffer 224 is connected with bridge 226, and described bridge 226 is connected with internal bus 250.
Described sampling controller 222 comprises: sampling parameter module 2221, in order to deposit the reference position of sampled images, default sampling line number, current sampling line number, default sampling columns, current sampling columns, default sampling frame number, current sampling frame number; Sampling pattern module 2222 is used to determine to full row or interlacing pixel, still is full row or every the row pixel sampling; And in interlacing with under row sampling situation, selected is the odd number or the data of even number row and column pixel; Port status module 2223 is used for reflecting in real time the information from a relevant pixel sampling of control port 223 is finished, delegation's image sampling is finished and two field picture sampling is finished; Sampling enable module 2224 is used for pixel sampling, row sampling, three kinds of sampling patterns of frame sampling are enabled, and stipulates the level signal feature that above-mentioned three kinds of sampling patterns enable to begin and the level signal feature of end.
Described sampling pattern module 2222 adopts one 32 bit register to realize that the content of being controlled comprises: image sampling enables, data-moving request, row synchronizing signal are selected, line synchronizing signal is selected, row sampling pattern, row sampling pattern, partiting row sampling pattern, select every row sampling pattern and pixel clock PCLK significant level.
Described bridge 226 is an interface circuit, and the concrete regulation of described interface circuit is a table 1:
| Signal | Direction | Note |
| cisc_reset | Input | Controller resets |
| cisc_csn | Input | Controller enables |
| cisc_clock | Input | The synchronous logic clock |
| cisc_read | Input | Read gate |
| cisc_write | Input | Write gate |
| cisc_addr[2:0] | Input | Address bus |
| cisc_data[31:0] | I/O | Data bus |
| cisc_ready | Output | Bus is ready |
| cisc_int_req | Output | Interrupt request |
Table 1.
Described sampling parameter module 2221 comprises: address register, in order to deposit the reference position of sampled images; The row sample register is in order to deposit default sampling line number, current sampling line number; The row sample register is in order to deposit default sampling columns, current sampling columns; The frame sampling register is in order to deposit default sampling frame number, current sampling frame number.
Described sampling pattern module 2222 contains the controlling of sampling register.Described port status module 2223 contains status register.
Described sampling enable module 2224 comprises: enable register is used for pixel sampling, row sampling, three kinds of sampling patterns of frame sampling are enabled; Enable to begin register, in order to the level signal feature of stipulating that above-mentioned three kinds of sampling patterns enable to begin; Enable end register, in order to the level signal feature of stipulating that above-mentioned three kinds of sampling patterns enable to finish.
Fig. 1 is a synoptic diagram of gathering fingerprint image with the CMOS optical sensor.The optical lens group is made up of lens and prism.Lighting source sees through the prism in camera lens front, and the finger of restraining on another camera lens right side is illuminated.The concavo-convex of finger watch dermatoglyph road stayed fingerprint trace at lens plane, through lens focus, projects on the CMOS optical sensor, carries out opto-electronic conversion, A/D conversion, exports digitized fingerprint image.Fingerprint image only needs monochrome image, and 256 rank gray scales are enough.Lighting source adopts red.
Fig. 2 is a kind of CMOS optical sensor pel array distribution schematic diagram.R, G, B represent red, green, blue colour vegetarian refreshments respectively.As previously mentioned, get monochromatic fingerprint image under the red illumination light source, this moment, red pixel point was best to the responsiveness of light source, in pel array, only needed indicating the red pixel point sampling of R.The sampling pattern of Que Dinging is thus: interlacing is every row, and is odd-numbered line, even column.If the image that the CMOS optical sensor generates is 640 * 480 pixels, form the monochrome image of a pair 320 * 240 pixels with above-mentioned pattern sampling back.Both satisfied the fingerprint recognition needs, and also saved with software and rejected the time null resource that unnecessary pixel consumes.The interface signal of CMOS optical sensor sees Table 2:
| Signal | Direction | Description |
| VSYNC | Input | The frame synchronizing signal of cmos image sensor |
| HSYNC | Input | The line synchronizing signal of cmos image sensor |
| PCLK | Input | The picture element clock sync signal of cmos image sensor |
| PIXEL[9:0] | Input | 8/10 of the external data bus of cmos image sensor is optional |
Table 2
Fig. 3 is the system architecture synoptic diagram that the present invention adopts technical scheme.Its core is an image sampling controller 220, by bridge 226, hangs on the internal bus 250 and is connected with primary processor 230, so that the image sampling data are sent to data-carrier store 240.
222 pairs of control ports of sampling controller 223 carry out enable operation, and send sampling parameter, sample pattern information.In sampling process, accept the sampling execution state information of control port 223 feedbacks.
221 pairs of address signals from primary processor 230 of code translator are deciphered, and make each related register in the sampling controller 222 obtain separately data message from data bus.
Fig. 4 is a bridge 226 when image sampling controller 220 is articulated to internal bus, concrete interface signal and move towards design.See the refinement form of table 3 table 3 for details for table 1:
| Sigal | Direction | Description |
| cisc_csn | Input | The controller enable. controller enables |
| cisc_addr[2:0] | Input | Address bus. address bus |
| cisc_read | Input | Read strobe. read gate |
| cisc_write | Input | Write strobe. write gate |
| cisc_data[31:0] | Input | Data bus. data bus |
| cisc_reset | Input | The controller reset. controller resets |
| cisc_clock | Input | Sync logic clock. synchronous logic clock |
| cisc_ready | Output | Bus ready. bus is ready |
| cisc_int_req | Output | Interrupt request. interrupt request |
| cisc_dma_req | Output | DMA request.DMA request |
Table 3
Fig. 5 is in the technical solution used in the present invention, sampling controller 222 partial detailed designs, and and control interface between annexation.
The 401st, with the control bus of bridge 226, the control signal that sends to code translator 221 is that sheet selects cisc_csn and addressing signal cisc_addr[2:0].
The 402nd, Internal Control Bus IBC is to each register transfer addressing information.
403 is BDB Bi-directional Data Bus of one 32.
Three synchronizing signals that send to control port 223 from cmos sensor are: VSYNC frame synchronization, capable synchronously, the PCLK picture element clock synchronization of HSYNC.
Send to control port 223 images from cmos sensor, by one 8/10 optional external data bus PIXEL[9:0], link to each other with buffer 224.
Table 4 is total tabulations of all kinds of registers that comprised of sampling controller 222.Title, access mode, addressing side-play amount and the functional definition of each register have been stipulated in the table.
| ?Register | Access | Address Offset | Description |
| ?CISC_CTRL | RW | 0x00 | Control register |
| ?CISC_STAT | RO | 0x04 | Status register |
| ?CISC_INTE | RW | 0x08 | Enable register |
| ?CISC_E_STAR | RW | 0x0c | Enable to begin register |
| ?CISC_E_END | RW | 0x0e | Enable end register |
| CISC_ADDR_SET | RW | 0x10 | The sampling initial address register |
| CISC_ROW_CNT | RW | 0x14 | The default register of row pixel counts |
| CISC_COL_CNT | RW | 0x18 | The row pixel counts is preset register |
| CISC_FRAME_CNT | RW | 0x1c | The frame pixel counts is preset register |
| CISC_BUFFER_DATA | RW | 0x1e | Data cached depth register |
| CISC_BUFFER_INT | RW | 0x20 | The buffer memory interrupt register |
Table 4
Below be in a preferred embodiment to the specific definition of each register:
Control register CISC_CTRL specific definition, referring to table 5:
CISC_CTRL?Register
| Field | Bit | | Description |
| Enable | |||
| 0 | 0 | The image sampling enable bit, high effectively, when having adopted a two field picture automatic clear 0. | |
| Dma_req_en | 1 | 0 | The DMA request enables |
| Vsync_sel | 2 | 0 | The 0:VSYNC signal is a positive pulse; The 1:VSYNC signal is a negative pulse |
| Hsync_sel | 3 | 0 | 0:HSYNC signal high level is effective; 1:HSYNC signal low level is effective |
| Row_mode | 4 | 0 | 0: full row is adopted pattern; 1: pattern is adopted in interlacing |
| Col_mode | 5 | 0 | 0: full row are adopted pattern; 1: adopt pattern every row |
| Row_odd | 6 | 0 | When pattern is adopted in interlacing: 0: adopt even number line; 1: adopt odd-numbered line |
| Col_odd | 7 | 0 | When row are adopted pattern: 0: adopt even column; 1: adopt odd column |
| pclk_level | 8 | 0 | The PCLK significant level is selected: during the 0:PCLK low level, and data latching such as CISC_PIXEL register; During the 1:PCLK high level, data latching such as CISC_PIXEL register |
| Rev | 31:9 | Keep |
Table 5
Status register CISC_STAT specific definition, referring to table 6:
CISC_STAT?Register
| Field | Bit | | Description |
| image_done | |||
| 0 | 0 | One two field picture sampling complement mark | |
| row_done | 1 | 0 | Delegation's image sampling complement mark |
| pixel_done | 2 | 0 | A pixel sampling complement mark |
| Rev | 31:3 | Keep |
Table 6
Enable register CISC_INTE specific definition, referring to table 7:
CISC_INTE?Register
| Field | Bit | | Description |
| image_done_inten | |||
| 0 | 0 | Enabling image_done interrupts | |
| row_done_inten | 1 | 0 | Enabling row_done interrupts |
| pixel_done_inten | 2 | 0 | Enabling pixel_done interrupts |
| Rev | 31:3 | Keep |
Table 7
Enable to begin register CISC_E_START specific definition, referring to table 8:
CISC_E_START?Register
| Field | Bit | Value | Description |
| image_start_flag | 0:1 | 0 | Image interrupt |
| row_start_flag | 2:3 | 0 | Row interrupt |
| pixel_start_flag | 3:4 | 0 | Pixel interrupt |
Table 8
Enable end register CISC_E_END specific definition, referring to table 9:
CISC_E_END?Register
| Field | Bit | Value | Description |
| image_end_flag | 0:1 | 0 | Image interrupt |
| row_end_flag | 2:3 | 0 | Row interrupt |
| pixel_end_flag | 3:4 | 0 | Pixel interrupt |
Table 9
Address register CISC_ADDR_SET specific definition, referring to table 10:
CISC_ADDR_SET?Register
| Field | Bit | Value | ?Description |
| row_addr_start | 15:0 | 0 | The capable beginning of n gathered |
| col_addr_start | 31:16 | 0 | The n row begin to gather |
Table 10
Row sample register CISC_ROW_CNT specific definition, referring to table 11:
CISC_ROW_CNT?Register
| Field | Bit | Value | Description |
| row_num_set | 15:0 | 0 | Default sampling line number |
| row_num_cnt | 31:16 | 0 | Columns meter during the current line sampling |
| Number |
Table 11
Row sample register CISC_COL_CNT specific definition, referring to table 12:
CISC_COL_CNT?Register
| Field | Bit | Value | Description |
| col_num_set | 15:0 | 0 | Default sampling columns |
| col_num_cnt | 31:16 | 0 | Columns counting when sample in the prostatitis |
Table 12
Frame sampling register CISC_FRAME_CNT specific definition, referring to table 13:
CISC_COL_CNT?Register
| Field | Bit | Value | Description |
| fra_num_set | 15:0 | 0 | Default sampling frame number |
| fra_num_cnt | 31:16 | 0 | Present frame sampling time frame counting number |
Table 13
BUFFER data depth register CISC_BUFFER_DATA specific definition, referring to table 14:
CISC_BUFFER_DATA
| Field | Bit | Value | ? |
| CISC_BUFFER_ENABLE | |||
| 0 | 0 | 1=enables the BUFFER function, allows BUFFER to interrupt | |
| CISC_BUFFER_DATA | 1:31 | 0 | The degree of depth of BUFFER is set, and how many data that is to say has just can produce interruption in the BUFFER |
Table 14
BUFFER interrupt register CISC_BUFFER_INT specific definition, referring to table 15:
CISC_BUFFER_INT
| Field | Bit | | Description |
| CISC_BUFFER_ISR | |||
| 0 | 0 | Producing BUFFER interrupts |
Table 15
Fig. 6 is in a preferred embodiment, adopts the CMOS optical sensor of HV7131R, the flow process of advancing to adopt one 200 * 180 pixel monochrome image under red illumination.
Step 601 is established the sampling reference position: the 150th row, the 120th row; If sampling ranks frame number: 200 row, 180 row, 5 frames;
Step 602 is selected three primary colors: R; Select sampling pattern: interlacing is sampled every row, and selects odd-numbered line, even column;
| Register | Description |
| CISC_CTRL | Control register |
| CISC_ADDR_SET | The sampling initial address register |
| CISC_ROW_CNT | The default register of row pixel counts |
| CISC_COL_CNT | The row pixel counts is preset register |
| CISC_FRAME_CNT | The frame pixel counts is preset register |
| CISC_BUFFER_DATA | Data cached depth register |
Step 606 if detect the buffer interrupt request, is then called interrupt service routine;
Step 607 is moved data-carrier store with sampled data from buffer;
Step 608 stops sampling;
So far, this flow process has guaranteed the CMOS optical sensor of HV7131R, advances to collect the flow process of one 200 * 180 pixel monochrome image under red illumination.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention.Within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Embodiment 2
With reference to Fig. 1-Fig. 6, a kind of CMOS optical sensor image sampling control method, this method comprises the steps:
1) reference position of default sampled images, sampling line number, sampling columns, sampling frame number, and these parameters are stored in the related register of sampling parameter 2221;
2) determine the requirement of sampled images tone, promptly make a kind of selection: 1 full color in following three kinds of alternativess; Any in the 2RGB three primary colors; In the 3RGB three primary colors any two kinds;
3), find out the corresponding pass that this tone and CMOS optical sensor pixel distribute according to the tone that described selection determined; Be converted into full row be listed as sampling entirely, with the multiple sampling pattern of the initial interlacing of odd or even row or column every the row sampling, and described sampling pattern parameter is stored in the related register of sampling pattern 2222;
4) size of decision buffer 224 buffer zones is stored in it in data depth register 2251 of memory controller 225;
5) control port 223 is enabled;
6) make control port 223,, in the presence of the synchronizing signal that CMOS optical sensor 210 is exported, the view data of CMOS optical sensor 210 outputs is sampled according to the parameter that sampling parameter 2221, sampling pattern 2222 provide;
7) control port 223 is in sampling process, and the situation of will sampling is in real time write in people's port state register 2223 with code form, and described sampling situation comprises: pixel sampling is finished, delegation's image sampling is finished and two field picture sampling is finished;
8) under primary processor 230 control, buffer 224 is accepted image sampling data that CMOS optical sensor 210 transmits via control port 223 as buffering, then with the monoblock data by bridge 226, via internal bus 250, be sent to data-carrier store 240.
Claims (9)
1. CMOS optical sensor image sampling control system, comprise CMOS optical sensor (210), primary processor (230), data-carrier store (240) and internal bus (250), described CMOS optical sensor (210) connects internal bus (250), described internal bus (250) is connected with primary processor (230), described primary processor (230) is connected with data-carrier store (240), it is characterized in that: described sampled-data control system also comprises cmos image sampling controller (220), and described cmos image sampling controller (220) comprising:
Code translator (221) is used to accept the control information that primary processor (230) is sent via internal bus (250), bridge (230), passes to sampling controller (222) and memory controller (225) after the decoding;
Sampling controller (222) is used for control port (223) is enabled or the forbidden energy operation, enables the back and sends sampling parameter, sample pattern information to control port (223), and accept the sampling execution state information of control port (223) feedback;
Control port (223) is used for sampling parameter, sample pattern information according to sampling controller (222), under the cooperation of the synchronizing signal that CMOS optical sensor (210) is exported, the view data of output is simultaneously sampled;
Buffer (224) is used to accept the image sampling data that CMOS optical sensor (210) transmits via control port (223);
Memory controller (225) comprises the data depth register (2251) of a size that is used for determining buffer (224) buffer zone and one and is used to the OIER (2252) that determines whether to allow buffer to enter interrupt service routine and move the monoblock sampled data;
Bridge (226) is used for setting up the bidirectional information passage between cmos image sampling controller (220) and internal bus (250);
Described CMOS optical sensor (210) is connected with described control port (223), described control port (223) is connected with buffer (224) with described sampling controller (222), described sampling controller (222) is connected with bridge (226) with code translator (221), described code translator (221) is connected with memory controller (225) with bridge (226), described memory controller (225) is connected with buffer (224), described buffer (224) is connected with bridge (226), and described bridge (226) is connected with internal bus (250).
2. a kind of CMOS optical sensor image sampling control system as claimed in claim 1, it is characterized in that: described sampling controller (222) comprising:
Sampling parameter module (2221) is in order to deposit the reference position of sampled images, default sampling line number, current sampling line number, default sampling columns, current sampling columns, default sampling frame number, current sampling frame number;
Sampling pattern module (2222) is used to determine to full row or interlacing pixel, still is full row or every the pixel sampling of row; And in interlacing or under row sampling situation, selected is the odd number or the data of even number row and column pixel;
Port status module (2223) is used for reflecting in real time the information from a relevant pixel sampling of control port (223) is finished, delegation's image sampling is finished and two field picture sampling is finished;
Sampling enable module (2224) is used for pixel sampling, row sampling, three kinds of sampling patterns of frame sampling are enabled, and stipulates the level signal feature that above-mentioned three kinds of sampling patterns enable to begin and the level signal feature of end.
3. a kind of CMOS optical sensor image sampling control system as claimed in claim 2, it is characterized in that: described sampling pattern module (2222) adopts one 32 bit register to realize that the content of being controlled comprises: image sampling enables, data-moving request, row synchronizing signal are selected, line synchronizing signal is selected, row sampling pattern, row sampling pattern, partiting row sampling pattern, select every row sampling pattern and pixel clock PCLK significant level.
4. as the described a kind of CMOS optical sensor image sampling control system of one of claim 1-3, it is characterized in that: described bridge (226) is an interface circuit, and the concrete regulation of described interface circuit is a table 1:
Table 1.
5. a kind of CMOS optical sensor image sampling control system as claimed in claim 2, it is characterized in that: described sampling parameter module (2221) comprising:
Address register is in order to deposit the reference position of sampled images;
The row sample register is in order to deposit default sampling line number, current sampling line number;
The row sample register is in order to deposit default sampling columns, current sampling columns;
The frame sampling register is in order to deposit default sampling frame number, current sampling frame number.
6. a kind of CMOS optical sensor image sampling control system as claimed in claim 2, it is characterized in that: described sampling pattern module (2222) contains the controlling of sampling register.
7. a kind of CMOS optical sensor image sampling control system as claimed in claim 2, it is characterized in that: described port status module (2223) contains status register.
8. a kind of CMOS optical sensor image sampling control system as claimed in claim 2 is characterized in that:
Described sampling enable module (2224) comprising:
Enable register is used for pixel sampling, row sampling, three kinds of sampling patterns of frame sampling are enabled;
Enable to begin register, in order to the level signal feature of stipulating that above-mentioned three kinds of sampling patterns enable to begin;
Enable end register, in order to the level signal feature of stipulating that above-mentioned three kinds of sampling patterns enable to finish.
9. method that realizes with CMOS optical sensor image sampling control system as claimed in claim 1, this method comprises the steps:
1) reference position of default sampled images, sampling line number, sampling columns, sampling frame number, and these parameters are stored in the related register of sampling parameter (2221);
2) determine the requirement of sampled images tone, promptly make a kind of selection: 1) full color in following three kinds of alternativess; 2) any in the RGB three primary colors; 3) in the RGB three primary colors any two kinds;
3), find out the corresponding relation that this tone and CMOS optical sensor pixel distribute according to the tone that described selection determined; Be converted into full row be listed as sampling entirely, with the multiple sampling pattern of the initial interlacing of odd or even row or column every the row sampling, and described sampling pattern parameter is stored in the related register of sampling pattern (2222);
4) size of decision buffer (224) buffer zone is stored in it in data depth register (2251) of memory controller (225);
5) control port (223) is enabled;
6) make control port (223),, in the presence of the synchronizing signal that CMOS optical sensor (210) is exported, the view data of CMOS optical sensor (210) output is sampled according to the parameter that sampling parameter (2221), sampling pattern (2222) provide;
7) control port (223) is in sampling process, and the situation of will sampling in real time writes in the port state register (2223) with code form, and described sampling situation comprises: pixel sampling is finished, delegation's image sampling is finished and two field picture sampling is finished;
8) under primary processor (230) control, buffer (224) is accepted image sampling data that CMOS optical sensor (210) transmits via control port (223) as buffering, then with the monoblock data by bridge (226), via internal bus (250), be sent to data-carrier store (240).
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Assignee: HANGZHOU ZHIAN TECHNOLOGY CO., LTD. Assignor: Hangzhou Shengyuan Chip Technique Co., Ltd. Contract record no.: 2011330001487 Denomination of invention: Image sampling control system and method for CMOS optical sensor Granted publication date: 20110105 License type: Exclusive License Open date: 20090325 Record date: 20111231 |
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