CN101383560A - DC voltage converter - Google Patents
DC voltage converter Download PDFInfo
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- CN101383560A CN101383560A CNA2007101497613A CN200710149761A CN101383560A CN 101383560 A CN101383560 A CN 101383560A CN A2007101497613 A CNA2007101497613 A CN A2007101497613A CN 200710149761 A CN200710149761 A CN 200710149761A CN 101383560 A CN101383560 A CN 101383560A
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Abstract
A DC voltage converting device comprises a load inspecting device, a size changeable power transistor group, and a power transistor size control device and drive device. The load inspecting device is used for inspecting the size of load current. The size changeable power transistor group is provided with a plurality of PMOS which are connected in parallel and a plurality of NMOS which are connected in parallel. The power transistor size control device and drive device is coupled between the load inspecting device and the size changeable transistor group so as to control the conduction status of the plurality of PMOS and the plurality of NMOS. As the load current changes, the size changeable power transistor group can adjust the potential of one converting voltage output end by different general sizes.
Description
Technical field
The present invention is relevant for a kind of dc voltage changer (DC-DC converter).
Background technology
Fig. 1 is a kind of execution mode of traditional dc voltage changer, and in order to change a raw DC voltage source VDD, the direct voltage after the conversion is exported by a changing voltage output end vo ut.This tradition dc voltage changer comprise an inductance L, a pulse generator 102 (Pulse Width Modulation, PWM), a power transistor enables signal generator 104, a power transistor group 110 (Power MOS), the drive circuit 106 (driver) that uses for the P-type mos transistor Mp (PMOS) of this power transistor group 110 and for the drive circuit 108 of N type metal oxide semiconductor transistor Mn (NMOS) use of this power transistor group 110.
The voltage Vout of this changing voltage output will import this pulse generator 102, to produce a pulse Vswitch after resistance R 1 and R2 dividing potential drop.This power transistor enable signal generator 104 comprise one dead time controller 112 (Dead-time Controller, DTC) and a Zero voltage switching circuit 114 (Zero Current Detector, ZCD).Controller 112 will be exported a P-type mos transistor and enable signal SW_P dead time this.This Zero voltage switching circuit 114 will be exported a N type metal oxide semiconductor transistor and enable signal SW_N.When this PMOS enabled signal SW_P for its initiate mode (low level), this PMOS of these drive circuit 106 military orders enabled the current potential that signal SW_P approaches earth terminal, with this PMOS Mp of conducting.When this NMOS enables signal SW_N for its initiate mode (high level), this NMOS of these drive circuit 108 military orders enables the current potential that signal SW_N approaches this raw DC voltage source VDD, with this NMOS Mn of conducting, voltage Vout thereby be maintained in a stability range.
Yet, the many specifications that manufacturer was provided with its load unit of the design of tradition dc voltage changer are benchmark, the power that is passed out is a default value, and this default value is the maximum consumption of power of this load unit, and this load unit of military order all is able to operate as normal in any case.But, when this load unit be processor, random access memory, display ... wait when using, the load unit overwhelming majority's time all is in holding state (low load), and its power demand is far below described default value.Make the power transfer usefulness extreme difference of traditional dc voltage changer in low loading range.
Summary of the invention
Example of the present invention provides a kind of dc voltage changer, comprising a load sensor (loadsensor), a variable-sized power transistor group and a power transistor size control and driver (width controller and driver).This load sensor is responsible for detecting the size of the load current of this dc voltage changer.This variable-sized power transistor group has a plurality of P-type mos transistors (PMOS) that are connected in parallel to each other and a plurality of N type metal oxide semiconductor transistors (NMOS) that are connected in parallel to each other.This power transistor size control and driver are coupled between this load sensor and this variable-sized power transistor group, are responsible for controlling according to this load current the conduction status of these a plurality of PMOS and these a plurality of NMOS.Along with the change of this load current, this variable-sized power transistor group will be adjusted the current potential of a changing voltage output of this dc voltage changer with different overall sizes.
Example of the present invention more provides a kind of dc voltage changer, enables a signal generator and a power transistor group comprising a load sensor, a dither jump modulation controller, a pulse generator, a NAND door, a power transistor.This load sensor is responsible for detecting the size of the load current of this dc voltage changer.This dither jump modulation controller will determine the dither modulation control interval that jumps according to the size of this load current, and wherein, this load current little then this dither modulation control interval that jumps of healing is longer.This dither jump modulation controller is more cut apart this dither with dither jump modulation unit and is jumped modulation control interval to export a dither jump modulation signal, wherein, it is low level that this dither jump modulation signal is modulated nidus in the dither jump of each dither jump modulation unit of this dither jump modulation control interval, according to the voltage of a changing voltage output of this dc voltage changer, this pulse generator produces a pulse.The input signal of this NAND door is inversion signal and this dither jump modulation signal of this pulse.According to the output signal of this NAND door, this power transistor is enabled signal generator and is produced that a P-type mos transistor (PMOS) is enabled signal and a N type metal oxide semiconductor transistor (NMOS) is enabled signal.This PMOS enables signal and this NMOS enables this power transistor group of signal controlling, to adjust the voltage of this changing voltage output.
For described and other purpose of the present invention, feature and advantage can be become apparent, cited below particularlyly go out several embodiment, and conjunction with figs. describes in detail.
Description of drawings
Fig. 1 is a kind of execution mode of traditional dc voltage changer;
Fig. 2 is a kind of execution mode of dc voltage changer of the present invention;
Fig. 3 is a kind of execution mode of power transistor size control of the present invention and driver;
Fig. 4 is a kind of execution mode of load sensor of the present invention;
Fig. 5 is the detailed circuit diagram of a kind of execution mode of the counting-type analog-to-digital converter of load sensor of the present invention;
Fig. 6 illustrates the size of how being judged this load current by the output of load current detection circuit of the present invention;
Fig. 7 detects a kind of execution mode of voltage generator for the present invention;
Fig. 8 is the another kind of execution mode of dc voltage changer of the present invention;
Fig. 9 is for adopting a direct current electric pressure converter embodiment of DSM control;
Figure 10 illustrates the various signals that the DSM control technology is produced;
Figure 11 is a kind of execution mode of this load sensor;
Figure 12 illustrates the relation of this dither jump modulation control interval and signal tN and reference signal Vmode;
Figure 13 is a kind of execution mode of dither jump modulation controller of the present invention;
Figure 14 jumps with dither and modulates the coherent signal waveform of control;
Figure 15 modulates the execution mode of the dc voltage changer of controlling for adopting this dither to jump.
The primary clustering symbol description
The 102-pulse generator;
The 104-power transistor is enabled signal generator;
106, the 108-drive circuit;
The 110-power transistor;
112-controller dead time;
The 114-Zero voltage switching circuit;
The 202-load sensor;
The variable-sized power transistor group of 204-;
206-power transistor group size control and driver;
The 208-pulse generator;
The 210-power transistor is enabled signal generator;
302-power transistor group size control and driver;
304-first control unit;
306-second control unit;
The 308-logical circuit;
The 310-drive circuit;
The 312-logical circuit;
The 314-drive circuit;
402-detects voltage generating circuit;
The 404-sample-and-hold circuit;
The 406-current/charge-voltage convertor;
408-current drives serial connection inverter delay circuit;
The 410-D D-flip flop;
The 502-sample-and-hold circuit;
The 504-current/charge-voltage convertor;
506-current drives serial connection inverter delay circuit;
508-delay cell;
Between 602-load current detection zone;
The 604-sampling range;
It is interval that 606-keeps;
The PMOS part of the variable-sized power transistor group of 702-;
The NMOS part of the variable-sized power transistor group of 704-;
706-detects with P-type mos transistor group;
The 802-pulse generator;
The 804-power transistor is enabled signal generator;
806,808-power transistor group size control and driver;
The 810-counting-type analog-to-digital converter;
The 812-current detection circuit;
The 902-load sensor;
904-dither jump modulation controller;
The 906-pulse generator;
The 908-NAND door;
The 910-power transistor is enabled signal generator;
912-dither jump modulation signal;
A switching cycle of 1002-pulse;
The 1102-sample-and-hold circuit;
The 1104-current/charge-voltage convertor;
1106-current drives serial connection inverter delay circuit;
1202 with dither that 1204-indicates corresponding large load current and the little load current modulation control interval that jumps;
The 1206-dither jumps and modulates the control interval place;
The 1302-1306-multiplexer;
The 1308-dither jumps and modulates the control input end;
1402-indicates dither jump modulation control interval;
Dither jump modulation signal when 1404-dither jump modulation control input end is " 0 ";
The PMOS of the corresponding dither jump of 1406-modulation signal 1404 enables signal SW_P;
Dither jump modulation signal when 1408-dither jump modulation control input end is " 1 ";
The PMOS of the corresponding dither jump of 1410-modulation signal 1408 enables signal SW_P;
1412, the 1414-dither jumps and modulates nidus;
The 1502-pulse generator;
The 1504-power transistor is enabled signal generator;
1506 with 1508-form this load sensor 902;
1510-dither jump modulation controller;
The switch controlling signal of CLKsam-sample-and-hold circuit;
(D1, D2 ..., DN)-thermometer-code;
The drive current of I-delay cell;
The IL-inductive current;
Isense-detects electric current;
The L-inductance;
Mn-NMOS；
Mn1-MnN-small size NMOS;
Mp-PMOS；
Mp1-MpN-small size PMOS;
Rsense-detects resistance;
SW_N-NMOS enables signal;
The Continuity signal of SW_Ni (i=1-N)-each small size NMOS;
The Continuity signal of SW_Pi (i=1-N)-each small size PMOS;
SW_P-PMOS enables signal;
The output of t1-tN-delay cell;
During the tN1-large load current, the output of last delay cell;
During the little load current of tN2-, the output of last delay cell;
The Td-passing time is poor;
Tx-indicates extraction time;
VDD-raw DC voltage source;
Vmode-extracts signal;
Vout-changing voltage output;
The inversion signal of the pulse that the VQ-pulse generator produces;
The signal that Vreset-delay cell is transmitted;
Vsense-detects voltage;
The Vx-first node.
Embodiment
Fig. 2 is a kind of execution mode of dc voltage changer of the present invention, comprising an inductance L, a load sensor 202, one variable-sized power transistor group 204 and a power transistor size control and driver 206.Compare with the conventional power transistors group 110 of Fig. 1, variable-sized power transistor group 204 of the present invention replaces the large scale PMOS (Mp) of Fig. 1 respectively with large scale NMOS (Mn) with a plurality of small size PMOS (Mp1-MpN) that are connected in parallel to each other and a plurality of small size NMOS (Mn1-MnN) that are connected in parallel to each other.These a plurality of small size PMOS (Mp1-MpN) will provide the path to be coupled to a raw DC voltage source VDD for a changing voltage output end vo ut of this dc voltage changer through this inductance L, and these a plurality of small size NMOS (Mn1-MnN) will provide the path to be coupled to an earth terminal for this changing voltage output end vo ut through this inductance L.Yet, compared to Figure 1, traditional dc voltage changer of Fig. 1 all uses the power transistor group 110 of fixed dimension at all loading ranges, and the present invention then can make a PMOS overall size of this variable-sized power transistor group 204 and the load current that a NMOS overall size is proportional to this dc voltage changer by the conducting state of controlling these a plurality of small-geometry transistors.Wherein, this load sensor 202 is responsible for detecting the size of this load current.The conduction status of these a plurality of small size PMOS (Mp1-MpN) and small size NMOS (Mn1-MnN) is then by the power transistor size control and driver 206 controls that are coupled between this load sensor 202 and this variable-sized power transistor group 204.
Observe traditional dc voltage changer shown in Figure 1, find because employed power transistor group 110 is a large scale, so employed drive circuit 106 and 108 also must be a large scale.When large load current, the power consumption of this tradition dc voltage changer mainly comes from the conduction loss (conduction loss) of this large scale power transistor group 110.When little load current, power consumption mainly comes from the handoff loss (switching loss) of this large scale power transistor group 110 and described large scale drive circuit 106 and 108.The preferable power usefulness yet the size of embodiments of the invention dc voltage changer-this variable-sized power transistor group 204 as shown in Figure 2 is directly proportional with this load current-will has.When large load current, adopt the large scale power transistor group, the equivalent resistance that makes power transistor group is diminished and reduce the conduction loss of power transistor group.When little load current, adopt the small size drive circuit to drive the small size power transistor group, can reduce the handoff loss of power transistor group and drive circuit in the lump.
See the execution mode of Fig. 2 for details, a kind of execution mode of this variable-sized power transistor group 204 is as follows.The source electrode of these a plurality of PMOS (Mp1-MpN) and drain electrode are respectively coupled to this a raw DC voltage source VDD and a first node Vx.The drain electrode of these a plurality of NMOS (Mn1-MnN) and source electrode are respectively coupled to this first node Vx and this earth terminal.Wherein this first node Vx couples this changing voltage output end vo ut through this inductance L.
Consult Fig. 2, pulse generator 208 is that generation one PMOS enables signal SW_P and a NMOS enables signal SW_N with the purpose that power transistor is enabled signal generator 210.Other can produce this PMOS and enable circuit that signal SW_P and this NMOS enable signal SW_P and also can be used to replace this pulse generator 208 and enable signal generator 210 with this power transistor.
In addition, a plurality of digital signals that the load sensor that execution mode adopted 202 shown in Figure 2 is exported (D1, D2 ..., be thermometer-code (thermometer code) DN), in order to indicate the size of this load current.These a plurality of digital signals (D1, D2 ..., DN) in the more signal be high level, then represent this load current bigger.These a plurality of digital signals (D1, D2 ..., DN) with these a plurality of PMOS (Mp1-MpN) and this a plurality of NMOS (Mn1-MnN) in correspondence with each other.Fig. 3 is a kind of execution mode of this power transistor size control and driver 206, and wherein this variable-sized power transistor group power of hypothesis comprises seven groups of undersized conventional power transistors groups (N=7).Fig. 3 illustrates PMOS and NMOS in these seven groups of small size conventional power transistors groups with Mp1-Mp7 and Mn1-Mn7.As shown in Figure 3, a power transistor size control and driver 302 comprise a plurality of first control units 304 and a plurality of second control units 306.With first control unit 304 shown in scheming is example, this first control unit 304 corresponding described PMOS (Mp1) and a described digital signal (Dj).When a PMOS enables signal SW_P for its initiate mode (low level), this first control unit 304 will determine the conducting state of pairing PMOS (Mp1) according to pairing digital signal (Dj).With second control unit 306 shown in scheming is example, this second control unit 306 corresponding described NMOS (Mn1) and a described digital signal (Dj).When a NMOS enables signal SW_P for its initiate mode (high level), this second control unit 306 will determine the conducting state of pairing NMOS (Mn1) according to pairing digital signal (Dj).
In execution mode shown in Figure 3, this first control unit 304 comprises a logical circuit 308 and one drive circuit 310.This logical circuit 308 is enabled signal SW_P in this PMOS and is exported a low level signal for its initiate mode (low level) and pairing digital signal (Dj) during for high level.This this low level signal of drive circuit 310 military orders approaches the current potential of this earth terminal with the pairing PMOS of conducting (Mp1).This second control unit 306 comprises a logical circuit 312 and one drive circuit 314 separately.This logical circuit is enabled signal SW_N in this NMOS and is exported a high level signal for its initiate mode (high level) and pairing digital signal (Dj) during for high level.This this high level signal of drive circuit 314 military orders approaches the current potential of this raw DC voltage source VDD with the pairing NMOS of conducting (Mn1).
Fig. 4 is a kind of execution mode of this load sensor 202, detects voltage generating circuit 402, a sample-and-hold circuit 404, a current/charge-voltage convertor 406, current drives serial connection inverter delay circuit 408 and a plurality of D flip-flop 410 comprising one.This detection voltage generating circuit 402 dwindles into a detection electric current with the electric current of this inductance L with a ratio, and makes this detection electric current flow through a detection resistance to produce a detection voltage Vsense.This sample-and-hold circuit 404 this detection voltage Vsense that will take a sample.The detection voltage Vsense of sampling becomes a drive current I after these current/charge-voltage convertor 406 conversions, its value is directly proportional with this detection voltage Vsense.As shown in the figure, this current drives serial connection inverter delay circuit 408 comprises a plurality of delay cells of serial connection, is used for transmitting a high level signal.These a plurality of delay cells comprise a plurality of inverters of serial connection separately.As execution mode among the figure, a delay cell is made up of two serial connection inverters.These a plurality of inverters are driven by this drive current I respectively.Because the propagation velocity of this high level signal in these a plurality of delay cells is directly proportional with this drive current I, therefore, present embodiment will be extracted the output end signal (t1-tN) of these a plurality of delay cells with these a plurality of D flip-flops 410, and judge the size of this drive current I with extracted digital signal (D1-DN), and then the relation of utilizing this drive current I to be directly proportional with load current, judge the size of this load current.Wherein, these a plurality of D flip-flop 410 unifications are extracted signal Vmode triggering by one.The circuit that this sample-and-hold circuit 404, this current/charge-voltage convertor 406, this current drives serial connection inverter delay circuit 408 and these a plurality of D flip-flops 410 are formed is a kind of simple numerical formula analog to digital converter, and this circuit will replace the huge analog converter circuit of tradition.
Fig. 5 is a kind of detailed circuit diagram of execution mode of the counting-type analog-to-digital converter 412 of this load sensor.Circuit 502,504, with 506 respectively to should sample-and-hold circuit 404, this current/charge-voltage convertor 406, be connected in series inverter delay circuit 408 with this current drives.Fig. 6 is example (N=5) with the variable-sized power transistor group that is divided into five small size power transistor group, and the size of how being judged this load current by the output of load current detection circuit is described.Wherein, 602 comprise that a sampling range 604 and keeps interval 606 between the load current detection zone.After entering this maintenance interval 606, the switch S 1 of this sample-and-hold circuit 502 is with not conducting.The detection voltage Vsense that is sampled to will convert drive current to by this current/charge-voltage convertor 504 and drive inverter in this current drives serial connection inverter delay circuit 506.As shown in Figure 6, the signal Vreset that imports in first delay cell 508 will switch to high level by low level after entering this maintenance interval 606.This high level signal will be passed to follow-up delay cell in regular turn.The output end signal of each delay cell is represented by t1-t5.The present invention extracts signal Vmode with one and extracts the output end signal t1-t5 of each delay cell in a set time (entering Tx place, interval 606 back of this maintenance).Because this high level signal is directly proportional with described drive current and this drive current is directly proportional with load current in the propagation velocity of these a plurality of delay cells, therefore, this load current is bigger, then the passing time difference Td between each delay cell is shorter, and it is high level that signal the more will be arranged in the digital signal of being extracted (D1-D5).As the example of Fig. 6, the digital signal of being extracted (D1 ..., D5) will be (1,1,1,0,0).(D1 ..., D5) coding formed is called thermometer-code (thermometer code).In this execution mode, each position by chance represents an equivalent load current poor for high level.Some execution mode comprises that also a thermometer-code changes bed to binary converter (thermometer code-binary codeconverter), in order to will (D1 ..., D5) transcoding is binary digital signal.At this moment, need this power transistor size control is done relative modification with driver 206.
In addition because the easy temperature influence of signal transmission speed of delay cell, the present invention more propose a kind of current/charge-voltage convertor with compensate this temperature become because of.Wherein a kind of execution mode is shown in the circuit blocks 504 of Fig. 5.This execution mode is the symmetric design of M3 based on transistor M1.When temperature changed, transistor M1 was that the source grid potential missionary society of M3 changes thereupon, causes node voltage VA and VB to change.VA is that the electric current that M4 produced can carry out reducing mutually at transistor M7 with VB in transistor M2, makes temperature become because of being compensated.Therefore, the drive current that this current/charge-voltage convertor 504 is exported can't temperature influence, so the circuit 506 that it drove also can temperature influence.
Fig. 7 detects a kind of execution mode of voltage generator 402 for this.Circuit 702 and 704 is respectively these a plurality of PMOS and these a plurality of NMOS of this variable-sized power transistor group among the figure.As shown in the figure, this detection voltage generating circuit comprises that one detects with P-type mos transistor group 706, will form a current mirror circuit with these a plurality of PMOS (circuit 702) and dwindle the electric current I L of this inductance L with certain proportion K.Electric current after dwindling is a detection electric current I sense.This detection electric current I sense will flow through a detection resistance R sense to produce a detection voltage Vsense.Because the actual overall size of PMOS of circuit 702 can change along with load current, so this detection also can be kept this certainty ratio K along with load current changes with P-type mos transistor group 706.In this execution mode, this detection replaces the big detection PMOS of conventional fixed size with PMOS with a plurality of small sizes detections of parallel connection with P-type mos transistor group.These a plurality of small sizes detect with the ratio of PMOS ratio each other with reference to each PMOS in the circuit 702, and the digital signal (this example is Dj-Dj+6) that these a plurality of detections are also exported by this load sensor with the conducting state of PMOS determines.
The present invention more proposes a kind of design of variable-sized power transistor group 204, and traditional large scale power transistor group is divided into 7 groups of small size power transistor group (N=7).In this design, Mp1:Mp2:Mp3:Mp4:Mp5:Mp6:Mp7=Mn1:Mn2:Mn3:Mn4:Mn5:Mn6:Mn7=1:1:2:2:2:2:2.Therefore, along with the difference of load current, a PMOS overall size of this variable-sized power transistor group and the variation of a NMOS overall size comprise: x1, x2, x4, x6, x8, x10, with seven kinds of x12.In other embodiments, can also more parts of small size power transistor group replace large scale power transistor group originally.The N value is bigger, and then the change in size of this variable-sized power transistor group is finer and smoother, and overall power usefulness is higher.
Fig. 8 is the another kind of execution mode of dc voltage changer of the present invention, and the circuit 102 and 104 that pulse generator 802 and the power transistor that is wherein adopted enabled signal generator 804 and Fig. 1 is identical.The power transistor size control of circuit 806 and 808 composition diagrams 3 and driver 302.Circuit 810 is the counting-type analog-to-digital converter in the load sensor 202.The detection voltage generating circuit that present embodiment realizes in the load sensor 202 with the current detection circuit in the pulse generator 802 812.
In addition, the present invention more proposes a direct current electric pressure converter, reduces unnecessary power loss by interdicting unnecessary power transistor group switching signal equably.Represent with dither jump modulation blocking control (Dithering Skip Modulation Control, DSM control) at this.
Fig. 9 enables a signal generator 910 and a power transistor group (Mp and Mn form) for adopting a direct current electric pressure converter embodiment of DSM control comprising an inductance L, a load sensor 902, a dither jump modulation controller 904, a pulse generator 906, a NAND door 908, a power transistor.This load sensor 902 is responsible for the size of the load current of this dc voltage changer of detection.This dither jump modulation controller 904 will determine a dither to jump according to the size of this load current and modulate control interval, and cut apart this dither jump modulation control interval to export a dither jump modulation signal 912 with dither jump modulation unit.Wherein, this load current is littler, and then the length of this dither jump modulation control interval is longer.This dither jump modulation signal 912 dither jump modulation nidus of each dither jump modulation unit in this dither jumps the modulation control interval is a low level.This pulse generator 906 will produce a pulse VQB according to the voltage Vout of a changing voltage output of this dc voltage changer.In Fig. 1 tradition dc voltage changer, this pulse label is Vswitch, is used for importing this power transistor and enables signal generator 104 and produce that these PMOS enable signal SW_P and this NMOS enables signal SW_N.Compared to Figure 1, in Fig. 9, this pulse (label VQB) is used for importing the jump length of modulation control interval of these dither jump modulation control circuit 904 these dithers of counting and is divided into jump modulation units and produce described dither jump modulation signal 912 according to this of a plurality of dithers with modulation control interval that this dither is jumped.The inversion signal VQ of this pulse as shown in the figure, (label VQB) and this dither jump modulation signal 912 will couple the input of this NAND door 908.The output signal of this NAND door 908 will be used for importing this power transistor and enable signal generator 910 to produce this PMOS and enable signal SW_P and this NMOS enables signal SW_N.This power transistor group (Mp and Mn form) will be enabled signal SW_P and this NMOS according to this PMOS and be enabled signal SW_N and make this changing voltage output end vo ut be coupled to a raw DC voltage source VDD or an earth terminal through this inductance L.Wherein, this pulse generator 906 and this power transistor are enabled signal generator 910 and can be adopted with the pulse generator 102 of Fig. 1 and this power transistor and enable the identical design of signal generator 104, or any circuit that same purpose is arranged.
Figure 10 illustrates the various signals that this DSM control technology is produced.The pulse that waveform VQB is produced for this pulse generator 906.Suppose that the length of a dither jump modulation unit equals three switching cycles (a switching cycle such as label 1002) of waveform VQB, and the dither of dither jump modulating unit jump modulation nidus is last switching cycle in three switching cycles.As shown in the figure, this dither modulation control interval that jumps by chance can be divided into three dither jump modulating units, and the corresponding dither jump modulation signal 912 that produces of institute will indicate three dithers with low level and jump and modulate nidus.After this dither jump modulation signal 912 is imported this NAND door 908 with the inversion signal of this pulse VQB, this power transistor of Vswitch signal military order that is produced is enabled signal generator 910 outputs PMOS shown in Figure 10 and is enabled signal SW_P, wherein has three place's initiate modes (low level) to be interdicted.In blocking place, PMOS (Mp) will not be switched on, and can reduce unnecessary handoff loss.
Figure 11 is a kind of execution mode of this load sensor 902.This figure omits one of this load sensor 902 and detects voltage generating circuit.Show that part in the drawings comprises a sample-and-hold circuit 1102, a current/charge-voltage convertor 1104 and current drives serial connection inverter delay circuit 1106.Figure 11 and Fig. 5 difference are that this load sensor 902 does not need D flip-flop, directly with the output (as tN) of a certain specific delays unit as output signal.This dither jump modulation controller 904 will be judged this dither jump modulation control interval according to a signal tN and a reference signal Vmode.
Figure 12 illustrates the relation of this dither jump modulation control interval and signal tN and reference signal Vmode.This reference signal Vmode is a fixed signal, will be fixed on to be high level in a certain section.With reference to Figure 11, the signal rising point of signal tN is relevant with the size of load current as can be known, and load current is bigger, and then signal tN can be healed and early risen to high level; Load current is littler, and then signal tN can be healed and risen to high level evening.Figure 12 will be relatively under a large load current and a little load current, and signal tN and dither jump and modulate the relation of control interval.Under the situation of large load current, signal tN is denoted as tN1.Under the situation of little large load current, signal tN is denoted as tN2.Not rise to the section of high level yet be the dither modulation control interval that jumps because this this reference signal of dither jump modulation controller 904 military orders Vmode is high level but this signal tN, so the deciphering of Figure 12 is as follows.Because the residing load current of signal tN1 is bigger, signal tN1 rises to high level very early, therefore this dither jump modulation controller 904 is judged does not have dither jump modulation control interval to have (beacon signal 1202 of dither jump modulation control interval remains on low level), show that load current is quite big, need not carry out dither jump modulation control.In addition, because the residing load current of signal tN2 is less, the later high level that just rises to of signal tN2, therefore the beacon signal 1204 of dither jump modulation control interval indicates dither jump modulation control interval 1206, show that load current is quite little, must carry out the switching signal of dither jump modulation control rupturing capacity transistor group, to reduce unnecessary handoff loss.
Figure 13 is a kind of execution mode of dither jump modulation controller 904, comprising a plurality of D flip-flops, trigger by described pulse VQB, cut apart this dither jump modulation control interval and produce described dither jump modulation signal 912 by the pulse number of counting this pulse VQB.Observe the dither jump modulation controller of Figure 13, except comprise three inputs receive this pulse VQB, this reference signal Vmode, with signal tN, also comprise dither jump modulation control input end 1308, in order to control the length of described dither jump modulation nidus.In execution mode shown in Figure 13, the value of this dither jump modulation control input end 1308 can be " 0 " or " 1 ".When the signal of this dither jump modulation control end 1308 is " 0 ", these a plurality of multiplexers 1302,1304, with 1306 selection signal be " 0 ", it is the switching cycle of this pulse VQB with the length that makes each dither jump modulating nidus that these a plurality of D flip-flops will counts this pulse VQB.When the signal of this dither jump modulation control end 1308 is " 1 ", these a plurality of multiplexers 1302,1304, be with 1306 selection signal " 1 " ', it is twice switching cycle of this pulse VQB with the length that makes each dither jump modulating nidus that these a plurality of D flip-flops will counts this pulse VQB.
Figure 14 jumps with dither and modulates the influence that the coherent signal waveform of controlling illustrates that signal SW_P is enabled in the setting of this dither jump modulation control end 1308 to described PMOS.The high level place of signal 1402 is a dither jump modulation control interval.When this dither jump modulation control end 1308 was " 0 ", the dither jump modulation signal that the dither jump modulation controller of Figure 13 is produced was a waveform 1404.As shown in the figure, the length of dither jump modulation nidus 1412 is the switching cycle of this pulse VQB, and it is waveform 1406 that pairing PMOS enables signal (SW_P).When this dither jump modulation control end 1308 was " 1 ", the dither jump modulation signal that the dither jump modulation controller of Figure 13 is produced was a waveform 1408.As shown in the figure, the length of dither jump modulation nidus 1414 is twice switching cycle of this pulse VQB; It is waveform 1410 that pairing PMOS enables signal (SW_P), can save more power supply.
Figure 15 modulates the execution mode of the dc voltage changer of controlling for adopting this dither to jump.Square 1506 will be formed load sensor shown in Figure 9 902 with the current detection circuit 1508 of this pulse generator.This dither jump modulation controller 1510 can be realized by circuit shown in Figure 13.
Though the present invention with preferred embodiment openly as above, so it is not in order to limit the present invention.Those of ordinary skill under any in the technical field under the situation that does not break away from the spirit and scope of the present invention, can carry out various changes and modification.Therefore, protection scope of the present invention is as the criterion with the scope of the claim that proposed.
Claims (16)
1. a dc voltage changer is characterized in that, comprising:
Load sensor detects the size of the load current of this dc voltage changer;
Variable-sized power transistor group has a plurality of P-type mos transistors that are connected in parallel to each other, and a plurality of N type metal oxide semiconductor transistors that are connected in parallel to each other; And
Power transistor size control and driver, be coupled between this load sensor and this variable-sized power transistor group, according to the size of this load current, control the transistorized conduction status of these a plurality of N type metal oxide semiconductors of these a plurality of P-type mos transistor AND gates.
2. dc voltage changer as claimed in claim 1, it is characterized in that, also comprise inductance, described P-type mos transistor couples the raw DC voltage source in order to the changing voltage output that makes this dc voltage changer through this inductance, and described N type metal oxide semiconductor transistor is coupled to earth terminal in order to make this changing voltage output through this inductance.
3. dc voltage changer as claimed in claim 2 is characterized in that, transistorized source electrode of these a plurality of P-type mos and drain electrode are respectively coupled to this raw DC voltage source and first node; And these a plurality of N type metal oxide semiconductor transistor drain and source electrode are respectively coupled to this first node and this earth terminal; Wherein this first node couples this changing voltage output through this inductance.
4. dc voltage changer as claimed in claim 3 is characterized in that, this load sensor will be the size conversion of this load current one group of thermometer-code, represent with a plurality of digital signals.
5. dc voltage changer as claimed in claim 4 is characterized in that, described N type metal oxide semiconductor transistor of the respectively corresponding described P-type mos transistor AND gate of these a plurality of digital signals.
6. dc voltage changer as claimed in claim 5 is characterized in that, this power transistor size control and driver comprise:
A plurality of first control units, described digital signal of a respectively corresponding described P-type mos transistor AND gate, when being initiate mode, determine the transistorized conducting state of pairing P-type mos according to pairing digital signal in order to enable signal at the P-type mos transistor; And
A plurality of second control units, described digital signal of a respectively corresponding described N type metal oxide semiconductor transistor AND gate, when being initiate mode, determine the transistorized conducting state of pairing N type metal oxide semiconductor according to pairing digital signal in order to enable signal at a N type metal oxide semiconductor transistor.
7. dc voltage changer as claimed in claim 6 is characterized in that, described these a plurality of first control units comprise separately:
Logical circuit, enabling signal in this P-type mos transistor is that initiate mode and pairing digital signal are exported a low level signal during for high level; And
Drive circuit makes this low level signal approach the current potential of this earth terminal with the pairing P-type mos transistor of conducting.
8. dc voltage changer as claimed in claim 6 is characterized in that, described these a plurality of second control units comprise separately:
Logical circuit, enabling signal in this N type metal oxide semiconductor transistor is that initiate mode and pairing digital signal are exported a high level signal during for high level; And
Drive circuit makes this high level signal approach the current potential in this raw DC voltage source with the pairing N type metal oxide semiconductor of conducting transistor.
9. dc voltage changer as claimed in claim 4 is characterized in that, described load sensor comprises:
Detect voltage generating circuit, the electric current of this inductance is dwindled into one with certain proportion detect electric current, and make this detections electric current flow through detecting resistance to produce detection voltage;
Sample-and-hold circuit, this detection voltage of taking a sample;
Current/charge-voltage convertor is a drive current with the detection voltage transitions of taking a sample, and its value is directly proportional with this detection voltage;
Current drives serial connection inverter delay circuit is formed by a plurality of delay cell serial connections, in order to transmit a high level signal, it is characterized in that,, these a plurality of delay cells comprise a plurality of inverters of serial connection separately, these a plurality of inverters are driven by this drive current respectively; And
A plurality of D flip-flops to should a plurality of delay cells, unifiedly extract signal triggering by one, in order to extract the output end signal of these a plurality of delay cells, to produce described digital signal.
10. direct current as claimed in claim 9 changes electric pressure converter, it is characterized in that, this detection voltage generating circuit comprises that also one detects with P-type mos transistor group, in order to form current mirror circuit dwindles this inductance with certain proportion electric current with described P-type mos transistor, wherein, this detection comprises a plurality of detections P-type mos transistor that is connected in parallel to each other with P-type mos transistor group, and these a plurality of detections are determined by these a plurality of digital signals with the transistorized conducting state of P-type mos.
11. a dc voltage changer is characterized in that, comprising:
Load sensor detects the size of the load current of this dc voltage changer;
Dither jump modulation controller, determine a dither that its length and this load current the be inverse ratio modulation control interval that jumps according to this load current, and cut apart this dither and jump modulation control interval exporting a dither jump modulation signal with the dither modulation unit that jumps, this dither jump modulation signal is a low level in this dither each dither of a modulation control interval dither of modulation unit modulation nidus that jumps that jumps that jumps;
Pulse generator produces a pulse according to the voltage of a changing voltage output of this dc voltage changer;
NAND door, its input couple inversion signal and this dither jump modulation signal of this pulse;
One power transistor is enabled signal generator, produces according to the output signal of this NAND door that a P-type mos transistor is enabled signal and a N type metal oxide semiconductor transistor is enabled signal; And
Power transistor group is enabled signal and this N type metal oxide semiconductor transistor is enabled signal controlling by this P-type mos transistor, to adjust the voltage of this changing voltage output.
12. dc voltage changer as claimed in claim 11, it is characterized in that, also comprise an inductance, be coupled between this power transistor group and this changing voltage output, described power transistor group will be enabled signal and N type metal oxide semiconductor transistor according to described P-type mos transistor and be enabled signal and make this changing voltage output be coupled to a raw DC voltage source or an earth terminal through this inductance.
13. dc voltage changer as claimed in claim 12 is characterized in that, described load sensor comprises:
Detect voltage generating circuit, the electric current of this inductance is dwindled into one with certain proportion detect electric current, and make this detections electric current flow through one detecting resistance to produce a detection voltage;
Sample-and-hold circuit, this detection voltage of taking a sample;
Current/charge-voltage convertor is a drive current with the detection voltage transitions of taking a sample, and its value is directly proportional with this detection voltage; And
Current drives serial connection inverter delay circuit is formed by a plurality of delay cell serial connections, and in order to transmit a high level signal, wherein, these a plurality of delay cells comprise a plurality of inverters of serial connection separately, and these a plurality of inverters are driven by this drive current respectively.
14. dc voltage changer as claimed in claim 13 is characterized in that, described dither jump modulation controller comprises:
First input end couples the output of a described delay cell; And
Second input couples a reference signal, and this reference signal rises to high level in reference time point by low level;
Wherein, jump signal that the modulation control interval is positioned at this first input end of described dither is that the signal of low level and this second input is the high level place.
15. dc voltage changer as claimed in claim 14 is characterized in that, described dither jump modulation controller also comprises:
The 3rd input couples described pulse;
A plurality of D flip-flops by described pulse-triggered, are cut apart this dither jump modulation control interval and are produced described dither jump modulation signal by the pulse number of counting this pulse.
16. dc voltage changer as claimed in claim 12 is characterized in that, this dither jump modulation controller also comprises dither jump modulation control input end, in order to control the length of described dither jump modulation nidus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101497613A CN101383560A (en) | 2007-09-05 | 2007-09-05 | DC voltage converter |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101497613A CN101383560A (en) | 2007-09-05 | 2007-09-05 | DC voltage converter |
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| CN101383560A true CN101383560A (en) | 2009-03-11 |
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| CNA2007101497613A Pending CN101383560A (en) | 2007-09-05 | 2007-09-05 | DC voltage converter |
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| CN101847991A (en) * | 2009-03-27 | 2010-09-29 | 台湾积体电路制造股份有限公司 | Clock generators, memory circuits, and methods for providing an internal clock signal |
| CN101924463A (en) * | 2010-09-10 | 2010-12-22 | 复旦大学 | PFM control method of switching power converter and realizing device thereof |
| CN101621056B (en) * | 2008-07-01 | 2011-11-16 | 立锜科技股份有限公司 | Multi-chip module for power supply circuit and voltage regulator using same |
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| CN105164598B (en) * | 2013-03-15 | 2017-09-12 | 沃尔泰拉半导体公司 | Voltage regulator with multiple transistors |
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| US9742282B2 (en) | 2013-08-30 | 2017-08-22 | Fitipower Integrated Technology, Inc. | Switching power voltage regulator for regulating electric energy to load |
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