CN101350036B - High speed real-time data acquisition system - Google Patents
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- CN101350036B CN101350036B CN2008100542955A CN200810054295A CN101350036B CN 101350036 B CN101350036 B CN 101350036B CN 2008100542955 A CN2008100542955 A CN 2008100542955A CN 200810054295 A CN200810054295 A CN 200810054295A CN 101350036 B CN101350036 B CN 101350036B
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Abstract
The invention discloses a novel high-speed real-time data acquisition system, which comprises a signal source which is used to output an analog signal to an analog-to-digital converter, the analog-to-digital converter which is used to convert the analog signal which is output by the signal source into a digital signal which can be compiled and to output the digital signal, a field programmable gate array FPGA chip which is used to store the digital signal which is output by the analog-to-digital converter and to control the input and the output of the digital signal, and a data stream operation processing module which is used to carry out signal processing to the digital signal which is output by the FPGA chip. The invention is based on the FPGA technique, a first DPRAM, a second DPRAM and a control logic module are integrated in the FPGA chip, and the stability of a clock is well guaranteed to prevent burrs. Simultaneously, since two blocks of DPRAMs are combined into ping-pong operations, thereby the data acquisition system which is provided by the invention can conveniently and effectively realize data real time transmission and storage.
Description
Technical field
The present invention relates to the data acquisition technology field, particularly relate to a kind of novel high speed real-time data acquisition system.
Background technology
Along with development of modern science and technology, data acquisition technology has been penetrated into numerous technical fields such as geologic prospecting, medicine equipment, radar, observing and controlling, and people have proposed more and more higher requirement to the sampling rate of data.At analog to digital conversion (Analog Digital, AD) in the sampling system, traditional crystal oscillator adds the analog form of thinking circuit and filtering circuit can not satisfy this requirement, and the dirigibility of the clock module of the clock chip of employing special use is not enough, current new technology trends is to use FPGA (FieldProgrammable Gate Array, be field programmable gate array) technology, adopt internal proprietary clock module and the logical resource of FPGA to make up the module of high precision clock flexibly that can satisfy system requirements.
Analog to digital converter is as the bridge of simulating signal and digital signal, and its application is extensive day by day.The current new theory that continues to bring out, new algorithm, the raising of digital signal processor spare performance has in addition promoted the development of data acquisition system (DAS).The speed of frequently-used data acquisition system is generally at several MSps～hundreds of MSps (Millionsamples per second at present, 1,000,000 sampling/seconds), be sent to the lower DSP of performance (Digital Signal Processing through data after A by memory buffer, digital signal processing) processor, perhaps send into microcomputer by various buses, so the data of being gathered can not get handling timely, be difficult to satisfy the requirement of real time data acquisition, and the controlling of sampling interface circuit that is adopted need take a large amount of DSP resource and bus resource.
Referring to Fig. 1, in traditional data acquisition system (DAS), the control of AD and the unloading of data can be controlled by microprocessor.This mode is used for high-speed data acquistion system will waste a large amount of CPU (Central processing unit, central processing unit) resource, and for MCU (Micro Controller Unit, miniature control module, be also referred to as one chip microcomputer), may not control the collection and the storing process of high-speed data.Because generally the result of AD conversion is read in, and then dump in the outer storer (RAM as shown) of sheet, this process needs 4 machine cycles at least, adopt traditional microprocessor or ARM (Advanced RISC Machines, senior risc microcontroller) scheme can not satisfy the needs of system at all.
Along with the propelling of digital revolution, data storage technology had also been obtained swift and violent development in recent years.In electronics and computer technology develop rapidly today, Digital Signal Processing has become one of most important means that information obtains.Each application is to the real-time of digital signal processing simultaneously, and integrated level and dirigibility are also had higher requirement.The low speed that oneself has, non real-time data acquisition processing system are difficult to satisfy this high-end demand.
In some intelligence instruments, often need carry out lot of data collection and storage operation.For example, in the precision agriculture operation, need to gather the information such as longitude, latitude, output and humidity of each sampled point in the field, sampled point has thousands of like this, so produced lot of data, the storage that guarantees these field datas at present is one of key issue in the TT﹠C system design.To intelligence instrument based on PC, these data can be directly deposit hard disk in the form of DOS or Windows file, and for SCM Based field apparatus, then slow, do not have reasons such as operating system support and memory capacity are little owing to system handles speed, be difficult to satisfy above-mentioned requirements.RAM (the random-access memory of the storage unit that common single-chip microcomputer is supported, random access memory), EEPROM (Electrically Erasable Programmable Read-OnlyMemory, EEPROM (Electrically Erasable Programmable Read Only Memo)) or the Flash storage chip of low capacity, their common feature is the restriction that is subjected to addressing space, can not satisfying magnanimity the requirement of storage, can't high-speed real-time ground realize the transmission and the storage of data, therefore for the high-speed multiple channel data acquisition, common single-chip microcomputer is difficult to satisfy the requirement of system to real time data acquisition and synchronism.
Summary of the invention
In view of this, the purpose of this invention is to provide a kind of novel high speed real-time data acquisition system, can high-speed real-time ground realize the transmission and the storage of institute's image data.
For this reason, the invention provides a kind of novel high speed real-time data acquisition system, comprising:
Signal source is used to export simulating signal and gives analog to digital converter;
Analog to digital converter, digital signal that the analog signal conversion that is used for that signal source is exported becomes can compile and output;
The on-site programmable gate array FPGA chip is used to store the digital signal of analog to digital converter output and the input and the output of control figure signal;
The dataflow computing processing module, the digital signal streams that is used for fpga chip is exported carries out signal Processing;
Described fpga chip comprises: be used for the first data cached dual port random access storer DPRAM and the second dual port random access storer DPRAM, and be used for a DPRAM and the 2nd DPRAM are read and write the Logic control module of control, a wherein said DPRAM and the 2nd DPRAM form the table tennis working method.
Preferably, a described DPRAM and the 2nd DPRAM form the table tennis working method.
Preferably, described Logic control module comprises: the input traffic selected cell, and ground is assigned to a DPRAM or the 2nd DPRAM with the digital signal of analog to digital converter output when being used for waiting; The output stream selected cell, ground selects the digital signal streams of output the one DPRAM or the 2nd DPRAM to give the dataflow computing processing module when being used for waiting.
Preferably, described Logic control module also includes the calculation process control module, is used for coming according to the state of analog to digital converter the operation of control data stream calculation process module.
Preferably, be connected with the low-pass signal wave filter between described signal source and the analog to digital converter, be used for the high frequency noise of erasure signal source institute output signal.
Preferably, described dataflow computing processing module is a digital signal processor DSP.
Preferably, described dataflow computing processing module is connected with external memory interface EMIF by Serial Peripheral Interface SPI with fpga chip.
By above technical scheme provided by the invention as seen, the present invention is based on the FPGA technology, FPGA (field programmable gate array) chip internal integrated two DPRAM (i.e. a DPRAM and the 2nd DPRAM) and control logic module, guaranteed the stable of clock well, prevent that burr from occurring.Compare with FIFO with traditional RAM, DPRAM had both had because of the non-interfering input/output port of two covers is arranged, and helped keeping pure, the stable advantage of clock when switching the input and output clock.Simultaneously because two DPRAM form ping-pong operation, and promptly in a DPRAM reading of data, another piece DPRAM carries out write data, so make data acquisition system (DAS) provided by the invention can realize data in real time transmission and storage easy and effectively.
Fig. 1 is the block diagram of traditional data acquisition system (DAS);
Fig. 2 is the composition frame chart of the novel high speed real-time data acquisition system based on DPRAM provided by the invention;
Fig. 3 is the composition frame chart of first embodiment of fpga chip Logic control module among the present invention;
Fig. 4 is the composition frame chart of second embodiment of fpga chip Logic control module among the present invention;
Fig. 5 is the composition frame chart of the present invention that is connected with the low-pass signal wave filter.
Embodiment
In order to make those skilled in the art person understand the present invention program better, the present invention is described in further detail below in conjunction with drawings and embodiments.
Fig. 2 is the block diagram of the novel high speed real-time data acquisition system based on DPRAM (dual port random access storer) provided by the invention, referring to Fig. 2, a kind of high speed real-time data acquisition system provided by the invention, this system comprises signal source 201, analog to digital converter 202, on-site programmable gate array FPGA chip 203 and dataflow computing processing module 204, wherein:
Analog to digital converter 202 is connected with signal source 201, is used for digital signal and output that the analog signal conversion that signal source 201 is exported is become can compile;
On-site programmable gate array FPGA chip 203 is used to store the digital signal of analog to digital converter 202 outputs and the input and the output of control figure signal; In the present invention, this fpga chip 203 comprises: be used for the first data cached dual port random access storer (DPRAM) 2031 and the second dual port random access storer (DPRAM) 2032, and be used for a DPRAM2031 or the 2nd DPRAM2032 are read and write the Logic control module 2033 of control.
Described Logic control module 2033 is connected with a DPRAM2031, the 2nd DPRAM2032 respectively.
Referring to Fig. 3, described Logic control module 2033 specifically comprises: input traffic selected cell 20331 that is connected with a DPRAM2031, the 2nd DPRAM2032 and output stream selected cell 20332 respectively, wherein, input traffic selected cell 20331, ground is assigned to a DPRAM2031 or the 2nd DPRAM2032 with the digital signal of analog to digital converter 202 outputs when being used for waiting; Output stream selected cell 20332, ground selects the digital signal streams of output the one DPRAM2031 or the 2nd DPRAM2032 to give dataflow computing processing module 204 when being used for waiting.
Dataflow computing processing module 204 is connected with fpga chip 203, is used for the digital signal streams that fpga chip 203 is exported is carried out signal Processing.As shown in Figure 2, dataflow computing processing module and fpga chip 203 by Serial Peripheral Interface (Serial Peripheral Interface, SPI) and external memory interface (External Memory Interface EMIF) is connected.
In Logic control module 2033 of the present invention, referring to Fig. 4, also comprise calculation process control module 20333, be used for coming the operation of control data stream calculation process module according to the state of analog to digital converter.For example, the analog to digital converter data sampling finishes or the buffer full of analog to digital converter overflows, and sends look-at-me to dsp processor, and DSP is out of service in control.
For electromagnetic interference that solves the output line road and the electromagnetic interference (EMI) that is received from the outside, referring to Fig. 5, the present invention also is connected with low-pass signal wave filter 205 between signal source 201 and analog to digital converter 202, be used for the high frequency noise of 201 output signals in erasure signal source.By at the set low-pass signal wave filter 205 of analog to digital converter 202 front ends, can the filtered signal transmission line on the unwanted high frequency interference composition of various work.
The present invention is based on the FPGA technology, FPGA (field programmable gate array) chip internal integrated two DPRAM (i.e. a DPRAM and the 2nd DPRAM) and control logic module, guaranteed the stable of clock well, prevent that burr from occurring.
Need to prove, in data acquisition system (DAS) provided by the invention, the intermediate-freuqncy signal frequency of being gathered is 36MHz (megahertz), sampling clock is 28.8MHz, DPRAM (Dual PortRandom-Access Memory, dual port RAM) output clock is 50MHz, so the input of DPRAM, output clock difference that is to say DPRAM plays cross clock domain and cushions in system effect.Because DPRAM has two to overlap independently input/output port, its input port meets 28.8MHz, and output port meets 50MHz, thereby has avoided clock is carried out the processing of any combinational logic, has avoided the deformity of clock, for follow-up logic control lays the first stone.
The high speed real-time data acquisition system that the present invention is based on DPRAM relates to storer and all relevant steering logics of utilizing FPGA to realize that sheet is interior, the IP CORE that utilizes XILINX company to carry generates two DPRAM, compare with FIFO with traditional RAM, DPRAM had both had because of the non-interfering input/output port of two covers is arranged, pure, the stable advantage that when switching the input and output clock, helps keeping clock, have easy to learnly again, be difficult for makeing mistakes, save the benefit of development time.Utilize two DPRAM to form ping-pong operation, realize real-time storage.Facts have proved that highest frequency of the present invention can reach 130MHz.
In addition, in the present invention, because two DPRAM form ping-pong operation, promptly in a DPRAM reading of data, another piece DPRAM carries out write data, so make data acquisition system (DAS) provided by the invention can realize data in real time transmission and storage easy and effectively.
In the present invention, described dataflow computing processing module 204 is preferably dsp processor.
Need to prove that DSP (Digital Signal Processor, digital signal processing) processor is a device of handling bulk information with digital signal.Dsp processor is a kind of microprocessor device that is particularly suitable for carrying out the digital signal processing computing, and it is mainly used is to realize various digital signal processing algorithms real-time.It is not only programmable, and travelling speed can reach the per second number with ten million bar complicated order program in fact the time, considerably beyond general purpose microprocessor, is the computer chip that becomes more and more important in the digitalized electron world.It has powerful data-handling capacity and high travelling speed.
In concrete practice, the concrete logic control operation of Logic control module 2033 comprises:
(1) control address decoded signal, address decode signal is used in many places in native system, such as: command register, status register etc.Can programme by VHDL language easily and realize.
(2) control various control signals, comprise that read-write control signal, systematic reset signal, two DPRAM reset signals, command register signals of two DPRAM reset or the like.
(3) signal of control data stream calculation process module 204 (as dsp processors) interruption, specifically be set to: interruption 0:A/D sampling finishes and interrupts; Interruption 1:A/D buffer full overflows and interrupts; Interrupt 2: emergency stop and interrupting.
For data acquisition system (DAS) provided by the invention, concrete table tennis transmission control procedures are: input traffic is by input traffic selected cell 20331, and ground is assigned to input traffic among the one DPRAM2031, the 2nd DPRAM2032 when waiting.At the 1st buffer circle, data flow cache to the DPRAM2031 with input, at the 2nd buffer circle, switching by input traffic selected cell 20331, data flow cache to the two DPRAM2032 with input, meanwhile, with the selection of the data in the 1st cycle of a DPRAM2031 buffer memory, deliver to dataflow computing processing module 204 by calculation process by output stream selected cell 20332.At the 3rd buffer circle, switching once more by input traffic selected cell 20331, data flow cache to the DPRAM2031 with input, meanwhile, with the switching of the data in the 2nd cycle of the 2nd DPRAM2032 buffer memory, deliver to dataflow computing processing module 204 by calculation process by output stream selected cell 20332.So circulation goes round and begins again, thereby can realize data in real time transmission and storage easy and effectively.
Compare with the traditional data acquisition system, clock in this novel high speed real-time data acquisition system assurance system is purer, not distortion, realized that simultaneously the construction cycle short, advantages such as circuit area is little, overcome the drawback in the design of traditional data acquisition system, effectively solved the real-time problem of data acquisition system (DAS).
The present invention is according to the advanced technology of FPGA and supporting developing instrument, the novel high speed real-time data acquisition system of exploitation, it uses DPRAM (Dual Port Random-access Memory, dual port RAM) replaces traditional RAM or FIFO (First In First Out, pushup storage), has and both meet functional requirement, and the advantage of higher-quality clock is arranged, be convenient to exploitation again, the benefit that is difficult for makeing mistakes.Significantly reduce the construction cycle, improved economic benefit.
The present invention concentrates on two DPRAM and whole relevant control logic module in the fpga chip, has not only reduced circuit area greatly, and circuit is standardized more, is easy to revise.
With the control core of FPGA, realize the collection and the processing of multi-channel analog signal as data acquisition.Because the control of FPGA centralized procurement sample, processing, buffer memory, transmission control, communication are in a chip, programmed configurations is flexible, construction cycle is short, system is simple, have that high integration, volume are little, low-power consumption, at a high speed, advantage such as many, the in-system programming of I/O port, be specially adapted to sequential is had the high-speed multiple channel data acquisition system (DAS) of strict demand.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1. a high speed real-time data acquisition system is characterized in that, comprising:
Signal source is used to export simulating signal and gives analog to digital converter;
Analog to digital converter, digital signal that the analog signal conversion that is used for that signal source is exported becomes can compile and output;
The on-site programmable gate array FPGA chip is used to store the digital signal of analog to digital converter output and the input and the output of control figure signal;
The dataflow computing processing module, the digital signal streams that is used for fpga chip is exported carries out signal Processing;
Described fpga chip comprises: be used for the first data cached dual port random access storer DPRAM and the second dual port random access storer DPRAM, and be used for a DPRAM and the 2nd DPRAM are read and write the Logic control module of control, a wherein said DPRAM and the 2nd DPRAM form the table tennis working method.
2. high speed real-time data acquisition system as claimed in claim 1 is characterized in that, described Logic control module comprises: the input traffic selected cell, and ground is assigned to a DPRAM or the 2nd DPRAM with the digital signal of analog to digital converter output when being used for waiting; The output stream selected cell, ground selects the digital signal streams of output the one DPRAM or the 2nd DPRAM to give the dataflow computing processing module when being used for waiting.
3. high speed real-time data acquisition system as claimed in claim 2 is characterized in that described Logic control module also includes the calculation process control module, is used for coming according to the state of analog to digital converter the operation of control data stream calculation process module.
4. high speed real-time data acquisition system as claimed in claim 1 is characterized in that, is connected with the low-pass signal wave filter between described signal source and the analog to digital converter, is used for the high frequency noise of erasure signal source institute output signal.
5. high speed real-time data acquisition system as claimed in claim 1 is characterized in that, described dataflow computing processing module is a digital signal processor DSP.
6. high speed real-time data acquisition system as claimed in claim 1 is characterized in that, described dataflow computing processing module is connected with external memory interface EMIF by Serial Peripheral Interface SPI with fpga chip.
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| CN102556792A (en) * | 2012-03-13 | 2012-07-11 | 杭州市特种设备检测院 | Online analysis meter and online analytical method for operation performance of elevator |
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| CN104239232B (en) * | 2014-09-10 | 2017-05-10 | 北京空间机电研究所 | Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) |
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| CN104461971A (en) * | 2014-11-26 | 2015-03-25 | 深圳市开立科技有限公司 | Data collecting control system and method |
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| CN113489493B (en) * | 2021-07-28 | 2023-08-08 | 江苏集萃智能集成电路设计技术研究所有限公司 | Time-sharing multiplexing control system of analog-digital converter and time-sharing multiplexing method thereof |
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| CN102556792A (en) * | 2012-03-13 | 2012-07-11 | 杭州市特种设备检测院 | Online analysis meter and online analytical method for operation performance of elevator |
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