CN101345745B - Data framing method and equipment thereof - Google Patents
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Abstract
The present invention relates to the communication field, and discloses a data framing method and equipment thereof, which reduces the probability of synchronization error. In the invention, M verifying blocks are obtained by coding N data blocks, wherein each data block contains a data synchronization header, each verifying block contains a verifying synchronization header, the data synchronization header and the verifying synchronization header are different, the N data blocks are divided into X parts, and the M verifying blocks are divided into Y parts (N>=X>=1, M>=Y>=1, at least on of X and Y is greater than 1, the difference of the absolute values of X and Y is less than 2). Then, various parts of the data blocks and verifying blocks are arranged with an interval between each other to form a frame.
Description
Technical field
The present invention relates to the communications field, particularly the data framing technology.
Background technology
Along with the continuous development of the communication technology, the user to the various service quality such as capacity, speed of communication require increasingly high.Because Access Network is one of the challenging zone that possesses skills most in the whole telecommunications network, therefore in order to satisfy user's requirement growing, the high speed of realization Access Network, broadband and intelligent, the appearance that various access technologies emerge in an endless stream to bandwidth.Wherein, being considered to the most promising is EPON (Passive Optical Network is called for short " PON ") technology, especially Ethernet passive optical network (Ethernet Passive Optical Network is called for short " EPON ") technology.
Because EPON is a kind of technology that adopts the passive light transmission, does not use the components and parts with amplification and relay function.Therefore the transmission range and the number of branches of EPON network depend on power budget and various loss.Along with the increase of transmission range or branching ratio number, the signal to noise ratio of transmission data (Signal NoiseRatio is called for short " SNR ") reduces gradually, thereby has just caused the more bits mistake.In order to address this problem, in the EPON system, to have introduced forward error correction (Forward Error Correction is called for short " FEC ") technology and improved the antijamming capability of system, to increase the power budget of system.
The basic functional principle of FEC in the EPON system is: affix FEC check code word behind the ethernet frame that transmitting terminal is transmitted; These check code words with by the ethernet frame data of verification with certain regular interrelated (constraint) of confirming; Receiving terminal is by the set rule test ethernet frame data and the relation of check code word; In case make a mistake in the transmission, will destroy this relation, thereby realize error correction ethernet frame data.The FEC technology makes every effort to correct mistake as much as possible with the least possible check byte, between expense (increased check byte and bring expense) and the coding gain that obtains, finds the balance point an of the best.
In the EPON system; For the data that make transmission are forms that receiver can receive; Before adopting the FEC technology, need to use the line coding technology, this line coding must guarantee that also the data of being sent have enough switchings (promptly 0, the conversion between 1) can recovered clock with the assurance receiving terminal.In the standard relevant, used the higher line coding mechanism of code efficiencies such as 64B/66B at Physical Coding Sublayer (Physical Coding Sublayer is called for short " PCS ") with Ethernet system.64B/66B line coding mechanism is on the basis of 64 bit informations; 2 different bit synchronous characters (" 01 " or " 10 ") have been increased as synchronous head (being called the data sync head); Form the line coding piece (being called data block) of 66 bits, promptly comprise the information data of 64 bits and the data sync head of 2 bits thereof in each data block.Wherein, the data block synchronous head is that " 01 " (or " 10 ") expression 64 bit informations all are data; For comprising data and control information in " 10 " (or " 01 ") expression 64 bit informations; For in " 00 " or " 11 " expression transmission course mistake has taken place.When the number of data blocks behind the 64/66b line coding reaches FEC and encodes desired data length, carry out the FEC coding.
Produce relevant check information through FEC coding back.The length of check information is 64 multiple, is the check information piece of unit thereby can check information be formed with 64 bits.Add the synchronous head (be called verification synchronous head) of the synchronization character (" 00 " or " 11 ") of 2 same bits then as the check information piece in the front of check information piece; Form the check block of 66 bits, each check block comprises the check information of 64 bits and the verification synchronous head of 2 bits thereof.
As shown in Figure 1 to a kind of information frame (being fec frame) structure of the PCS layer in the 10GEPON system at present.1 complete fec frame is made up of data block and check block, is positioned at the front of fec frame in the set of data blocks, and check block is concentrated the back that is positioned at fec frame.Owing to contain the data sync head of 2 bits in the data block of per 66 bits; The data sync head of this 2 bit is inequality always; And contain the verification synchronous head of 2 bits in the check block of per 66 bits; The verification synchronous head of this 2 bit is always identical, therefore utilizes these information to realize the synchronous of data block and check block at receiving terminal, thereby is convenient to carry out FEC decoding and circuit decoding.
Yet; Inventor of the present invention finds, because in a fec frame, the data sync head is random; Possibly be that " 01 " also possibly be " 10 "; This is by transmitting the data type decision, and the verification synchronous head is good according to prior stipulative definition, and promptly system knows that the verification synchronous head of certain check block in this fec frame is " 00 " or " 11 ".And in transmission course, have reasons such as noise jamming, and the data sync head in the data block may become " 00 " or " 11 " from original " 01 " or " 10 ", and system can sentence it as the verification synchronous head of check block by mistake; The verification synchronous head of check block also possibly make a mistake, and is the data sync head of data block by system's erroneous judgement.Therefore, take place in system just false sync might occur under the situation of erroneous judgement.
Fig. 2 has provided the synchronous sketch map that makes a mistake; If error of transmission all takes place in data sync head, the verification synchronous head of first check block and the verification synchronous head of last check block in the previous fec frame of last data block in fec frame; Make a mistake simultaneously in the position that is (1) among Fig. 2～(3); Position (1) is " 11 " by " 00 " mistake, and position (2) are verification synchronous head " 00 " by data sync head mistake, and position (3) are the data sync head by verification synchronous head " 11 " mistake; Last check block of the partial frame of this fec frame and preceding 1 fec frame will be mistaken for a complete fec frame so, thereby makes a mistake synchronously.That is to say; In the frame structure of prior art; Between the new frame that a complete fec frame and several block of informations of this frame slip (data block and check block are referred to as block of information) back constitute the higher degree of correlation is arranged; When conducting frame is synchronous, the synchronous situation that just might make a mistake, thus reduced the performance of system.
Summary of the invention
The technical problem underlying that embodiment of the present invention will solve provides a kind of data framing method and equipment thereof, makes the probability of false sync be minimized.
For solving the problems of the technologies described above, execution mode of the present invention provides a kind of data framing method, may further comprise the steps:
N data block encoded obtains M check block, wherein comprises the data sync head in each data block, comprises the verification synchronous head in each check block, and data sync head and verification synchronous head are inequality;
N data block is divided into X part, M check block is divided into Y part, N >=X >=1, M >=Y >=1 has one at least greater than 1 among X, the Y, and the difference of the absolute value of X and Y is less than 2;
With the data block of each several part and check block apart from one another by rearranging a frame.
Execution mode of the present invention also provides a kind of data framing equipment, comprising:
Coding unit, being used for N data block encoded obtains M check block, wherein comprises the data sync head in each data block, comprises the verification synchronous head in each check block, and data sync head and verification synchronous head are inequality;
Division unit is used for N data block is divided into X part, and M check block is divided into Y part, N >=X >=1, and M >=Y >=1 has one at least greater than 1 among X, the Y, and the difference of the absolute value of X and Y is less than 2;
Arrangement units, the data block of the each several part that is used for division unit is divided and check block are apart from one another by rearranging a frame.
Embodiment of the present invention compared with prior art, the main distinction and effect thereof are:
N data block encoded obtains M check block, wherein comprises the data sync head in each data block, comprises the verification synchronous head in each check block; Data sync head and verification synchronous head are inequality, and N data block is divided into X part, and M check block is divided into Y part; N >=X >=1; M >=Y >=1 has one at least greater than 1 among X, the Y, the difference of the absolute value of X and Y is less than 2.Then, with the data block of each several part and check block apart from one another by rearranging a frame.Owing to no longer all check blocks all are placed on after the data block; But check block and data block are intersected placement; Therefore can reduce the degree of correlation between the new frame that constitutes after several block of informations of a complete fec frame and this fec frame slip; When thereby conducting frame is synchronous, reduced the probability that the fec frame false sync takes place.
Description of drawings
Fig. 1 is according to fec frame structure of the prior art;
Fig. 2 is according to the synchronous sketch map that makes a mistake of the prior art;
Fig. 3 be according in the data framing method of first embodiment of the invention with the data block of each several part and check block apart from one another by arranging sketch map;
Fig. 4 is the data framing method flow chart according to first embodiment of the invention;
Fig. 5 is the data framing method sketch map according to first embodiment of the invention;
Fig. 6 is according to the error pattern sketch map in the first embodiment of the invention;
Fig. 7 is the data framing method sketch map according to second embodiment of the invention;
Fig. 8 is the data framing device structure sketch map according to third embodiment of the invention.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, will combine accompanying drawing that execution mode of the present invention is done to describe in detail further below.
First execution mode of the present invention relates to a kind of data framing method; In this execution mode; To N data block behind FEC coding and M check block apart from one another by rearranging a fec frame; Be about to N data block and be divided into X part, M check block is divided into Y part, with the data block of each several part and check block apart from one another by rearranging a frame; N >=X >=1 wherein, M >=Y >=1 has one at least greater than 1 among X, the Y, and the difference of the absolute value of X and Y is less than 2.If X=Y=p is then as shown in Figure 3, in a complete fec frame, at first place N
1And then individual data block places M
1Individual check block is placed N then
2And then individual data block places M
2Individual check block, and the like, last N
pIndividual data block followed M
pIndividual check block.Like this, all data blocks have been divided into p section, wherein N respectively with all check blocks
1+ N
2+ ... N
p=N, M
1+ M
2+ ... M
p=M.
Be that example describes below with X=Y=2, idiographic flow is as shown in Figure 4.
In step 410, original information data to be verified is carried out scrambling.Specifically, after information data is sent to the PCS layer from Ethernet media independent interface, be that unit is divided into the little block message of N with original information data with per 64 bits.Then, every little block message is carried out scrambling, obtain the S after the scrambling
iBlock message (i=0,1 ... N), as shown in Figure 5.Through information data is carried out scrambling, can guarantee to the full extent that institute's transmission information has enough switchings, thereby be convenient to the clock recovery of receiving terminal.
Then, get into step 420, to S through scrambling
iBlock message carries out the 64B/66B line coding, generates data block.Specifically, to the S of per 64 bits
iPiece carries out line coding, and the process of line coding is at S
iThe piece front adds the synchronous head of dibit, i.e. data sync head, one of them bit (like the 2nd bit) have carried this S of indication
iThe information of data type in the piece claims that with this bit this is the nose heave bit of wanting of data sync.Such as this significant bits is that " 0 " (also can be " 1 ") represented this S
iAll data in the piece; For " 1 " (also can be " 0 ") represented this S
iHave control information in the piece.The another one bit of data sync head (like the 1st bit) is referred to as less important bit, wants the negate of bit for data sync is nose heave, to guarantee that 2 bits in the data sync head are the inequality bit.As shown in Figure 5, in the data block that via line coding back generates, except that the information data that comprises 64 bits, also comprise the data sync head of 2 bit inequalities.
Then, get into step 430, information data in the data block that generates and the significant bits in the data sync head are carried out the FEC coding, obtain check information, and generate the check information piece.Specifically, the data block that via line coding back is generated is sent to line coding code word buffer memory/order module.Suppose that the desired length of FEC coded frame is 65 * N bit; Then when line coding code word buffer memory/order module receives N data block, go out this N data block movement, wherein the information data with significant bits in the data sync head of data block and 64 bits is sent to the FEC encoder.Less important bit in the data sync head directly is sent to synchronous head buffer memory/order module.By the FEC encoder to the information data in N the data block of receiving and with the data sync head in significant bits (totally 65 * N bit), carry out FEC coding, obtain check information.After obtaining check information, be that unit is divided into the check information piece with check information with 64 bits again.As shown in Figure 5, generation with N the corresponding M of a data block check information piece be P
i(i=1,2 ..., M).
Because the less important bit in the data sync head is not participated in the FEC coding; Effectively having reduced needs the amount of information through the FEC coding protection; Make more redundant (check bit) protect to the least possible Useful Information data; Thereby obtain bigger coding gain, increased the power budget of system.And because the bit that is used for the designation data type has been carried out the FEC coding protection, bigger coding gain can improve the correct probability that the data type is judged.
Then, get into step 440,, obtain M check block for each check information piece adds the verification synchronous head (like " 00 " or " 11 ") of 2 same bits.For the check information piece adds the verification synchronous head is for data block in the frame and check block are made a distinction, so that receiving terminal is realized the synchronous of data block and check block, thereby carries out FEC decoding and circuit decoding.
Then, get into step 450, N data block is divided into the X part, M check block is divided into the Y part.Such as, be 30 at N, M under 5 the situation, can be divided into 2 parts with 30 data blocks, and preceding 12 data blocks are as the N of first
1, back 18 data blocks are as second portion N
25 check blocks also are divided into 2 parts, and preceding 3 check blocks are as the M of first
1, back 2 check blocks are as second portion M
2
Then, get into step 460, with the data block of each several part and check block apart from one another by rearranging a frame.Specifically, to N data block and M the framing procedure that check block carries out, be actually the position of array data block sum check piece in frame.Place the preceding N in N the data block at first, earlier
1Individual data block, and then place the preceding M in M the check block
1Individual check block is placed successively, last N
pIndividual data block followed M
pIndividual check block.Wherein, the number of all data blocks is N in the frame, and the number of check block is M, and the data length in this frame is 66 * (N+M), and is as shown in Figure 5.Owing to be that example describes in this execution mode, that is to say that N data block only is divided into 2 parts, N=N with X=Y=2
1+ N
2, M check block also only is divided into 2 parts, M=M
1+ M
2Therefore, in framing procedure, place N earlier
1Individual data block is placed M again
1Individual check block, and then place N
2Individual data block is placed M at last
2Individual check block.After N data block and M check block formed fec frame, can be in harmonious proportion device through code check and send the physical medium additional sub to.
Through with data block and check block apart from one another by rearranging a fec frame, can reduce the probability that the fec frame false sync takes place.The demonstration that is this conclusion is convenient, below the notion of first definition error pattern.
Error pattern is represented a fec frame, and all produce the situation of false sync, and are as shown in Figure 6.The synchronous main cause that leads to errors is because mistake has taken place the synchronous head of data block or check block, produces erroneous judgement thereby cause.Therefore the data block of fec frame and the synchronous head sequence of check block have only been provided among Fig. 6.A complete fec frame is made up of 3 data blocks and 3 check blocks.Wherein 3 check block synchronous heads in the fec frame are " 00 ", " 00 ", " 11 ".If in transmission course; The 2nd check block synchronous head of fec frame is " 11 " by " 00 " mistake, and the 3rd data block synchronous head is " 00 " by " 10 " mistake, and last check block of going up a fec frame simultaneously is " 10 " by " 11 " mistake; Common property is given birth to 4 bit mistakes; Last check block of going up a fec frame so can be mistaken for a fec frame together with the first five block of information of this fec frame, thereby false sync occurs, corresponding to " sliding 1 block of information false sync " among Fig. 6.These 4 bit mistakes are called and cause " sliding 1 block of information false sync " required minimal error bit number.As shown in Figure 6 equally, if in the position of arrow indication 6 bit mistakes take place simultaneously, the situation of sliding 2,3,4 block of information false sync will appear so.Occur 4 wrong meetings simultaneously in corresponding position and sliding 5 block of information false sync occur.Fig. 6 has comprised by 3 data blocks and 3 fec frames that check block constitutes, wherein 3 situation that the check block synchronous head is all false sync of " 00 ", " 00 ", " 11 ".Therefore, can be expressed as with error pattern: S
Err=(4
2, 6
3).Wherein, " 4 " and " 6 " are respectively the minimum error bit number that causes certain false sync situation required.More particularly, to cause sliding 1,5 required minimum error bit number of these 2 kinds of false sync situation of block of information be 4 in " 4 " expression.Describe for the back literary composition is convenient, claim that " 4 " and " 6 " are the synchronous sample that leads to errors.Subscript " 2 " and " 3 " are illustrated in all situation that produce false sync, and the situation number that leads to errors synchronous by 4 and 6 bit mistakes is respectively " 2 " and " 3 ", is referred to as the synchronous number of samples that leads to errors later on.
This shows that error pattern is an important indicator weighing the synchronous probability that makes a mistake.The false sync probability is to be decided by smallest sample value in the error pattern and smallest sample quantity.Smallest sample value is big more, and perhaps smallest sample quantity is few more, and its probability that produces false sync is more little.
Experimental result proves, adopts the scheme of this execution mode, can reduce the probability that the fec frame false sync takes place.Such as, constitute by N=30 data block and M=5 check block at fec frame, wherein the verification synchronous head sequence of 5 check blocks is: { 00; 11,11,11; Under the situation of 00},, be about to 30 data blocks and be placed on the front if adopt the framing mode of prior art scheme; 5 check blocks are put behind, and then through analyzing the error pattern that draws are: S
Err=(6
2, 8
4, 10
28), promptly the smallest sample of false sync is 6, its sample size is 2.That is to say, in all synchronous heads, (comprise data sync head and verification synchronous head), just might lead to errors synchronously as long as 6 bit generation errors of transmission are arranged.
And if adopt the scheme of this execution mode, be about to 30 data blocks and be divided into 2 parts, preceding 12 data blocks are as the N of first
1, back 18 data blocks are as second portion N
25 check blocks also are divided into 2 parts, and preceding 3 check blocks are as the M of first
1, back 2 check blocks are as second portion M
2And with N
1, M
1, N
2, M
2Order form a fec frame, then be: S through analyzing the error pattern that draws
Err=(8
8, 10
26), promptly the smallest sample of false sync is 8, its sample size is 8.That is to say that in all synchronous heads, (comprising data sync head and verification synchronous head) will have 8 bit generation errors of transmission at least, just might lead to errors synchronously.
This shows that this execution mode can reduce the probability that the fec frame false sync takes place, thereby improved the performance of system.
According to experimental result, provide when X=Y=2 below, the piece of check block is counted error pattern and the corresponding verification synchronous head sequence thereof that M gets different value.
Table 1 has provided the piece of check block and has counted under the situation of M=5, adopts the error pattern and its corresponding check synchronous head sequence of different segmented modes.N representes the piece number of data block in table 1.Work as M
1=0, M
2=5 o'clock, the framing mode of expression prior art (promptly all check blocks are concentrated and are placed on after the data block).All the other situation are the framing mode of this execution mode.Can find that from table 1 after employing was segmented into frame, the smallest sample of error pattern was 8, and the smallest sample of the error pattern of prior art framing mode is 6.Therefore, adopt the framing mode of this execution mode can reduce the false sync probability.In table 1, give the verification synchronous head sequence of the optimum of the correspondence under the different segmented modes.With M
1=2, M
2=3 is that example (is about to 5 check blocks and is divided into 2 parts; With preceding 2 check blocks as first; With back 3 check blocks as second portion); Its 1st optional verification synchronous head sequence is " 00 11,11 11 00 ", and the corresponding synchronous head of 2 check blocks of expression first is respectively " 00 ", " 11 "; The corresponding synchronous head of 3 check blocks of second portion is respectively " 11 ", " 11 ", " 00 ".
Table 1
Table 2 has provided the piece of check block and has counted under the situation of M=6, adopts the error pattern and its corresponding check synchronous head sequence of different segmented modes.
Table 2
Table 3 has provided the piece of check block and has counted under the situation of M=7, adopts the error pattern and its corresponding check synchronous head sequence of different segmented modes.
Table 3
Table 4 has provided the piece of check block and has counted under the situation of M=8, adopts the error pattern and its corresponding check synchronous head sequence of different segmented modes.
| 2 | 6 | (12 6，14 12，16 N+M-19) | 00?11，00?11?00?00?11?11 | 00?11，11?00?11?11?00?00 | 11?00，00?11?11?00?11?00 | 11?00，00?11?00?00?11?11 |
| 3 | 5 | (12 6，14 12，16 N+M-19) | 00?11?00，11?00?00?11?11 | 00?11?00，11?00?11?11?00 | 11?00?11，00?00?11?11?00 | 11?00?11，00?11?11?00?00 |
| 4 | 4 | (12 6，14 12，16 N+M-19) | 00?00?11?11，11?00?11?00 | 00?11?00?11，11?11?00?00 | 11?00?11?00，00?00?11?11 | 11?11?00?00，00?11?00?11 |
| 5 | 3 | (12 6，14 12，16 N+M-19) | 00?00?11?11?00，11?00?11 | 00?11?00?11?11，11?00?00 | 11?00?11?00?00?00?11?11 | 11?11?00?00?11，00?11?00 |
| 6 | 2 | (12 6，14 12，16 N+M-19) | 00?00?11?11?00?11，11?00 | 00?11?00?00?11?11?11?00 | 11?00?11?11?00?00，00?11 | 11?11?00?00?11?00，00?11 |
| 7 | 1 | (12 6，14 12，16 N+M-19) | 00?00?11?11?00?11?00，11 | 00?11?00?11?11?00?00，11 | 11?00?11?00?00?11?11，00 | 11?11?00?00?11?00?11，00 |
Table 4
Table 5 has provided the piece of check block and has counted under the situation of M=9, adopts the error pattern and its corresponding check synchronous head sequence of different segmented modes.
Table 5
What deserves to be mentioned is, when N data block being carried out the FEC coding, also can carry out the FEC coding, that is to say that the data sync head of 2 bits in the data block is all participated in the FEC coding information data in the data block and data sync head.Such as the data block that via line coding back is generated is sent to line coding code word buffer memory/order module.Suppose that the desired length of FEC coded frame is 66 * N bit; Then when line coding code word buffer memory/order module receives N data block; This N data block formed a FEC coded frame, and this FEC coded frame is sent to the FEC encoder carries out the FEC coding.
Because in this execution mode, be through with data block and check block apart from one another by rearranging a fec frame, to reduce the probability of generation fec frame false sync.Therefore, how data block is carried out the FEC coding and generate check information, can't have influence on the effect of this execution mode.
In addition, in this execution mode, be that example describes with the 64B/66B line coding, in practical application, also can adopt other k/ (k+2) line coding, k is a positive integer, like the 32B/34B line coding.
Second execution mode of the present invention relates to a kind of data framing method, and this execution mode is roughly the same with first execution mode, and its difference is, in the first embodiment, is that the information data after scrambling is carried out line coding, the generation data block; And in this execution mode, be after conducting transmission line is encoded, the information data in the data block that generates is carried out scrambling again, as shown in Figure 7.This execution mode specifically is applied to data composition order and the framing mode after Ethernet media independent interface data gets into Ethernet PCS.
Specifically, as shown in Figure 7, from the information data part of two of the transmission of Ethernet media independent interface continuous Ethernet media independent interface data formation 64B/66B line codings.The length of each Ethernet media independent interface data is 32 bits.These 8 bytes of 64 bit information data D0～D7 in the data block that will behind the 64B/66B line coding, generate are then sent into scrambler and are carried out scrambling.64 bit information data S0～S7 fronts after scrambling are added on the data sync head of 2 bits that obtain in the 64B/66B line coding process.Wherein the 2nd of the data sync head the bit is significant bits.
It is the encoding block of unit that information data S0 after the scrambling～S7 constitutes with 65 bits together with significant bits.Send into the FEC encoder behind the such encoding block of N and encode Deng collecting.After coding is accomplished, output encoder piece (each encoding block is made up of the information data and the significant bits of 64 bits) and check information piece.Add the less important bit in the data sync head in the encoding block front of 65 bits, form the data block of 66 bits, add the synchronous head of 2 bits then in the check information piece front of 64 bits, form check block.Data block and check block are waited for framing.
With preceding N
1Individual data block is placed on the front of fec frame, places M then
1Individual check block is placed N again
2Individual data block and M
2Individual check block is placed N at last
pIndividual data block and M
pIndividual check block.The number of data block and check block is respectively N and M in this frame.The length of this frame is 66 * (N+M) bits.Behind this frame process code check mediation device, send out.
The 3rd execution mode of the present invention relates to a kind of data framing equipment, and is as shown in Figure 8, comprising: scrambling unit, line coding unit, coding unit, division unit and arrangement units.Scrambling unit and line coding unit communication, communicate by letter with coding unit in the line coding unit, and coding unit is communicated by letter with division unit, and division unit is communicated by letter with arrangement units.
Wherein, scrambling unit is used for original information data to be verified is carried out scrambling, and the information data after the scrambling is outputed to this line coding unit.The line coding unit is used for information data is carried out k/ (k+2) line coding (like the 64B/66B line coding), generates data block, and the data block that generates is outputed to this coding unit, and wherein k is a positive integer, comprises the data sync head in each data block.Coding unit is used for N data block encoded and obtains M (preferably M >=5) check block, wherein comprises the verification synchronous head in each check block, and data sync head and verification synchronous head are inequality.Division unit is used for this N data block is divided into X part, and this M check block is divided into Y part, N >=X >=1, and M >=Y >=1 has one at least greater than 1 among X, the Y, and the difference of the absolute value of X and Y is less than 2.Arrangement units, the data block of the each several part that is used for this division unit is divided and check block are apart from one another by rearranging a frame.
Wherein, coding unit further comprises: the FEC subelement of encoding, be used for the information data and the data sync head of data block are carried out the FEC coding, and generate the check information in M the check block; Perhaps; This FEC coding subelement is used for the information data and the significant bits in the data sync head of N data block are carried out the FEC coding; Generate the check information in M the check block, wherein significant bits is the bit that is used for indicating the type of same data block information data.
Owing to no longer all check blocks all are placed on after the data block; But check block and data block are intersected placement; Therefore can reduce the degree of correlation between the new frame that constitutes after several block of informations of a complete fec frame and this fec frame slip; When thereby conducting frame is synchronous, reduced the probability that the fec frame false sync takes place.
Need to prove, in this execution mode, earlier original information data to be verified is carried out scrambling, the information data after the scrambling is outputed to the line coding unit by scrambling unit.But in practical application; Also can carry out line coding by the line coding unit to original information data to be verified earlier; By scrambling unit the information data in the data block of this line coding unit output is carried out scrambling again, the scrambling result is outputed to this FEC coding unit.
In sum, in embodiments of the present invention, N data block encoded obtains M check block; Wherein comprise the data sync head in each data block, comprise the verification synchronous head in each check block, data sync head and verification synchronous head are inequality; N data block is divided into X part, M check block is divided into Y part, N >=X >=1; M >=Y >=1 has one at least greater than 1 among X, the Y, the difference of the absolute value of X and Y is less than 2.Then, with the data block of each several part and check block apart from one another by rearranging a frame.Owing to no longer all check blocks all are placed on after the data block; But check block and data block are intersected placement; Therefore can reduce the degree of correlation between the new frame that constitutes after several block of informations of a complete fec frame and this fec frame slip; When thereby conducting frame is synchronous, reduced the probability that the fec frame false sync takes place.
Such as; The check block number that carries out the back generation of FEC coding is 5; If these 5 check blocks all are placed on after the data block, lead to errors then synchronously that required minimum error of transmission bit number is 6, that is to say; In all synchronous heads, (comprise data sync head and verification synchronous head) as long as 6 bit generation errors of transmission are arranged, just might lead to errors synchronously.If but check block and data block are intersected placement; As these 5 check blocks are divided into 2 parts, preceding 2 check blocks as first, are arranged in back 3 check blocks after this first's check block as second portion; The a part of data block in interval between this first's check block and the second portion check block; Can know from experimental result that then the synchronous required minimum error of transmission bit number that leads to errors is 8, that is to say; In all synchronous heads, (comprising data sync head and verification synchronous head) will have 8 bit generation errors of transmission at least, just might lead to errors synchronously.
Information data in the data block that via line coding back is generated is carried out FEC coding generation check block with the significant bits in the data sync head, and this significant bits is the bit that is used for indicating the type of same data block information data.Do not participate in the FEC coding owing to be used for the synchronous partial bit of data block in this data sync head; Effectively having reduced needs the amount of information through the FEC coding protection; Make more redundant (check bit) protect to the least possible Useful Information data; Thereby obtain bigger coding gain, increased the power budget of system.And because the bit that is used for the designation data type has been carried out the FEC coding protection, bigger coding gain can improve the correct probability that the data type is judged.
Before information data to be verified is carried out line coding; Or after the conducting transmission line coding, carry out before the FEC coding information data being carried out scrambling; So that guarantee institute's transmission information to the full extent enough switchings are arranged, thereby be convenient to the clock recovery of receiving terminal.
Though through reference some preferred implementation of the present invention; The present invention is illustrated and describes; But those of ordinary skill in the art should be understood that and can do various changes to it in form with on the details, and without departing from the spirit and scope of the present invention.
Claims (15)
1. a data framing method is characterized in that, may further comprise the steps:
N data block encoded obtains M check block, wherein comprises the data sync head in each said data block, comprises the verification synchronous head in each said check block, and said data sync head and said verification synchronous head are inequality;
A said N data block is divided into X part, a said M check block is divided into Y part, N >=X >=1, M >=Y >=1 has one at least greater than 1 among X, the Y, and the difference of the absolute value of X and Y is less than 2;
With the data block of each several part and check block apart from one another by rearranging a frame.
2. data framing method according to claim 1 is characterized in that, obtains comprising following substep in the step of M check block said N data block encoded:
Information data in the said data block and data sync head are carried out forward error correction coding, generate the check information in the said M check block; Perhaps,
Significant bits in information data in the said data block and the data sync head is carried out forward error correction coding, generates the check information in the said M check block; Said significant bits is the bit that is used for indicating the type of same data block information data.
3. data framing method according to claim 2 is characterized in that, before said step of carrying out forward error correction coding, comprises following substep:
Original information data to be verified is carried out line coding, generate said data block.
4. data framing method according to claim 3 is characterized in that,
Before the step of carrying out said line coding, further comprising the steps of: that said original information data is carried out scrambling; In said step of original information data to be verified being carried out line coding, the original information data after the scrambling is carried out line coding; Perhaps,
Between the step of said line coding and the step of said forward error correction coding, further comprising the steps of:
Information data in the said data block of via line coding back generation is carried out scrambling.
5. according to claim 3 or 4 described data framing methods, it is characterized in that said M >=5;
In said step of carrying out line coding, information data to be verified is carried out k/ (k+2) line coding, k is a positive integer.
6. data framing method according to claim 5 is characterized in that, said M=5, said Y=2, said X=2;
Said 5 check blocks are being divided in the step of 2 parts, preceding 1 check block as first, is being arranged in back 4 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 11,00; 00,11,00}, { 11,00,11; 00,00}, { 00,11,11,00; 11} or 00,11,00,11,11};
Perhaps, said 5 check blocks are being divided in the step of 2 parts, preceding 2 check blocks as first, are being arranged in back 3 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 11,11,11,00}, { 11,00,00; 00,11}, { 00,00,11,00; 11} or 11,11,00,11,00};
Perhaps, said 5 check blocks are being divided in the step of 2 parts, preceding 3 check blocks as first, are being arranged in back 2 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 11,11,11,00}, { 11,00,00; 00,11}, { 11,00,11,00; 00} or 00,11,00,11,11};
Perhaps, said 5 check blocks are being divided in the step of 2 parts, preceding 4 check blocks as first, are being arranged in back 1 check block after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block; The verification synchronous head of each check block from front to back be followed successively by 11,11,00,11,00}, { 11; 00,11,11,00}, { 00; 11,00,00,11} or { 00; 00,11,00,11}.
7. data framing method according to claim 5 is characterized in that, said M=6, said Y=2, said X=2;
Said 6 check blocks are being divided in the step of 2 parts, preceding 1 check block as first, is being arranged in back 5 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 11,11,00,11,00}, { 00; 11,00,11,11,00}, { 11; 00,11,11,00,00} or { 11; 11,00,11,00,00};
Perhaps, said 6 check blocks are being divided in the step of 2 parts, preceding 2 check blocks as first, are being arranged in back 4 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11}, { 00; 11,00,11,11,00}, { 11; 00,11,00,00,11} or { 11; 11,00,11,00,00};
Perhaps, said 6 check blocks are being divided in the step of 2 parts, preceding 3 check blocks as first, are being arranged in back 3 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11}, { 00; 11,00,11,11,00}, { 11; 00,11,00,00,11} or { 11; 11,00,00,11,00};
Perhaps, said 6 check blocks are being divided in the step of 2 parts, preceding 4 check blocks as first, are being arranged in back 2 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,00,11,11}, { 00; 11,11,00,11,00}, { 11; 00,11,11,00,00} or { 11; 11,00,11,00,00};
Perhaps, said 6 check blocks are being divided in the step of 2 parts, preceding 5 check blocks as first, are being arranged in back 1 check block after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11}, { 00; 11,11,00,11,00}, { 11; 00,11,11,00,00} or { 11; 11,00,11,00,00}.
8. data framing method according to claim 5 is characterized in that, said M=7, said Y=2, said X=2;
Said 7 check blocks are being divided in the step of 2 parts, preceding 1 check block as first, is being arranged in back 6 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00; 11,11,00,11,00}, { 00,11; 00,11,11,00,00}, { 11,00; 11,00,00,11,11} or { 11,11; 00,00,11,00,11};
Perhaps, said 7 check blocks are being divided in the step of 2 parts, preceding 2 check blocks as first, are being arranged in back 5 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11,00}, { 00; 11,00,11,11,00,00}, { 11; 00,11,00,00,11,11} or { 11; 11,00,00,11,00,11};
Perhaps, said 7 check blocks are being divided in the step of 2 parts, preceding 3 check blocks as first, are being arranged in back 4 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11,00}, { 00; 11,00,11,11,00,00}, { 11; 00,11,00,00,11,11} or { 11; 11,00,00,11,00,11};
Perhaps, said 7 check blocks are being divided in the step of 2 parts, preceding 4 check blocks as first, are being arranged in back 3 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11,00}, { 00; 11,00,11,11,00,00}, { 11; 00,11,00,00,11,11} or { 11; 11,00,00,11,00,11};
Perhaps, said 7 check blocks are being divided in the step of 2 parts, preceding 5 check blocks as first, are being arranged in back 2 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11,00}, { 00; 11,00,11,11,00,00}, { 11; 00,11,00,00,11,11} or { 11; 11,00,00,11,00,11};
Perhaps, said 7 check blocks are being divided in the step of 2 parts, preceding 6 check blocks as first, are being arranged in back 1 check block after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00; 00,11,11,00,11,00}, { 00; 11,00,11,11,00,00}, { 11; 00,11,00,00,11,11} or { 11; 11,00,00,11,00,11}.
9. data framing method according to claim 5 is characterized in that, said M=8, said Y=2, said X=2;
Said 8 check blocks are being divided in the step of 2 parts, preceding 1 check block as first, is being arranged in back 7 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,11,00; 11,00,00,11,11}, { 00,11,11; 00,00,11,00,11}, { 11,00,00; 11,11,00,11,00} or { 11,00; 11,00,11,11,00,00};
Perhaps, said 8 check blocks are being divided in the step of 2 parts, preceding 2 check blocks as first, are being arranged in back 6 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,11; 00,11,00,00,11,11}, { 00,11; 11,00,11,11,00,00}, { 11,00; 00,11,11,00,11,00} or { 11,00; 00,11,00,00,11,11};
Perhaps, said 8 check blocks are being divided in the step of 2 parts, preceding 3 check blocks as first, are being arranged in back 5 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,11; 00,11,00,00,11,11}, { 00,11; 00,11,00,11,11,00}, { 11,00; 11,00,00,11,11,00} or { 11,00; 11,00,11,11,00,00};
Perhaps, said 8 check blocks are being divided in the step of 2 parts, preceding 4 check blocks as first, are being arranged in back 4 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00; 11,11,11,00,11,00}, { 00,11; 00,11,11,11,00,00}, { 11,00; 11,00,00,00,11,11} or { 11,11; 00,00,00,11,00,11};
Perhaps, said 8 check blocks are being divided in the step of 2 parts, preceding 5 check blocks as first, are being arranged in back 3 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00; 11,11,00,11,00,11}, { 00,11; 00,11,11,11,00,00}, { 11,00; 11,00,00,00,11,11} or { 11,11; 00,00,11,00,11,00};
Perhaps, said 8 check blocks are being divided in the step of 2 parts, preceding 6 check blocks as first, are being arranged in back 2 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00; 11,11,00,11,11,00}, { 00,11; 00,00,11,11,11,00}, { 11,00; 11,11,00,00,00,11} or { 11,11; 00,00,11,00,00,11};
Perhaps, said 8 check blocks are being divided in the step of 2 parts, preceding 7 check blocks as first, are being arranged in back 1 check block after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00; 11,11,00,11,00,11}, { 00,11; 00,11,11,00,00,11}, { 11,00; 11,00,00,11,11,00} or { 11,11; 00,00,11,00,11,00}.
10. data framing method according to claim 5 is characterized in that, said M=9, said Y=2, said X=2;
Said 9 check blocks are being divided in the step of 2 parts, preceding 1 check block as first, is being arranged in back 8 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00; 11,00,00,11,11,11; 00}, { 00,00,11,11,11,00; 00,11,00}, { 11,11,00,11; 00,11,11,00,00} or { 11,11 00 00 11 11 00 11 00};
Perhaps, said 9 check blocks are being divided in the step of 2 parts, preceding 2 check blocks as first, are being arranged in back 7 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,11,11; 00,11,00,00,11,11}, { 00,11,11; 11,00,00,11,00,11}, { 11,00,00; 00,11,11,00,11,00} or { 11,00; 00,11,00,11,11,00,00};
Perhaps, said 9 check blocks are being divided in the step of 2 parts, preceding 3 check blocks as first, are being arranged in back 6 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00,11; 00,11,11,00,11,00}, { 00,11,00; 11,00,00,11,11,00}, { 11,00,11; 11,00,00,11,11,00} or { 11,00; 00,00,11,00,11,11,00};
Perhaps, said 9 check blocks are being divided in the step of 2 parts, preceding 4 check blocks as first, are being arranged in back 5 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,11,00; 11,00,11,11,00,00}, { 00,11,00; 11,11,11,00,00,11}, { 11,00,11; 00,00,00,11,11,00} or { 11,00; 11,00,11,00,00,11,11};
Perhaps, said 9 check blocks are being divided in the step of 2 parts, preceding 5 check blocks as first, are being arranged in back 4 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00,11; 11,00,11,00,11,00}, { 00,11,11; 00,00,00,11,00,11}, { 11,00,00; 11,11,11,00,11,00} or { 11,11; 00,00,11,00,11,00,11};
Perhaps, said 9 check blocks are being divided in the step of 2 parts, preceding 6 check blocks as first, are being arranged in back 3 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,11,00; 11,11,00,11,00,00}, { 00,11,11; 00,00,11,00,11,00}, { 11,00,00; 11,00,11,11,11,00} or { 11,11; 00,00,11,00,11,00,11};
Perhaps, said 9 check blocks are being divided in the step of 2 parts, preceding 7 check blocks as first, are being arranged in back 2 check blocks after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,00,11; 11,00,11,00,00,11}, { 00,11,00; 11,11,00,00,00,11}, { 11,00,11; 00,00,11,11,11,00} or { 11,11; 00,00,11,00,11,11,00};
Perhaps, said 9 check blocks are being divided in the step of 2 parts, preceding 8 check blocks as first, are being arranged in back 1 check block after this first's check block as second portion, the back a part of data block in the said data block at interval between this first's check block and the second portion check block, the verification synchronous head of each check block from front to back is followed successively by { 00,11,00; 00,11,11,11,00,00}, { 00,11,11; 11,00,00,11,00,00}, { 11,00,00; 11,11,00,11,00,00} or { 11,11; 00,00,11,00,11,00,00}.
11. a data framing equipment is characterized in that, comprising:
Coding unit, being used for N data block encoded obtains M check block, wherein comprises the data sync head in each said data block, comprises the verification synchronous head in each said check block, and said data sync head and said verification synchronous head are inequality;
Division unit is used for a said N data block is divided into X part, and a said M check block is divided into Y part, N >=X >=1, and M >=Y >=1 has one at least greater than 1 among X, the Y, and the difference of the absolute value of X and Y is less than 2;
Arrangement units, the data block of the each several part that is used for said division unit is divided and check block are apart from one another by rearranging a frame.
12. data framing equipment according to claim 12 is characterized in that, said coding unit further comprises:
The forward error correction coding subelement is used for the information data and the data sync head of said data block are carried out forward error correction coding, generates the check information in the said M check block; Perhaps,
Said forward error correction coding subelement is used for the information data of said data block and the significant bits in the data sync head are carried out forward error correction coding, generates the check information in the said M check block; Said significant bits is the bit that is used for indicating the type of same data block information data;
Said forward error correction coding subelement is communicated by letter with said division unit.
13. data framing equipment according to claim 12 is characterized in that, also comprises:
The line coding unit is used for original information data to be verified is carried out line coding, generates said data block, and the said data block that generates is outputed to said forward error correction coding subelement.
14. data framing equipment according to claim 13 is characterized in that, also comprises:
Scrambling unit is used for said original information data is carried out scrambling, and the original information data after the scrambling is outputed to said line coding unit; Perhaps,
Said scrambling unit is used for the information data of the data block of said line coding unit output is carried out scrambling, and the scrambling result is outputed to said forward error correction coding subelement.
15. according to claim 13 or 14 described data framing equipment, it is characterized in that, said M >=5, said line coding unit carries out k/ (k+2) line coding to information data to be verified, and k is a positive integer.
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| CN2007101295772A CN101345745B (en) | 2007-07-09 | 2007-07-09 | Data framing method and equipment thereof |
| PCT/CN2008/071449 WO2009006818A1 (en) | 2007-07-09 | 2008-06-26 | Data frame forming method and equipment |
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| JP5509438B2 (en) * | 2010-03-03 | 2014-06-04 | 株式会社日立製作所 | Data transfer device and data transfer system |
| CN102025448B (en) * | 2010-11-18 | 2013-11-06 | 华为技术有限公司 | Common public radio interface service transmitting/receiving method and device |
| CN102480333B (en) * | 2010-11-22 | 2014-08-13 | 华为技术有限公司 | Line coding method as well as synchronous processing method and device of coded data block |
| ES2673571T3 (en) | 2013-01-04 | 2018-06-22 | Huawei Technologies Co., Ltd. | Method to process data on Ethernet, physical layer integrated circuit and Ethernet device |
| CN106254054B (en) * | 2015-06-19 | 2019-11-15 | 北京自动化控制设备研究所 | A kind of frame structure design method can be avoided false synchronization |
| CN110324110B (en) * | 2018-03-30 | 2020-10-27 | 华为技术有限公司 | Communication method, communication device and storage medium |
| CN110391871B (en) * | 2018-04-19 | 2021-11-19 | 华为技术有限公司 | Data coding and decoding method and device, OLT, ONU and PON system |
| CN111984184B (en) * | 2019-05-23 | 2022-05-17 | 浙江宇视科技有限公司 | Data management method and device for solid state disk, storage medium and electronic equipment |
| CN113381836B (en) * | 2020-02-25 | 2023-03-24 | 华为技术有限公司 | Line coding method and device |
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| CN101345745A (en) | 2009-01-14 |
| WO2009006818A1 (en) | 2009-01-15 |
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