CN101344899B - Simulation test method and system of on-chip system - Google Patents
Simulation test method and system of on-chip system Download PDFInfo
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Abstract
The invention is applicable to the field of integrated circuits and provides a system-on-chip simulation testing method and a simulation testing system. The simulation testing method comprises the steps as follows: the testing level classification information of an SoC chip input from the exterior is received; model transmission information among all testing levels input from the exterior is received; the information of each testing level is obtained by analyzing the testing level classification information; and corresponding testing codes are generated according to the model transmission information and are operated via a testing tool so as to test the obtained testing level one after another. In the invention, the testing levels are classified according to SoC chip structure and application software information; the testing codes are generated according to the testing goal of each testing level and the models transmitted by other levels, and the testing tool is used for carrying out function testing so that application software development is organically integrated into the stimulation testing phases of the SoC chip, therefore, the matching situation of the SoC chip structure and the application software can be timely confirmed.
Description
Technical field
The invention belongs to integrated circuit fields, relate in particular to a kind of emulation test method and emulation test system of SOC (system on a chip).
Background technology
Along with infotech and development of semiconductor, the miniaturization day by day of consumer electronics products such as portable terminal, function is complicated day by day, the interface of supporting is more and more, power consumption is also in continuous reduction, and the principal element that promotes this variation is exactly SOC (system on a chip) (System on a Chip, SoC) development of technology.SoC refers to an integrated complete system on single chip, current chip fabrication techniques is enough to integrated a plurality of processor cores, controller and accelerating engine etc. on the chip piece of nail cover size, and the application of its support is enough to compare with the logical personal computer of a Daepori.More than the function that the SoC chip is finished, cause chip internal structure very complicated, the application software of supporting chip is also extremely numerous and diverse, tackles these challenges and be unable to do without effective method of testing.
Emulation testing is an important link of SoC chip testing, and Fig. 1 is the structure principle chart of typical emulation test system, and emulation test system utilizes custom-designed software (system testing unit) and hardware system (emulation board) emulation chip logic.Because the SoC chip logic is realized on programmable logic chip, as field-programmable logic array (Field Programmable Gate Array, FPGA), emulation testing can be surpassing a plurality of orders of magnitude of software simulator, even show the behavior and the function of objective chip near the speed of final chip.Emulation testing be unable to do without a series of benchmarks, and these programs are developed according to the chip specification, are used for the matching degree of proofing chip function.
Application software is followed certain model and standard usually when exploitation, for example can call the C built-in function with the application program of C language development, these built-in functions provide the frequent function of using of program or have encapsulated the system call of operating system, these functions and interface have definite semanteme and call standard, and application program is used them according to certain pattern.And in the existing emulation testing framework, the exploitation of benchmark is carried out with reference to the specification of chip, generally emphasize the function that chip is finished, too much do not pay close attention to the inherent model and the standard (for example level of software, calling interface and data structure) of application software, so just cause benchmark and final application software in structure and external manifestation (as code and organizational form thereof), to greatly differ from each other, make benchmark can only serve the chip emulation test and can not be used for final applied software development.In addition, although can verify the function of SoC by benchmark, but these benchmarks are not equal to the finally application software of actual motion in the SoC application scheme after all, if the benchmark program program can not cover the principal character of application software, the unmatched situation of actual demand that SoC system architecture and functions of modules and application scheme then may occur, this do not match have only to middle and later periods of application scheme exploitation just find, chip design this moment finalizes the design almost, variable cost is bigger, has prolonged the Time To Market of chip and application scheme thereof virtually.
In a word, the design of SoC chip more and more has application-oriented feature, be new application and development SoC chip, rather than will become a kind of main flow for the new application of SoC chip development, and existing SoC emulation test method may cause the actual demand of SoC system architecture and functions of modules and application scheme not to be complementary.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of method of testing of SOC (system on a chip), is intended to solve the problem that existing SoC emulation test method may cause the actual demand of SoC system architecture and functions of modules and application scheme not to be complementary.
The embodiment of the invention is achieved in that a kind of emulation test method of SOC (system on a chip), and described emulation test method may further comprise the steps:
Receive the test level division information of the SoC chip of outside input; Described test level division information includes the structural information of SoC chip and the structural information of application software;
Receive the Model Transfer information between outside each test level of importing; Described Model Transfer packets of information contains the Model Transfer relation information between each test level, and the Model Transfer content information;
Resolve described test level division information, obtain each test hierarchical information, if current test level does not come from the model that other levels are transmitted, the structural information of then arbitrarily choosing application software generates the test code of this level and by the testing tool operation, one by one each test layer level of obtaining is tested; Come from the model that other levels are transmitted if current test level has, then generate corresponding test code and, one by one each test layer level of obtaining is tested by the testing tool operation according to described Model Transfer information.
Another purpose of the embodiment of the invention is to provide a kind of emulation test system of SOC (system on a chip), and described emulation test system comprises system testing unit and programmable logic device (PLD) emulation board;
Described system testing unit comprises:
Test level division information receiver module, be used to receive the test level division information of the outside SoC chip of importing; The test level division information of the SoC chip that described test level division information receiver module receives includes the structural information of SoC chip and the structural information of application software;
The Model Transfer information receiving module is used to receive the Model Transfer information between outside each test level of importing; The Model Transfer packets of information that described Model Transfer information receiving module receives contains the Model Transfer relation information between each test level, and the Model Transfer content information; And
The test code generation module, be used to resolve the test level division information that described test level division information receiver module receives and obtain each test hierarchical information, if current test level does not come from the model that other levels are transmitted, the structural information that described test code generation module is arbitrarily chosen application software generates the test code of this level; Come from the model that other levels are transmitted if current test level has, described test code generation module generates corresponding test code according to described Model Transfer information;
Described programmable logic device (PLD) emulation board is used to move the test code that described test code generation module generates.
In the embodiment of the invention, divide the test level according to SoC chip structure and application software information, the model that transmits according to test target and other levels of each test level generates test code then, the use test instrument moves this test code to carry out functional test, thereby make applied software development organically incorporate the emulation testing stage of SoC chip, benchmark in the emulation testing can easily or be directly used in the applied software development, improve the reusability of testing software, can in time confirm the match condition of SoC chip structure and application software simultaneously.
Description of drawings
Fig. 1 is the structure principle chart of typical emulation test system;
Fig. 2 is the realization flow figure of the emulation test method of the SOC (system on a chip) that provides of the embodiment of the invention;
Fig. 3 is the frame principles figure of 4 layers of test structure providing of the embodiment of the invention;
Fig. 4 is the structure principle chart of a SoC chip that provides of the embodiment of the invention;
Fig. 5 is the level synoptic diagram of the application software of SoC chip shown in Figure 4;
Fig. 6 is that the test level of SoC chip shown in Figure 4 is divided synoptic diagram;
Fig. 7 is that the Model Transfer of test layer inter-stage shown in Figure 6 concerns synoptic diagram;
Fig. 8 is the structural representation of the FPGA emulation board shown in Figure 4 that provides of the embodiment of the invention;
Fig. 9 is the single system synoptic diagram to the SRAM of the processor layer level is tested among Fig. 6 time visit that the embodiment of the invention provides;
Figure 10 is the single system synoptic diagram to the SDRAM/DDR of the processor layer level is tested among Fig. 6 time visit that the embodiment of the invention provides;
Figure 11 is the single system synoptic diagram of the support serial ports of Fig. 6 middle controller level being tested time visit that provides of the embodiment of the invention;
Figure 12 is the minimum system synoptic diagram of the support operating system of visit when the simple application level is tested among Fig. 6 of providing of the embodiment of the invention;
Figure 13 is the structure principle chart of the emulation test system of the SOC (system on a chip) that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In the embodiment of the invention, divide the test level according to SoC chip structure and application software information, the model that transmits according to test target and other levels of each test level generates test code then, and the use test instrument carries out functional test.
Fig. 2 shows the realization flow of the emulation test method of the SOC (system on a chip) that the embodiment of the invention provides, and details are as follows:
In step S201, receive the test level division information of the SoC chip of outside input, wherein test the level division information and include the structural information of SoC chip and the structural information of application software.
In the embodiment of the invention, whole test process is carried out according to a kind of orderly mode, be divided into of the structure realization checking of a plurality of test phases to SoC chip and application software, the branch that has the height of level between the test phase, the low-level test phase is supported the high-level test phase, and each test phase has clear and definite test target.
At first want the structure composition of clear and definite SoC chip and the layer of structure of application software, promptly determine the main function components of SoC chip and interconnect situation, so that understand the concrete situation that application software is used SoC chip functions parts intuitively, and then reach the purpose that applied software development is organically incorporated the emulation testing stage of SoC chip.Consider that the SoC chip finally will be application service, so the embodiment of the invention pays close attention to is the application software that will move on the application scheme and the structure of application software thereof.Application software comprises application program, function library, operating system and boot, and the software systems that are made of these softwares.The program development language and the developing instrument of application software use are also very important in addition, the emulation testing program adopts development language and the developing instrument identical with application software in the present embodiment, to improve the reusability of software, C, C++ can be chosen in the program development language, assembly language also can be used in place in necessity, and the particular type of assembly language is by the processor decision of SoC chip.Application software is used higher level lanquage usually as far as possible, utilizes compiler, assembler and linker to generate two machine-processed executable codes then.Application software has immanent structure, the structural information of application software comprises information such as software level, actuating logic, algorithm model, calling interface and data structure in the present embodiment, wherein calling interface information comprises semanteme, input parameter and form thereof, output parameter and form thereof and the information of returning and the form thereof of interface, and data structure information then comprises the type and the constituted mode of data structure.
In step S202, receive the Model Transfer information between outside each test level of importing, wherein, the Model Transfer packets of information contains the Model Transfer relation information between each test level, and the Model Transfer content information.
In the embodiment of the invention, Model Transfer is carried out to the low-level test phase by the high-level test phase, at first want clear and definite which test level to need TRANSFER MODEL, which test level need receive the content of the model of the model of transmission and transmission, the content of Model Transfer comes from the structural information of the application software that receives among the step S201, promptly comprises information such as software level, actuating logic, algorithm model, calling interface and data structure.
In step S203, resolve test level division information, obtain each test hierarchical information, generate corresponding test code and, one by one each test layer level of obtaining is tested according to Model Transfer information by the testing tool operation.
At first determine required testing tool, be each test level and determine that this test phase carries out the required device of test activity, equipment and related software with the user.Device or equipment comprise the programmable logic device (PLD) that can realize the SoC chip structure, common input-output device, as serial ports, network interface card, USB (Universal Serial BUS, USB (universal serial bus)), LCD (Liquid Crystal Display, LCD), JTAG (Joint Test Action Group, joint test behavior tissue) etc., and by these devices and equipment and engage the system that other necessary device is built.In use test device and equipment, corresponding software is essential, this software is normally operated in can be to proving installation or equipment sending data on the main frame, perhaps from device or equipment receiving data, as the serial port terminal of host side, debugging software, network tool commonly used and USB client-access software etc. based on JTAG.Testing tool should satisfy the test target of establishing among the step S201, and the model that transmits among the support step S202.
Next utilizes developing instrument, according to the test target of each test level and in conjunction with the model that passes over by high-level, generate corresponding executable code, in testing tool, move this code and detect operation result, analyze the result of acquisition and the difference of expected results then, judge whether to cause according to difference,, repeat whole test process then if then revise chip structure and application software architecture by chip structure and application software architecture.
In the embodiment of the invention, if current test level does not come from the model that other levels are transmitted, then the test code of this level can arbitrarily be chosen the structural information of application software, as software level, execution flow process, algorithm model, function interface and data structure etc., otherwise to be consistent with the model of high-level transmission.In addition, will consider program development language and developing instrument definite among the step S201 when realizing generating code, test code also will be considered the support that testing tool can provide.
Fig. 3 is the frame principles that example shows the emulation testing of the SOC (system on a chip) that the embodiment of the invention provides with 4 layers of test structure, wherein high-level can be to the low-level TRANSFER MODEL, level 4 and level 3 are respectively to level 2 TRANSFER MODEL among Fig. 3, and level 2 is to level 1 TRANSFER MODEL.The Model Transfer direction is pointed by " model " arrow, follows by the direction of high-level to low-level." test " arrow shows the actual direction of carrying out of test, promptly from the low-level to the high-level.Have supporting relation between level, low-level supports high-level, supports level 2 as level among Fig. 31, and level 2 supports level 3, and the rest may be inferred; Whether low-level supports high-level is guaranteed by the test result of each level.
Those having ordinary skill in the art will appreciate that, all or part of step in realization the foregoing description method can instruct relevant hardware to finish by program, this program can be stored in the computer read/write memory medium, random access memory), disk, CD etc. as ROM/RAM (Read-Only Memory: ROM (read-only memory), random access memory:.
Easier to understand and implement for the emulation test method that makes the SOC (system on a chip) that the embodiment of the invention provides, below the high-performance SoC chip that uses with a consumer electronics product (as MP4) set forth the specific implementation process of this method as example, the structural principle of this SoC chip is as shown in Figure 4.
The 1st step, the test level division information of the SoC chip of the outside input of reception.
At first determine SoC chip structure and intended application scheme: with reference to Fig. 4, microprocessor adopts microprocessor (the Microprocessor without Interlocked PipedStages of a 32 no inner interlocking pipelining-stages, MIPS) nuclear 401, have memory management unit (Memory Management Unit, MMU).Processor and each function module circuit adopt standard A MBA (Advanced Microcontroller BusArchitecture, advanced microcontroller bus architecture) bus to connect.The AMBA bus is made of AHB (Advanced High-performance Bus, Advanced High-performance Bus) bus and APB (AdvancedPeripheral Bus) bus.Ahb bus is a kind of high-speed bus, MIPS nuclear 401, bus arbiter 402, video accelerator 410, DMA (Direct Memory Access, direct memory access (DMA)) controller 411, lcd controller 412, Audio Controller 413, USB414, MMC/SD controller 415, SDRAM/DDR controller 416, AHB/APB bridge 406, NAND Flash controller 416 and SRAM interface 403 (SRAM IF) etc. are arranged on it.The APB bus is a kind of low speed bus, and interruptable controller 409, timer 408 and UART407 etc. are arranged on it.Ahb bus and APB bus are carried out bridge joint by the AHB/APB bridge.SRAM interface 403 can connect network interface card 417 (Lan), SRAM 404 and Nor Flash (or/no type flash memory) 418.
Application scheme based on this kind of SoC requires to support multiple audio frequency and video form, supports common memory device.Operating system is chosen Linux, boot U-boot, and audio/video player occurs with the form of the application program on the Linux.Voice ﹠ Video software adopts the C language development, just as the application program on the common PC, can freely call various C built-in functions, and visit is connected the equipment access interface that the equipment on the SoC then provides by means of operating system if desired.The driving of equipment is finished by the device driver under the Linux.Audio-video document is transferred to the (SuSE) Linux OS management with the form of file, and C built-in function file access primitive is followed in the visit of file.Linux kernel is by boot U-boot guiding, and its effect is that the kernel that will be kept on nonvolatile memory such as the Flash copies on interior cun SDRAM or the DDR.Developing instrument is based on gcc.
After the structure of having analyzed application software, the whole DASE on the SoC can be divided into level shown in Figure 5.Boot be chip power up or restart after the program that at first will carry out, chip is carried out some Preliminary detection and setting, the load operation system jumps to the inlet of kernel then to internal memory from the non-volatile memory device.The SoC chip is supported the large number quipments interface, correspondingly in operating system device drives will be arranged, and the device drives of Linux has own specific model.Usually need revise the code of hardware relevant portion when linux kernel is supported a SoC newly developed, existing kernel is supported multiple processor and structure, has therefore formed own model, and is also necessary wherein adaptive to the support of SoC.Be built-in function on the operating system, such as C storehouse, shape library etc., the system call that specific function or encapsulation operation system are provided is to application program.Application program occupies the superiors, is that the user directly can see or operate.
Secondly divide test level: on the structure of chip, processor core is this SoC " heart " and bus is exactly " collaterals of human ".All software all will be carried out on processor, therefore is that processor is divided a level separately.Boot and Linux driver need use the controller on the SoC, can work so be necessary to guarantee single controller, so just mark off a controller level.But boot and Linux driver be in when work, again may a plurality of controller collaborative works, therefore introduce the application level of a simplification.Linux kernel has the software configuration of oneself, and the structure of SoC should be mated the structure of linux kernel, therefore divides an operating system level separately.For safety, application program is direct control hardware not generally, but undertaken by the interface that built-in function provides, and some built-in function belongs to pure software function, and some then uses hardware indirectly by operating system, therefore built-in function is divided into a level separately.So just mark off 6 levels, specifically see Fig. 6.Briefly introduce the target of each level below.
The maximum attention point of processor level is to guarantee that the von Neumann computation model can operate as normal, the von Neumann computation model thinks that instruction is kept on the memory device just as data, the instruction fetch of processor order is carried out, if the address of next bar instruction has clearly been indicated in present instruction, then carry out from the instruction fetch of new address.The von Neumann computation model is that all application software are carried out the abstract of mechanism.Here to guarantee MIPS processor core correctly access memory and execution command exactly.
The controller level guarantees that each function module circuit of SoC can finish the function of appointment in the specification, mainly pays close attention to the function of single controller here.Picture UART (Universal AsynchronousReceiver/Transmitter, universal asynchronous reception/dispensing device), NAND FLASH (with non-type flash memory), USB and SD/MMC controller etc. all must be tested.
Simplify the software that application level realizes having certain application characteristic, this software is followed certain actuating logic and algorithm model, but different with application program on the final operating system, the simplification that has embodied a kind of function and realized.The software of this level can directly be coordinated a plurality of functional modules of chip, externally shows certain functional.For example boot is exactly typical case's representative of this level.
The operating system level guarantees that operating system can normal operation, and just various functions such as the characteristics such as process scheduling, time management, memory management and device drives supported of operating system can normal operation.Here operating system is chosen Linux, therefore will guarantee that Linux can normally be transplanted on the SoC, and just this SoC supports the operation of Linux.
The built-in function level will guarantee that those built-in functions that application program expectation is called all can realize in the system based on the SoC chip.These built-in functions have definite semanteme, and input parameter and rreturn value all have clear and definite regulation.
The application program level is towards the user of direct use application scheme, need guarantee that application program meets user's quality and functional requirement, and the user can frequently not meet with abnormal conditions such as " deadlocks " when using these softwares.For example video jukebox software declares that for it situation interrupted or that can not decode should not appear in form easily that support when playing.
In the 2nd step, receive the Model Transfer information between outside each test level of importing.
After clear and definite test level, to know that now which level answers TRANSFER MODEL, which level will be accepted model, and the content of the model that transmits.Fig. 7 has illustrated the Model Transfer between level to concern.
1. operating system level---＞application level simplified
Operating system is very complicated software systems, when going up the transplanting (SuSE) Linux OS to a newly-designed SoC, how is distinguishing linux kernel operation failure to cause owing to the bug patch of kernel code or by the chip self-defect? when being the SoC chip development software of maturation, the software developer generally need not suspect chip defect, but when developing new SoC for the appointment application scheme, in order to shorten Time To Market, SoC chip development and application scheme exploitation weave in, in order to relax the problem that the complicated software system mistake is difficult to locate, therefore be necessary the Linux moving model is delivered to and simplify application level and realize and verify.
Linux kernel supports the multi-process timesharing to share CPU.Process may trigger unusual when carrying out, external unit also may produce interruption.When unusual and interruption took place, process entered kernel state, interrupts or abnormality processing, and the kernel decision is the new process execution of scheduling or recovers previous process after disposing.In order to realize timesharing mechanism, kernel is provided with a timer, and timer produces periodic interruptions, and for example per 1 millisecond or 10 milliseconds produces a timer interruption, be called a ticktock in kernel.Equipment also can produce interruption, such as network interface card, when receiving a packet or having sent a packet, produces and interrupts.Device driver can be registered the break in service function to kernel, and equipment is had no progeny in producing, and kernel can call the break in service function of previous registration.In view of the above, the operating system level is simplified computation model to simplifying the application level transmission such as the next one, comprise that two are calculated main line, article one, be processor initialization, device initialize, enter infinite loop then, can carry out any computing function in the circulation, an other main line is to handle various interruptions or unusual, after interrupting or taking place unusually, processor enters and interrupts or unusual inlet, carries out corresponding service function.The distribution of linux kernel the inside interrupt resources, discharge, forbid and enable etc. all has definite interface, distributes as interrupt resources and adopts following function interface:
int?request_irq(unsigned?int?irq，irqreturn_t(*handler)(int，void*，struct?pt_regs*)，unsigned?long?irq_flags，const?char*devname，void*dev_id)
If these Model Transfer can be realized and test that to simplifying application level transplanting kernel in the operating system level so will be simply with much quick.
2. application program level---＞application level simplified
Operate in the application program on the Linux, although itself and other process is shared computational resource, the virtual sensation of monopolizing computational resource is arranged but, it is absorbed in oneself execution flow process and algorithm model, and operating system is distributed computational resource pellucidly between a plurality of processes.Operating system also can physically be removed, and simplifies the program of application level operation like this and just monopolizes the total system resource truly.There is no need all models of application program level all are delivered to the simplification application level, only extract the structure that can reflect the application program Core Feature here.
3. built-in function level---＞controller level
The built-in function layer provides the specific primitive of access means, for example application program is kept at file on the MMC by the file access interface accessing, after opening file, position with the visit of file pointer setting data, read then or write operation, the operation on these upper stratas finally can be mapped as the simple operations one by one that the MMC controller is carried out.More simple example PC goes up and calls built-in function printf () with the application program regular meeting of C language development, the character string of display formatization in standard output, and UART can serve as standard output.The controller level can realize printf () model, so just can print significant information, the function of also having tested serial ports simultaneously easily on serial ports.
The 3rd step in conjunction with the structural information by the model of high-level transmission or the application software chosen, generated corresponding code and moves by testing tool, tested.
At first to determine testing tool.Engage the target that each test level will be reached, the testing tool of selecting for use here comprises a FPGA emulation board, supports BDI, BDI debugging software, serial port terminal and the network protocol software etc. of jtag interface.
Fig. 8 shows the general configuration of FPGA emulation board, and fpga chip, Nor Flash 802, DDR/SDRAM 803, card slot 804, power supply 805, network interface card 806, serial ports 807, wire jumper 808, Reset button 809, jtag interface 810 and keyboard 811 etc. are arranged on the plate.Plank and PERCOM peripheral communication are mainly undertaken by serial ports 807, network interface card 806 and jtag interface 810.Serial ports 807 is a kind of simply and easily input-output device, and controller function is simple, and its logical circuit is very mature and stable, all support serial ports on nearly all PC, the PC end software of a lot of support serial ports is arranged, can show the data that the serial ports end is received, can also send data to serial ports.Network interface card 806 transmission speeds are fast, can reach 10Mb/s even higher, and serial ports 807 on the FPGA plate also with regard to tens kb/s.Jtag interface 810 is used for downloading to bare machine, cooperates debugging acid BDI, can observe register and access memory.Wire jumper 808 is used to select the SRAM startup from fpga chip 801 or the Nor FLASH outside the sheet starts.Capacity can not be very big on FPGA for SRAM, generally with regard to several k or tens k byte-sized.What Nor Flash was common has 2,000,000, and perhaps 4,000,000, can place more complicated program.Can support whole application software on the FPAG emulation board, as the testing tool of each test grades.
Secondly test along the nominative testing direction.According to the test target of each level and in conjunction with the model that passes over by high-level, realize corresponding test code.When realizing, code to consider definite program development language and developing instrument in the 1st step.If a level does not come from the model that high-level is transmitted, then the test code of this level can arbitrarily be chosen the software level, carry out flow process, algorithm model, function interface and data structure etc., otherwise will be consistent with the model of high-level transmission.
1. processor level.Instruction is carried out by MIPS processor 401 nuclears and is finished among the SoC, and instruction then will be kept among SRAM or the SDRAM/DDR.Therefore SRAM interface 403 is compared simpler than SDRAM/DDR, allow processor carry out instruction among the SRAM 404 earlier.
On FPGA, build the system that constitutes by MIPS processor core 401, bus arbiter 402, SRAM interface 403 and SRAM 404, as Fig. 9.Those current obsolete modules are not introduced among the FPGA earlier.When function module circuit is linked together, to guarantee that at first each module all passed through logic that the Logical Design stage carries out and sequential emulation etc., although this can not guarantee the necessarily correctly collaborative work of each module, but can greatly improve the probability that system can move.
Behind the burned fpga chip of the system logic among Fig. 9, the FPGA plate is powered up, check whether can revise the value at place, arbitrary address among the SRAM by means of JTAG by BDI.
But next develop a MIPS assembly routine and confirm instruction of MIPS processor correct execution and visit SRAM.Program is made of two parts, promptly unusual and interrupt table and processor initialization and SRAM fetcher code.
Unusual and the interrupt table of processor will guarantee that processor enters self-loopa in specified location when taking place unusually with interruption.A lot of modes are arranged, and article one instruction of carrying out in the time of for example can allowing unusual and interruption generation is the unconditional jump instruction, jumps to a unification address, and unconditional jump instruction is located to have in this address, and it jumps to the instruction address of self, so just enters self-loopa.
Processor setup code initialization coprocessor register is forbidden the response interruption, forbids enabling the processor high speed memory buffer.
The SRAM fetcher code checks whether SRAM can correctly visit.This can pass through processor memory access instruction (as instructions such as LW, LH, LB and SW, SH, SB), visits according to the mode of byte (8 bit), half-word (16 bit) and word (32 bit) respectively.The similar common memory test program of SRAM fetcher code.The General Principle of memory test is to write the AD HOC word in internal memory, and reading back then compares, if identical explanation read-write is correct, if mistake is then utilized the pattern analysis possible cause of makeing mistakes.SRAM finite capacity, test code can be very not complicated, only carry out some preliminary tests here.
After SRAM can use, next prepare the big a lot of SDRAM/DDR of the capacity of enabling, had bigger internal memory FPGA to go up and just can move more complicated test procedure.Add the SDRAM/DDR module in the FPGA system logic, the SoC structure as shown in figure 10 now.
Revise the code of front visit SRAM, increase SDRAM/DDR controller 405 setup codes.The test class of SDRAM/DDR is similar to the test to SRAM.
2. controller level.Processor on the SoC can executive routine, but the result that program is carried out will be by BDI, and serial ports is used in expectation now.Add AHB/APB 406 bridges and UART 407 in the FPGA system logic, system logic will be as shown in figure 11.
The processor level has guaranteed that SDRAM/DDR is tentatively available, and test procedure can be used to place the program run time version with regard to bigger internal memory is arranged now.Because final boot, operating system, built-in function and application program all is to use the C language development basically, also uses c program development and testing program now as far as possible.Owing to there is not operating system to support on the bare machine, therefore must realize C language call environment, this mainly is to increase BBS section initialization and stack pointer setup code on other test procedure of processor level, jumps to C function entrance main () then and locates to carry out.
The built-in function level has been transmitted printf () interface to controller level level, and this interface will be followed the semanteme of C built-in function printf (), accepts the input parameter of same form, with UART as standard output device.Here the realization of printf () is very simple, at first generates the character string after formaing in internal memory, operates the serial ports related register then character string is exported, and shows the character of output on the main frame with serial port terminal.Lcd controller also can adopt the similar thought of UART, realizes printf ().But to consider character pattern here and handle operations such as new line, give unnecessary details no longer one by one.
Most of controller not only can work in poll but also can work in interrupt mode, and the training in rotation mode is understood and test easily, and interrupt mode requires high to program code, and this level is only considered the training in rotation mode, considers and interrupt mode is placed on the simple application level.
3. simple application level.The operating system level can correctly be transplanted in order to guarantee the operating system level to simple application level TRANSFER MODEL, realizes two main line actuating logics in the simple application level, and one is master routine, and one is Interrupt Process.In SoC, increase interruptable controller and timer.Logic among the FPGA looks as shown in figure 12 now.
Revise the program of controller level, add interruptable controller 409 initialization, interrupt sending, distribute, discharge, forbidding and enable interface.The way that these interfaces can be copied the linux kernel realizes.Each interruption has a numbering, and corresponding to interrupting array one provides Interrupt Process function pointer and Interrupt Process function parameters.Interrupt distribution and release relate to the management of interrupting array.
Next test each controller and whether can work in interrupt mode,, send out the form that ping wraps to the FPGA plate, detect the working condition of network interface card interrupt mode with main frame such as adding network interface card.If network interface card can true(-)running, just can transplant a boot, such as u-boot.
The simple application level can also be verified the situation of a plurality of function module circuit collaborative works, for example when displaying video, video data will utilize the DMA transmission then from memory device (reading NAND Flash or the SD/MMC), through the video accelerating engine, finally send by lcd controller.The execution flow process and the algorithm model of the playing process that extracts from video jukebox software just can be realized at the simple application layer in a kind of mode of simplification.
4. operating system level.The simple application level has been guaranteed the parts of the SoC that the operating system level the is used cooperation operate as normal of can meeting, and core actuating logic and algorithm model that this level is used are verified in the simple application level, code with reference to the simple application level, the relevant code of retouching operation system, the transplanting of complete operation system.
5. built-in function level.Built-in function is the basis of application level, verifies the interface that these have definite language to define one by one.
6. application level.Developing application and test.Application program utilizes built-in function to come the using system resource, the cooperation that palpus SoC goes up a plurality of controllers during actual motion, to use MIPS processor core, bus, video accelerating engine, LCD, SD/MMC controller and DMA etc. such as the software of separating video, the model of application level has been delivered to the simple application level, code there can be developed as the basis.
Figure 13 shows the structural principle of the emulation test system of the SOC (system on a chip) that the embodiment of the invention provides, and for convenience of description, only shows the part relevant with the embodiment of the invention.
Model Transfer information receiving module 1312 is used to receive the Model Transfer information between outside each test level of importing, and wherein, the Model Transfer packets of information contains the Model Transfer relation information between each test level, and the Model Transfer content information.In the embodiment of the invention, Model Transfer is carried out to the low-level test phase by the high-level test phase, at first want clear and definite which test level to need TRANSFER MODEL, which test level need receive the content of the model of the model of transmission and transmission, the content of Model Transfer comes from the structural information of the application software of test level division information receiver module 1311 receptions, promptly comprises information such as software level, actuating logic, algorithm model, calling interface and data structure.
Test code generation module 1313 is used to resolve the test level division information of testing 1311 receptions of level division information receiver module and obtains each test hierarchical information, the Model Transfer information that receives according to Model Transfer information receiving module 1312 generates corresponding test code, and the code that generates inputed to operation in the programmable logic device (PLD) emulation board 132, test and detect operation result, analyze the result of acquisition and the difference of expected results then, judge whether to cause according to difference by chip structure and application software architecture, if then revise chip structure and application software architecture, repeat whole test process then.Wherein, programmable logic device (PLD) emulation board 132 can add necessary parts according to actual needs, as power supply, serial ports, network interface card, keyboard etc.
Each module in the system testing unit 131 can be the unit of software unit, hardware cell or software and hardware combining, and the software unit part can be stored in the computer read/write memory medium, as ROM/RAM, disk, CD etc.Programmable logic device (PLD) emulation board 132 can be the FPGA emulation board.
In the embodiment of the invention, divide the test level according to SoC chip structure and application software information, the model that transmits according to test target and other levels of each test level generates then, the use test instrument carries out functional test, thereby make applied software development organically incorporate the emulation testing stage of SoC chip, benchmark in the emulation testing can easily or be directly used in the applied software development, improve the reusability of testing software, can in time confirm the match condition of SoC chip structure and application software simultaneously.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (8)
1. the emulation test method of a SOC (system on a chip) is characterized in that, said method comprising the steps of:
Receive the test level division information of the SoC chip of outside input; Described test level division information includes the structural information of SoC chip and the structural information of application software;
Receive the Model Transfer information between outside each test level of importing; Described Model Transfer packets of information contains the Model Transfer relation information between each test level, and the Model Transfer content information;
Resolve described test level division information, obtain each test hierarchical information, if current test level does not come from the model that other levels are transmitted, the structural information of then arbitrarily choosing application software generates the test code of this level and by the testing tool operation, one by one each test layer level of obtaining is tested; Come from the model that other levels are transmitted if current test level has, then generate corresponding test code and, one by one each test layer level of obtaining is tested by the testing tool operation according to described Model Transfer information.
2. emulation test method as claimed in claim 1 is characterized in that the structural information of described application software comprises software level, actuating logic, algorithm model, calling interface and data structure information.
3. emulation test method as claimed in claim 2 is characterized in that, described calling interface information comprises semanteme, input parameter and form thereof, output parameter and form thereof and the information of returning and the form thereof of interface; Described data structure information comprises the type and the constituted mode of data structure.
4. emulation test method as claimed in claim 1 is characterized in that, described Model Transfer content information comprises software level, actuating logic, algorithm model, calling interface and data structure information.
5. the emulation test system of a SOC (system on a chip) is characterized in that, described emulation test system comprises system testing unit and programmable logic device (PLD) emulation board;
Described system testing unit comprises:
Test level division information receiver module, be used to receive the test level division information of the outside SoC chip of importing; The test level division information of the SoC chip that described test level division information receiver module receives includes the structural information of SoC chip and the structural information of application software;
The Model Transfer information receiving module is used to receive the Model Transfer information between outside each test level of importing; The Model Transfer packets of information that described Model Transfer information receiving module receives contains the Model Transfer relation information between each test level, and the Model Transfer content information; And
The test code generation module, be used to resolve the test level division information that described test level division information receiver module receives and obtain each test hierarchical information, if current test level does not come from the model that other levels are transmitted, the structural information that described test code generation module is arbitrarily chosen application software generates the test code of this level; Come from the model that other levels are transmitted if current test level has, described test code generation module generates corresponding test code according to described Model Transfer information;
Described programmable logic device (PLD) emulation board is used to move the test code that described test code generation module generates.
6. emulation test system as claimed in claim 5, it is characterized in that, in the test level division information that described test level division information receiver module receives, the structural information of application software comprises software level, actuating logic, algorithm model, calling interface and data structure information.
7. emulation test system as claimed in claim 6 is characterized in that, described calling interface information comprises semanteme, input parameter and form thereof, output parameter and form thereof and the information of returning and the form thereof of interface; Described data structure information comprises the type and the constituted mode of data structure.
8. emulation test system as claimed in claim 5 is characterized in that, described Model Transfer content information comprises software level, actuating logic, algorithm model, calling interface and data structure information.
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| CN102201267A (en) * | 2010-03-26 | 2011-09-28 | 上海摩波彼克半导体有限公司 | Platform system for realizing circuit verification of Nandflash flash memory controller based on FPGA (Field Programmable Gate Array) and method thereof |
| CN102955713B (en) * | 2011-08-31 | 2015-11-25 | 北京中电华大电子设计有限责任公司 | The disposal route that a kind of 802.11n wireless network card chip emulation firmware is optimized |
| CN103150281B (en) * | 2013-03-28 | 2016-04-06 | 青岛中星微电子有限公司 | The integrated approach of bus bar module, device and verification method and device |
| CN103714219A (en) * | 2014-01-06 | 2014-04-09 | 北京昆腾微电子有限公司 | Method and system for verifying digital circuit module in integrated circuit |
| KR102147172B1 (en) * | 2014-04-09 | 2020-08-31 | 삼성전자주식회사 | System on chip and verification method thereof |
| CN107239391B (en) * | 2016-03-29 | 2021-03-16 | 腾讯科技（深圳）有限公司 | Application program testing method and device and terminal |
| CN106371995A (en) * | 2016-09-05 | 2017-02-01 | 芯海科技（深圳）股份有限公司 | Method for realizing rapid automated testing through MCU (Microprogrammed Control Unit) simulator |
| CN108241546B (en) * | 2017-12-04 | 2021-02-02 | 北京东土科技股份有限公司 | Method, device and system for sharing use of BDI debugger |
| CN110737577B (en) * | 2018-07-20 | 2022-11-04 | 北京奇虎科技有限公司 | Test defect data storage method and device |
| CN112363752B (en) * | 2020-11-11 | 2023-11-03 | 海光信息技术股份有限公司 | Chip verification method and device based on configurable operating system |
| CN113766216A (en) * | 2021-09-08 | 2021-12-07 | 北京爱芯科技有限公司 | Verification method and verification system for video module |
| CN114330178B (en) * | 2021-12-28 | 2023-03-14 | 杭州朗迅科技有限公司 | Drive system for debugging and verifying embedded hardware circuit |
| CN115248998B (en) * | 2022-09-22 | 2023-01-03 | 济南新语软件科技有限公司 | SoC chip distributed simulation verification platform and method |
| CN116225973B (en) * | 2023-05-10 | 2023-06-30 | 贵州轻工职业技术学院 | Chip code testing method and device based on embedded implementation electronic equipment |
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