CN101331554A - Memory with retargetable memory cell redundancy - Google Patents
Memory with retargetable memory cell redundancy Download PDFInfo
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- CN101331554A CN101331554A CNA2006800467474A CN200680046747A CN101331554A CN 101331554 A CN101331554 A CN 101331554A CN A2006800467474 A CNA2006800467474 A CN A2006800467474A CN 200680046747 A CN200680046747 A CN 200680046747A CN 101331554 A CN101331554 A CN 101331554A
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Abstract
In a memory array having redundant columns, a scheme allows defective cells to be individually remapped to redundant cells in a redundant column. Redundant cells in one redundant column replace defective cells in multiple non-redundant columns. Remapping is done as part of initial test and configuration. Specific hardware can be used for the scheme or firmware in the memory controller can implement the scheme.
Description
Technical field
The present invention relates to nonvolatile memory, and the redundant data storage units that relates in particular in the use flash memory replaces defective data storage cell.
Background technology
Nowadays there are many commercial successful non-volatile memory products to be used, especially with the form of small-shape factor card, it adopts quickflashing EEPROM (electronics Erasable Programmable Read Only Memory EPROM) cellular array that is formed on one or more integrated circuit (IC) chip.Memory Controller (its usually but not necessarily be positioned on the independent integrated circuit (IC) chip) and main frame (described card is connected to described main frame in removable mode) boundary connect and control the operation of described card internal storage array.This controller comprises microprocessor, a certain non-volatile ROM (read-only memory) (ROM), volatile random access memory (RAM) and one or more special circuits usually, for example when data are passed described controller during programming and reading of data, come the special circuit of miscount correcting code (ECC) by described data.In the commercially available card some is CompactFlash
TM(CF) card, multimedia card (MMC), secure digital (SD) card, smart media card, individual label (P-label) and memory stick card.Main frame comprises personal computer, notebook, PDA(Personal Digital Assistant), various data communication equipment (DCE), digital camera, cell phone, portable audio player, car audio system and same category of device.Except that the storage card embodiment, alternately this type of storer is embedded in all kinds of host computer systems.
There are two general memory array architecture (that is, NOR and NAND) to be applied in the commerce.In typical NOR array, memory cell is connected between adjacent bit line source and the drain diffusion, described diffusion is extended along column direction, wherein controls grid and is connected to the word line that extends along cell row.Memory cell comprises at least one memory element, and described element is positioned at least a portion in the cell channel zone between source electrode and the drain.Therefore, the charge level of having programmed on the described memory element is controlled the operating characteristics of described unit, thereby can read described unit by applying suitable voltage to addressed memory unit.The 5th, 070,032,5,095,344,5,313,421,5,315,541,5,343,063,5,661,053 and 6,222, example, its use and manufacture method thereof in accumulator system of this unit are provided in No. 762 United States Patent (USP)s.These patents are incorporated herein with way of reference in full together with all other patents of being quoted in this application case, patent application case and other open case.
The NAND array utilizes two above memory cells (for example 16 or 32 s') series connection string, and it selects transistor to be connected between individual bit lines and the reference potential to form cell columns together with one or more.Word line is crossed over the unit in these a large amount of row and is extended.Depend on that the charge level that is stored in the selected cell reads and verify the individual elements in the row by making the residue unit hard firing in the described string during programming so that flow through a string electric current.The 5th, 570,315,5,774,397,6,046,935 and 6,522, the example of NAND architecture array is proposed and as the operation of the part of accumulator system in No. 580 United States Patent (USP)s.
Modal in the charge storage cell of the current quickflashing eeprom array of discussing in the previous institute referenced patents is the conduction floating boom, and it is formed by the polycrystalline silicon material of conductiving doping usually.The memory cell that can be used for the alternative type of quickflashing EEPROM system utilizes non-conductive dielectric material to substitute described conduction floating boom with the non-volatile storage electric charge.Three layers of dielectric medium that formed by monox, silicon nitride and monox (ONO) sandwich between the surface of the semiconductive substrate on the conductive control grid utmost point and the memory cell channel.By electronics is injected into the described unit of programming in the nitride (intercepted and captured and be stored in the confined area at electronics described in the described nitride) from cell channel, and wipe described unit by hot hole being injected into nitride.The several discrete cell structures and the array of employing dielectric storage element are described in No. the 2003/0109093rd, your (Harari) people's of etc.ing of Harrar the U.S. Patent Application Publication case.
With the same in most integrated circuit are used,, also exist and dwindle the pressure of implementing the required silicon substrate area of some integrate circuit function for the flash EEPROM memory array.Need to increase the amount of the numerical data in the silicon substrate that can be stored in set area always,, or not only increase capacity but also reduce size so that increase the memory capacity of the encapsulation of the storage card of both sizings and other type.A kind of mode that is used to increase the density of data storage is that one of each memory cell and/or each storage unit or element storage are with upper data.This can be divided into two or more states and realize by the window with storage element charge level voltage range.Use four this states to allow the data of each two position of storage, unit, use eight states to allow the data of each three position of storage element stores, the rest may be inferred.Use the multimode quickflashing eeprom structure and the operation thereof of floating boom to be described in the 5th, 043,940 and 5,172, in No. 338 United States Patent (USP)s, and for the structure of using dielectric floating gate, it is described in the open case of No. 2003/0109093 aforesaid U.S. Patent application.For various reasons, also can be by the 5th, 930, No. 167 and the 6th, 456, the mode described in No. 528 United States Patent (USP)s is with the selected part of two states (scale-of-two) operation multistate memory array.
The memory cell of typical quickflashing eeprom array can be divided into the discrete unit piece of wiping together.That is to say that piece is exactly an erase unit, the unit of the minimal amount that can wipe simultaneously.Each piece is stored one or more data pages usually, and described page or leaf is minimum programming and reading unit, but can programme or read page or leaf more than in different subarrays or plane concurrently.Each page or leaf is one or more data segments of storage usually, and the size of described section is defined by host computer system.The exemplary section comprises the user data (it follows the standard of setting up at disk drive) of 512 bytes, add a certain number byte about user data and/or store the Overhead of the piece of described user data.Sort memory is configured to have in each piece many pages or leaves usually, and a plurality of host sectors of data of each page or leaf storage.
User data is programmed in the memory array and reads degree of parallelism during the user data in order to increase from it, generally described array is divided into plurality of sub array (being commonly referred to as the plane), described subarray contain himself data register and other circuit allowing parallel work-flow, thereby each or each from several or all planes that a plurality of data segments can be programmed into simultaneously in several or all planes read a plurality of data segments simultaneously.Array on the single integrated circuit can physically be divided into a plurality of planes, or each plane can be formed by one or more independent integrated circuit (IC) chip.The example of this storer embodiment is described in the 5th, 798, No. 968 and the 5th, 890, No. 192 United States Patent (USP)s.
For further diode-capacitor storage effectively, can be with block chaining together to form dummy block will or first piece.That is to say, each first piece is defined as a piece that comprises from each plane.The 6th, 763, the use of first piece is described in No. 424 United States Patent (USP)s (described patent is incorporated herein in full with way of reference).By the host logic block address described first piece is identified as and is used to programme and the destination of reading of data.Similarly, all pieces of first piece are wiped free of together.Use the controller in the accumulator system that this bulk and/or first piece operate to carry out some functions, wherein comprise the LBA (Logical Block Addressing) (LBA) that receives from main frame and the conversion between the physical block number (PBN) in the memory array.Usually discern individual page in described by the skew in the block address.Address translation usually comprises the middle entry that uses logical block number (LBN) and logical page (LPAGE).
In some accumulator system, also physical memory cells arc is grouped into two or more district's bands.District's band can be any subclass of having cut apart of physical storage or accumulator system, and wherein the LBA (Logical Block Addressing) of particular range is mapped in the described subclass.For example, the accumulator system that can store 64 megabytes of data can be divided into four zones, and the data of each area stores 16 megabyte.Then, also the scope of LBA (Logical Block Addressing) can be divided into four groups, the physical block of each in described four district's bands is assigned a group.In typical embodiment, LBA (Logical Block Addressing) is restricted, to such an extent as to the data of each LBA (Logical Block Addressing) will not be written to the outside of the single physical district band that described LBA (Logical Block Addressing) is mapped to.Be divided into some planes (subarray) (respectively have himself addressing, programme and read circuit) memory array in, each district's band preferably comprises the piece from a plurality of planes, is generally from each the piece of similar number in the described plane.District's band is mainly used in the address administration of simplification such as logic to physical transformation, thereby obtain less conversion table, preserve the very fast access time that these are shown required less RAM storer and are used for the current active zone of addressable memory, but may cause abrasion equilibration not reach the best owing to its finitude.
Individual flash EEPROM unit is stored in a certain amount of electric charge (it represents one or more data) in charge storage cell or the unit.The threshold voltage that the charge level of memory element is controlled its memory cell (generally is expressed as V
T), it is as the foundation of the store status that reads described unit.Generally threshold voltage window is divided into some scopes, the corresponding scope of each in two or more store statuss of described memory cell.In this way, the number of the visual voltage range in a unit and preserve the data that the data of a position maybe can be preserved two or more.These scopes are separated by boundary belt, and described boundary belt comprises the nominal of the store status that allows definite individual elements and reads level.Owing to electric charge to the programming carried out in adjacent or other associated memory unit, page or leaf or the piece, read or the interference of erase operation makes these memory level often be shifted.Therefore, come miscount correcting code (ECC) by controller usually, and described error-correcting code stored together with the host data of being programmed, and during reading in order to verification msg and carry out to a certain degree the adjustment of data where necessary.Equally, the displacement charge level can recover to get back to the center of its state range every now and then before perturbation operation makes it be offset out its scope that has defined fully and therefore causes the read error data.This process is called Refresh Data or removing, and it is described in the 5th, 532, and No. 962 and the 5th, 909, in No. 449 United States Patent (USP)s, described patent is incorporated herein in full with way of reference.
Memory cell in the memory array is defectiveness sometimes.Can may between the operating period defective appear at chip owing to manufacturing defect causes unit defectiveness or unit in the new memory chip.When the unit defective occurs during use, can detect defective owing to wiping, be written to the unit or reading from the unit.A kind of mode of handling this defective for the data storage that will will store in the defective part of storer in the another position.Title for " Nonvolatile memory system card (Non-volatile memory system card with flash erasablesectors of EEPROM cells including a mechanism for substituting defective cells) " with quickflashing erasable area section of the EEPROM unit that comprises the mechanism that is used to be substituted with defective unit the 5th, 535, this data of description from the defectiveness position to the position of substitution remap in No. 328 United States Patent (USP)s, and described patent is incorporated herein in full with way of reference.The defectiveness unit can be remapped to diverse location or whole section is remapped to the another location.Title for " device and method (Device and method for defect handling in semi-conductor memory) that is used for the defect processing of semiconductor memory " the 5th, 200, description is used for reorientating several another programs away from the defectiveness unit in No. 959 United States Patent (USP)s, and described patent is incorporated herein in full with way of reference.Reorientate whole data in the time of also can in a piece of memory array, having defective unit in this way.
At title be " quickflashing eeprom array data and header file structure (Flash EEPROM arraydata and header file structure) " the 5th, 438, describe the another program that is used to manage the defectiveness unit in No. 573 United States Patent (USP)s, described patent is incorporated herein in full with way of reference.This scheme will be repositioned onto the next unit in the described row corresponding to the data of a position of defectiveness memory cell.To be repositioned onto its adjacent cells corresponding to the position of next unit, the rest may be inferred, thereby will push away one on the position in the described row.All provide redundant digit in each row, therefore described data are still in described row.
Can several modes detect the defectiveness unit, for example, during test procedure, in factory, before using memory chip, finish detection usually, or between the normal operating period, search defective by Memory Controller usually by the user.Factory testing can be searched formed in the mill physical imperfection usually.Special test equipment is used in this test, when carrying out test special test equipment is connected to accumulator system, and after test is finished itself and accumulator system is disconnected.With the permanent mode defectiveness zone of remapping.Can be by attempting programming, reading and wipe the memory array each several part and whether have the unit that in specified limit, to carry out to search defective to check.Also can adopt title be " in the EEPROM device latent defect handle (Latent defect handling inEEPROM devices) " the 5th, 428, No. 621 the described mode of United States Patent (USP) detects latent defect, and described patent is incorporated herein in full with way of reference.
In some prior art design, the defectiveness that provides redundant columns of cells to replace in the memory array is listed as.If there is not defective in the memory array, then this redundant columns is not stored any data.Fig. 1 shows the example according to the use of the redundant columns of prior art.At the test period of memory array, found a memory cell defectiveness.The reason that described defective produces can be pollution, improper processing or a certain other reason.When running into defectiveness unit 101 in row 1, row 1 are regarded as the defectiveness row and are mapped to redundant columns A.Write down this mapping so that row 1 no longer are used in a certain mode.Usually write down described mapping by the burning fuse of indicating described defectiveness row.To send to row 1 in the original plan now but because described remapping and any data of not sending to row 1 send to redundant columns A.Be substituted with defective unit 101 by replacing unit 103.In addition, also replace all other zero defect unit in the row 1 by the unit among the redundant columns A.
Fig. 2 shows the sketch be used for the accumulator system 200 that execution graph 1 illustrated row replace.At test period, light the position that the quickflashing fuse is indicated the defectiveness row.The quickflashing fuse is flash cells or the cell group that can be considered fuse, but different with conventional fuse be that it can be programmed again.Can there be a fuse in each non-redundant column in the flash memory cell array 221.When accumulator system 200 starts, quickflashing fuse 220 is read in the row Redundant Control register 222, thereby can indicate the defectiveness row and replace the position that is listed as by the content of described register.When main frame sent memory access instruction, physical address that will access and the column address in the row Redundant Control register 222 compared.If indication defectiveness row, then access replaces row, rather than attempts access defectiveness row.Therefore, row Redundant Control register 222 will replace that column address offers Y address decoding circuit 224 so that the defectiveness row not by access.Can replace above defectiveness row in this way.Some replacement row 226 are provided usually, therefore can replace some row.Fig. 1 shows N+1 non-redundant column (row 0 to N) and four redundant columns (row A is to D).Word line and described row meet at right angles and cross over described array extension, and it extends above redundancy and non-redundant column.
The defectiveness unit can not be the unit that can not use fully always, and it can only be operated outside the performance limitations of appointment.For example, still can not programme, it is considered as the defectiveness unit yet even after the potential pulse of a certain number, also there is programmed unit providing under the situation of additional pulse.The number of the defectiveness unit that selected performance limitations decision is found.By setting high performance limits, can improve overall performance (for example, can reduce the programming time), but the defective number can increase.Setting low performance limits can performance be that cost reduces number of defects.
Operate though the prior art row replacement scheme of above-mentioned Fig. 1 and Fig. 2 allows memory array to be listed under the situation with one or more defectiveness unit, it has several shortcomings.This scheme needs redundant columns and the non-redundant column with defective unit as many, and each defective needs a redundant columns usually.Redundant columns takies the useful space on the chip and increases production cost of chip.The redundant columns that is provided is many more, and cost is just big more.Yet if very little redundant columns is provided, the redundant columns that exists may be not enough to repair some chip so that chip can not use.Therefore, if very little redundant columns is provided, then qualification rate can be impaired.Newer memory array has more multi-memory unit and littler characteristic dimension, and this tends to increase the number of defective in the memory array.Equally, because the more multiple-unit in the big page or leaf of programming together, so do not have in a few slow cells that the programming time tends to be limited under the substituted situation.Therefore, the replacement of defectiveness unit is very important for newer accumulator system.
Therefore, need the more effective mode that is mapped with defective unit in a kind of space.Also need to comprise the accumulator system that more effectively to carry out the circuit of this mapping.
Summary of the invention
When retargetable memory cell redundancy scheme allows to contain the defectiveness unit in redundant columns the defectiveness unit individually is mapped to the redundancy unit in the redundant columns, rather than permutation is mapped to redundant columns.In this way, the defectiveness unit maps in a plurality of row can be listed as to same redundant.Needn't only permutation be considered as defectiveness because of one or more unit defectiveness in the row.This allows more effectively to use the free space in the redundant columns.
Using before accumulator system comes storaging user data, detecting the defectiveness unit and it is mapped to redundancy unit in the redundant columns as the part of initial testing and configuration operation.Described mapping is normally nonvolatil, and therefore the life period in accumulator system does not use any defectiveness unit always.The defective mapping (enum) data record defective row or unit in memory array the position and during initial testing and configuration, produce and be stored.The defective mapping (enum) data can be stored in the part of flash memory or be stored in the private memory.
(after initial testing and the configuration) be redirected any trial that is used for access defectiveness unit, then access replaces the unit during the normal running of accumulator system.Be redirected for this that will carry out, the row and the row address of row and row address and defectiveness unit must all mate, and only must the coupling column address in the prior art scheme.
Can implement individual elements replacement and row in the same memory system simultaneously replaces.In general, at first wherein all memory cells being any row that defectiveness unit or defectiveness unit number surpass threshold number carries out row and replaces.Subsequently, the individual elements in the residue non-redundant column can be mapped to permutation and replace unwanted redundant columns.The mode of the intermediate sizes cell group that also can comprise an above unit but lack than the permutation unit number replaces the unit.The example of this intermediate sized group is the group that is formed by the memory cell of being connected in series in the NAND string.
But use location and memory array are adjacent and implement unit replacement scheme with the circuit that memory array is positioned on the identical chips.Sort circuit is similar to some circuit of prior art, the row address of row address with the defectiveness unit that has remapped is compared with permission but contain extra circuit.Perhaps, can use be used for will access the Memory Controller that compares of address and address from the defective mapping (enum) data implement the unit and replace scheme.Can under the situation that does not change hardware, implement this scheme and it only needs to change the Memory Controller firmware.
Flash memory is the piece erasable memory, therefore erase unit individually not, but be the unit erase unit with the piece.Piece is crossed over multiple row usually and is extended.Piece can be crossed over redundant columns and non-redundant column, and both extend and with the redundancy unit of the defectiveness unit maps in the piece in the same block.Therefore, redundancy unit and the non-redundant cells that contains the logic sequence data can be wiped together.
Description of drawings
Fig. 1 shows that the row of prior art replace scheme.
Fig. 2 shows that the row that are used for execution graph 1 replace the prior art memory array and the peripheral circuit of scheme.
Fig. 3 shows the accumulator system of supporting the some aspects of the present invention.
The block structure of the memory array of the accumulator system of Fig. 4 graphic extension Fig. 3.
The structure of the piece 100 of Fig. 5 A displayed map 4, it has a plurality of NAND strings that connect by word line and bit line.
The more detailed view of the NAND string of Fig. 5 B displayed map 5A.
Fig. 6 shows the example that redundancy unit and the redundant columns according to the embodiment of the invention remaps.
Fig. 7 shows and to be used to carry out redundancy unit and redundant columns the remap test of scheme (for example, scheme shown in Figure 6) and the process flow diagram of configuration operation.
Fig. 8 shows and to be used to carry out the remap calcspar of circuit of scheme (for example, the scheme of Fig. 6) of redundancy unit and redundant columns.
Fig. 9 shows and to be used to carry out the remap calcspar of alternative hardware of scheme (for example, the scheme of Fig. 6) of redundancy unit and redundant columns.
Embodiment
Fig. 3 shows the accumulator system 330 that comprises each side of the present invention.Accumulator system 330 be connected to the main frame (not shown) and with described main-machine communication.Usually carrying out between main frame and the accumulator system this by standard interface communicates by letter.In some instances, accumulator system (for example, accumulator system 330) is the part with removable storage card of standard interface, therefore can be according to being connected to various main frames such as previous described standard.In alternative arrangement, accumulator system (for example, accumulator system 330) can be embedded in the host computer system, therefore it for good and all can be connected to described host computer system.
Accumulator system 330 comprises controller 20, and it comes the operation of control store array 1 in response to the order that receives from main frame.Controller 20 can contain microprocessor, RAM, quickflashing, impact damper, register, error-correcting code (ECC) circuit and be used for other circuit of diode-capacitor storage system 330.Write when instruction when receiving main frame, in the data storage that will receive from main frame under the indication of controller 20 memory array 1.For example, the physical location that writes of these data is determined by controller usually.Controller 20 is according to the firmware operation that can be loaded into controller 20 during initial configuration.When main frame receives reading command, under the indication of controller 20 from memory array 1 reading of data.Controller 20 is kept the record of the logic of host data to physical mappings usually, so when main frame passes through the logical address recognition data, but the data at the correct physical address place in the access memory array 1.
Controller 20 is communicated by letter with memory array 1 with the peripheral circuit between the memory array 1 by controller 20.Peripheral circuit comprises line control circuit 3, arrange control circuit 2, data input/output circuit 6, state machine 8 and command circuit 7.Also can use extra peripheral circuit, but in Fig. 3, not show for clarity.When special command slave controller 20 was sent to command circuit 7, state machine 8 was configured to by proper signal being sent to line control circuit 3 and arrange control circuit 2 is carried out described order.When state machine 8 complete operations, it turns back to command circuit 7 with signal, and command circuit 7 is finished to the described operation of controller 20 indications again.Controller 20, memory array 1 and peripheral circuit can be formed on the single chip together.Perhaps, on a chip, form memory array and peripheral circuit, and on another chip, form controller, shown in the dotted line of between controller chip 21 and memory array chip 22, cutting apart accumulator system 330.
Fig. 4 shows the structure of the memory array 1 that comprises a plurality of, and piece is a minimum unit of erase.In this example, memory array has 1024 pieces (piece 0 to 1023), wherein comprises following piece in greater detail 100.Yet some memory array can have more polylith.Also can be with block chaining to form first piece of wiping and then being regarded as single bulk together.In some storer, piece can be arranged in some planes, its midplane is the group of the piece of shared some read.
Fig. 5 A and 5B show the example of the structure of the nand memory array 1 that uses the some aspects of the present invention.Piece 100 is by a plurality of NAND string 50a, 50b ... 50c forms, and each string all has a plurality of floating boom unit that are connected in series.The additional strings that Fig. 5 A does not show is between string 50b and 50c.Fig. 5 A shows that string 50a, 50b, 50c are (squares 100) that how to be linked at together with a part that forms array.Bit line 51a, 51b ... 51c vertically moves and is connected with a plurality of strings.The NAND string that is connected to single bit line forms row.For example, the string 50a, the 50d...50x that are connected to bit line 51a form row 55a, and the string 50b, the 50e...50y that are connected to bit line 51b form row 55b.Row 55a and 55b are non-redundant column.String 50c, 50f ... 50z forms redundant columns 55c.As shown in the figure, piece (for example, piece 100) can be crossed over a plurality of row extensions.Row can run through a plurality of and vertically extend.Redundancy is classified the row that generally do not contain data as, unless there is defective.Non-redundant column generally contains data when its memory portion of locating is not wiped free of.The data of being stored in the memory array can be the header data of host data, ECC data, a certain form, control data or a certain other data that controller is stored.Word line is crossed over the piece along continuous straight runs and is extended.Source electrode line is also crossed over the end that piece extends and be connected to the NAND string.Can be considered as the delegation in the memory array by one group of unit that word line connects.Piece 100 is made up of the NAND string 50a, the 50b...50c that connect by word line.The unit of piece 100 is wiped together and can not be wiped separately.
Fig. 5 B schematically graphic extension is organized into the string 50a of the memory cell of NAND string.NAND string 50a is by concatenation transistor M1, the M2...Mn (n=4,8,16 or higher) that pass through source electrode separately and drain and connect with daisy chaining.A pair of selection transistor S1, S2 control the connection of string 50a to the residue string of memory array via the source terminal 54 and the drain terminal 56 of NAND string.In memory array, when conducting drain selection transistor S1, source terminal is coupled to source electrode line.Similarly, when transistor S2 was selected in the conducting drain electrode, the drain terminal of NAND string was coupled to the bit line of memory array.Each memory transistor in the chain has a charge storage cell with the both quantitative electric charge of storage, thereby presents the memory state of expection.The control grid of each memory transistor all provides reading and the control of write operation.Select each the control grid among transistor S1, the S2 to provide control access via its source terminal 54 and drain terminal 56 respectively to the NAND unit.
When reading and verifying the addressed memory transistor in the NAND string during programming, its control grid is supplied with suitable voltage.Simultaneously, do not apply enough voltage on the control grid of addressed memory transistor by the residue in NAND string 50 and the described not addressed memory transistor of conducting fully.In this way, produce the conductive path of the source terminal 54 of string effectively, similarly, produce the conductive path of drain terminal 56 effectively from indivedual insulator transistor drain to described string from the transistorized source electrode of individual memory to NAND.Piece 100 is crossed over the redundancy and the non-redundant column of memory array and is extended.Can be with the defectiveness unit maps in the piece 100 to the redundancy unit that also is positioned at piece 100.
Fig. 6 shows the redundant columns mapping according to the embodiment of the invention.Different with the redundant columns of prior art, the redundant columns B of Fig. 6 contains an above non-redundant column (row 2 and 3) the institute mapped data from memory array 600.The first defectiveness unit 602 in the row 2 is mapped to redundancy unit 604 among the redundant columns B.The second defectiveness unit 606 in the row 3 is mapped to another redundancy unit 608 among the redundant columns B.Therefore, a redundant columns (row B) is used for storing the data of two the different non-redundant column (row 2 and row 3) from memory array 600.In this way, can use a redundant columns to repair a plurality of defectives in the memory array.This is than using the prior art scheme of whole redundant columns much effective at each defective in the memory array.In the embodiment shown, when in row, finding defective, map unit line by line, rather than shine upon all unit in the described row.Therefore, can only defectiveness unit 602,606 be mapped to redundant columns B.Not with other zero defect unit maps in row 2 and the row 3 to redundant columns B.
The defectiveness unit maps is arranged in the unit of same row in the redundant columns.This means the shared word line of defectiveness unit and the redundancy unit that replaces described defectiveness unit.In this scheme, can be along word line only with a defectiveness unit maps to redundant columns.But, under the situation that can use an above redundant columns, can be about to each defective along one and be mapped to different redundant columns, therefore, the number of the tolerable defective in the delegation can be identical with the number of available redundancy row.For example, the defectiveness unit 610 in Fig. 6 display column 1.Defectiveness unit 602 in defectiveness unit 610 and the row 2 all is arranged in row 612.Because the unit among the redundant columns B 604 is used for the data from unit 602, so defectiveness unit 610 is mapped to redundancy unit 614 among the redundant columns C.Can be at the redundant columns mapping scheme that has enable nand gate (for example, enable nand gate shown in Fig. 5 A and Fig. 5 B) or have the NOR structure or have execution graph 6 in the memory array of another structure.
Except that having from the redundant columns of a plurality of row mapped data, also there is the additional redundant columns of operation in a usual manner.These row replace whole non-redundant column, so each unit of non-redundant column replaces by the unit of redundant columns.This can finish when looking non-redundant column for defectiveness.This may be because equal defectiveness in all unit (not can read) in the described row or because the defectiveness unit outnumbers threshold number in the described row.For example, Fig. 6 demonstration is mapped to redundant columns A with defectiveness non-redundant column 0, and it becomes one and replaces row.
Can be used as a part that initial testing and configuration do finishes or is finished the mapping (reach mapping that defectiveness be listed as redundant columns) of defectiveness unit to redundancy unit the time subsequently storage of subscriber data is in accumulator system after.In some instances, do during (it is carried out in factory in sale or before using accumulator system usually) in initial testing and configuration, redundant columns only is used to remap.The defective that can otherwise processed occurs subsequently or find subsequently.Remapping during initial testing and the configuration is nonvolatil, and therefore (for example) writes down described remapping by using fuse in irreversible mode.
Though shown in Figure 6 reorientating is single position or row, other replaces unit also is possible.For example, in the nand memory shown in Fig. 5 A and Fig. 5 B, can replace a string location easily, wherein said string contains the defectiveness memory cell.Therefore (for example) if the string 50a of Fig. 5 A includes defective unit, then can adopt string 50c to replace string 50a, and not need to shine upon other string (for example, string 50d) that is connected to bit line 51a.
Fig. 7 shows the process flow diagram that initial testing that the memory array according to the embodiment of the invention lists and configuration are done.Can be after the memory array manufacturing but before main frame uses, use the testing apparatus that is connected to memory array carry out shown in this test and configuration.Usually to come the testing memory array with the mode of controller and the isolation of other circuit.But also execute card level detecting, but its defective in instruction memory array not usually.At first, finish test and determine whether have defective unit (720) in the memory array.This can be by being programmed into test data memory array and the described test data of reading back is then finished.If in the given time can't programming data, then visual element be a defectiveness.If the data of reading back from the unit are inequality with the data that are written to described unit, then visual described unit is a defectiveness.Removed state if the unit can't reach in the schedule time of removing during doing, then also visual described unit is a defectiveness.Perhaps, can measure and let out electric current and discern the defectiveness unit, maybe can use the member of a certain other identification defectiveness unit.Can be with regard to a defectiveness unit testing memory array, to determine the position of all defectiveness unit in the memory array.Next, determine whether to exist in the memory array row (722) that have above the defectiveness unit of chain-reacting amount.If row have the defectiveness unit that surpasses described chain-reacting amount, then replace row (724) by redundant columns.These row that are similar to prior art replace.In an example, described chain-reacting amount equals the number of unit in the described row.In this case, only when all unit equal defectiveness in the row, just replace described row.If the number of defectiveness unit then individually is substituted with defective unit less than the number of whole unit in the described row.Be mapped with after the defective row, the indivedual defectiveness unit maps in one or more defectiveness row are arrived redundancy unit (726).In this way, a redundant columns can contain from a plurality of non-redundant column mapped data.Record the mapping (728) of defective unit in permanent mode, make described information belong to memory array so that use in the future to redundancy unit.A kind of mode that for good and all writes down this defective mapping (enum) data is to use fuse or anti-fuse, the position of its indication defectiveness memory cell and replacement thereof.The another kind of mode that for good and all writes down described defective mapping (enum) data is that it is stored in the part that is exclusively used in this data of storage and is configured to subsequently it to be removed of nonvolatile memory.This can finish by hardware or software.Also can use the method for other permanent storage defective mapping (enum) data.
Fig. 8 shows the example of the accumulator system 841 (it comprises flash memory cell array 843) that comprises each side of the present invention.The same with the situation in some prior art systems, there is quickflashing fuse 840 (also can make) with light fuse or a certain equivalent structure.The defective mapping (enum) data that at first will be stored in the quickflashing fuse 840 is loaded in the capable Redundant Control register 842.The input that row Redundant Control register 842 has from row address register 844.The row address of the next line that this input permission will be read is transferred to capable Redundant Control register 842.Row address (being written into from the quickflashing fuse) in described row address and the row Redundant Control register 842 is compared, to determine whether there is any defective in the described row.If described row address is different with the row address in the row Redundant Control register 842, then in the row of institute's addressing, does not have defective unit, and can use the acquiescence described row of column address access and do not need access redundant columns 844.If from the row address of row address register 844 and the row address coupling in the row Redundant Control register 842, then signal, thereby determine to want the redundant columns non-redundant column of the defective in the addressed row (rather than contain) of access to row Redundant Control register 846.Offer Y address decoding circuit 848 at the column address of this journey indication redundant columns the non-redundant column of defectiveness unit (rather than contain).Therefore, access redundant columns line by line, and in the prior art, access does not rely on row address.At this moment, both all must mate row and column address with the defective locations that is write down, and in the prior art, only need the column address coupling.Can be used as unique replacement scheme and finish this mapping scheme line by line, or can finish this mapping scheme line by line in conjunction with row replacement scheme shown in Figure 6.Under the situation that outnumbers predetermined number of defectiveness unit or defectiveness row, also these schemes and other can be used to replace the scheme combination of (for example, replacing whole) of memory array each several part.
Carrying out the required hardware of described replacement scheme can be included in memory array and be formed in the peripheral circuit on the identical chips.Be called in name " flash memory flexibly with the effective row redundant (Flexible and areaefficient column redundancy for flash memories) in zone " the 6th, 560, be provided for carrying out the example of the hardware of row redundancy scheme in No. 146 United States Patent (USP)s and the 2005/0141387A1 U.S. Patent Publication case, described patent is incorporated herein in full with way of reference.Can receive row address and make the circuit shown in the open case of 2005/0141387A1 patented claim be suitable for carrying out the redundant case (for example, the memory cell redundancy scheme of accumulator system 841) of retargetable memory cell in the circuit that described row address and row (it has the unit that the has been remapped) address of being stored compare by adding.
Fig. 9 shows another example according to accumulator system 960 of the present invention.As shown in the figure, external memory system controller 962 is connected to flash memory device 964.This is similar to example shown in Figure 3.At this moment, external memory system controller 962 is connected to flash memory device 964 by external flash memory bus 966.External memory system controller 962 and flash memory device 964 are formed on the independent chip usually.External memory system controller 962 comprises CPU (central processing unit) (CPU) or microprocessor 968 and controller storage 970 (it can be a random-access memory (ram)).When conducting external memory system controller 962, the defective mapping (enum) data can be loaded in the controller storage 970.Perhaps, can use non-volatile ram to preserve described defective mapping (enum) data.In accumulator system 960, controller storage 970 is written into the defective mapping (enum) data from quickflashing fuse 970.Perhaps, the defective mapping (enum) data can be stored in any other correct position.External memory system controller 962 compares the position of defective and the physical address in the data of access just.When just when the row of the data of access and column address are all mated with defective locations, external memory system controller 962 will indicate the access command of one in the redundant columns 972 row of defectiveness unit (rather than have) to send to flash memory device 964.State machine 974 makes row Redundant Control register 976 give Y address decoding circuit 978 with the redundant columns row of defectiveness unit (rather than have) indication then.Therefore, in Fig. 9, come the performed function of specialized hardware in the accumulator system 841 of execution graph 8 by external memory system controller 962.This example has the advantage of easier enforcement, because it does not need hardware change (because being provided for the external memory system controller of diode-capacitor storage system in most of accumulator systems).Yet, the method may be and is externally applied extra burden on accumulator system controller 962 and the external flash memory bus 966, and this can cause accumulator system 960 operations (with carrying out these functions by the special circuit on the memory array chip and comparing).
In such scheme, position (or the some position) data of defectiveness unit are repositioned onto are arranged in colleague's's (being connected to identical word line) redundancy unit mutually.In many reservoir designs, one along one or more word lines extensions.Therefore, the unit of delegation or group's row is wiped free of together.In embodiments of the present invention, piece extends nonredundancy and the redundancy unit that connects by word line to comprise.Any defectiveness unit in described is remapped to redundancy unit in the same block.Therefore, when wiping non-redundant cells, also the data erase of redundancy unit will be remapped to from non-redundant cells in the redundant columns.This means, when the data in the redundancy unit become discarded data, do not need to follow the tracks of independent data management structure.Because nonredundancy is wiped free of with redundancy unit, so both all turn back to erase status and prepare to receive new data and without any need for independent operation.
Though described each side of the present invention at specific embodiment, should be appreciated that entitlement of the present invention is protected in the full breadth of claims of enclosing.
Claims (23)
1, a kind of nonvolatile memory array, it comprises:
The first row memory cell, it contains a defectiveness unit and some zero defects unit;
The secondary series memory cell, it is the redundant columns that only contains the data of reorientating other position from described memory array; And
Described defectiveness unit individually is mapped to redundancy unit in the described secondary series, thereby with the data storage in described defectiveness unit to be stored in described redundancy unit, described defectiveness unit is arranged in mutually with described redundancy unit goes together, and described secondary series does not contain from the data of the described zero defect unit maps of described first row.
2, memory array as claimed in claim 1, it further comprises the 3rd row that are regarded as defectiveness and do not store data, described tertial all data all be stored in as redundant columns the 4th row in.
3, memory array as claimed in claim 2, wherein said the 3rd row are regarded as defective because of the threshold number that outnumbered of its defectiveness unit.
4, memory array as claimed in claim 1, wherein said defectiveness unit and described redundancy unit are arranged in same and can not wipe separately.
5, memory array as claimed in claim 4, wherein said defectiveness unit to the described map record of described redundancy unit in another piece of described memory array.
6, memory array as claimed in claim 1, wherein said secondary series contains excessive data, and described excessive data is the defectiveness unit maps from the row except that described first row.
7, memory array as claimed in claim 1, wherein said defectiveness unit arrive the outside of the described map record of described redundancy unit at described nonvolatile memory array.
8, memory array as claimed in claim 1, wherein said defectiveness unit is to use fuse or anti-fuse permanent recording to the described mapping of described redundancy unit.
9, memory array as claimed in claim 1, wherein said memory array has enable nand gate.
10, memory array as claimed in claim 1, wherein said first or the individual elements of secondary series contain two or more data.
11, memory array as claimed in claim 1 wherein subsequently when attempting the described defectiveness of access unit, changes the described redundancy unit of access into.
12, memory array as claimed in claim 11 is wherein when attempting the described defectiveness of access unit, with the row of described defectiveness unit and be listed as both to compare with definite described defectiveness unit with the defective mapping be defective.
13, memory array as claimed in claim 12 is wherein compared described row and row and the mapping of described defective by the single user state machine that is connected to described memory array.
14, memory array as claimed in claim 12 is wherein compared described row and row and the mapping of described defective by the controller of also carrying out other memory management functions.
15, a kind of method of during the initialize routine of new memory chip, testing and repairing nonvolatile memory array, described nonvolatile memory array has the redundancy unit of one or more defectiveness unit and one or more redundant columns, and described method comprises:
Detect one or more defectiveness unit in the described memory array; And
Individually assign replacement unit in the redundant columns to replace defectiveness unit in first row, do not replace the unit and do not need to assign any other in the described redundant columns for the zero defect unit of described first row, described defectiveness unit is connected by word line with described replacement unit.
16, method as claimed in claim 15, it further comprises by number and threshold number with defectiveness unit in the secondary series and compares to determine that described secondary series is defective, and assigns whole additional redundant columns to replace described secondary series.
17, method as claimed in claim 15, it further comprises the described appointment by making fuse or anti-fuse generation permanent change write down described replacement unit.
18, method as claimed in claim 15, it further is included in the described appointment of the described replacement of record unit in the nonvolatile memory.
19, a kind of method that replaces a string memory cell in the non-volatile NAND type flash memory array, a string NAND units in series are connected two and select between the grid, and described method comprises:
Determine that the first burst memory unit in first row is the defectiveness string; And
With the second burst memory unit of the described first burst memory unit maps in the redundant columns, and do not need other string of described first row is mapped to described redundant columns.
20, method as claimed in claim 19 is wherein because the described first burst memory unit contains at least one defectiveness unit and it is defined as the defectiveness string.
21, method as claimed in claim 19 is wherein because the described first burst memory unit only contains the defectiveness unit and it is defined as the defectiveness string.
22, method as claimed in claim 19, both are arranged in same wherein said first string and described second string.
23, method as claimed in claim 19, wherein said first string is shared common word line with described second string.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/270,198 | 2005-11-08 | ||
| US11/270,198 US7379330B2 (en) | 2005-11-08 | 2005-11-08 | Retargetable memory cell redundancy methods |
| US11/270,410 | 2005-11-08 |
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|---|---|
| CN101331554A true CN101331554A (en) | 2008-12-24 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNA2006800467474A Pending CN101331554A (en) | 2005-11-08 | 2006-11-01 | Memory with retargetable memory cell redundancy |
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