CN101290599B

CN101290599B - System and method for checking watchdog zero clearing signal

Info

Publication number: CN101290599B
Application number: CN2008101118823A
Authority: CN
Inventors: 彭少宁; 彭鼎祥
Original assignee: Beijing Star Net Ruijie Networks Co Ltd
Current assignee: Beijing Star Net Ruijie Networks Co Ltd
Priority date: 2008-05-16
Filing date: 2008-05-16
Publication date: 2011-09-14
Anticipated expiration: 2028-05-16
Also published as: CN101290599A

Abstract

The invention relates to a system and a method for detecting reset signals of watchdogs. The system comprises a maximum register, a minimum register, a statistic module and an alarm indication module, wherein the statistic module detects and acquires the pulse width of a watchdog signal, and compares the pulse width with a maximum pulse width value and a minimum pulse width value; the alarm indication module sends out an alarm indication signal under the circumstance that the pulse width is more than the maximum pulse width value or less than the minimum pulse width value. The method comprises the following steps of acquiring the pulse width in a watchdog reset signal, comparing the pulse width with the preset maximum pulse width value and the minimum pulse width, sending out the alarm indication signal under the circumstance that the pulse width is more than the maximum pulse width value or less than the minimum pulse width value. The method ensures that the system can detect the reset signals of all watchdogs, and greatly simplifies the operation of detecting the reset signals of all watchdogs.

Description

Detect the system and method for watchdog zero clearing signal

Technical field

The present invention relates to the hardware watchdog signal detection technique, relate in particular to a kind of system and method that detects watchdog zero clearing signal.

Background technology

Technology is modal Anti-Jamming Technique to house dog (Watch Dog Timer is called for short WDT), but house dog is actually the timer conter of a zero clearing.When timer conter when external circuit is realized, is hardware watchdog with central processing unit chip (Central Processing Unit is called for short CPU); When timer conter is realized with cpu chip timer internal or counter, be software watchdog.

Hardware watchdog has reset terminal and two ports of timing clear terminal, when protected cpu system moves just often, it is watchdog zero clearing signal (being the WDI signal) that protected system constantly send variation level to the timing clear terminal, guarantee that WatchDog Timer by zero clearing in time, can not overflow the generation reset signal; When the operation of protected system is broken down, can not in time send WDI signal, house dog zero clearing in time to the timing clear terminal; timer is overflowed; thereby the reset terminal of house dog produces reset signal and sends to protected system, and protected system restarts.

In order to guarantee that CPU can carry out effective zero clearing to the house dog counter, the maximum pulse of WDI signal (is designated as T for ease of description _{WDI_Max}) must overflow the time less than the minimum of house dog and (be designated as tt for ease of description _Min), the minimum pulse width of WDI signal (is designated as T for ease of description _{WDI_Min}) must (be designated as tw greater than the minimum value that watchdog chip requires for ease of description _Min), and the WDI signal realizes that by interruption variation level drives by CPU, so the existence of the pulse width of WDI signal is uncertain, it is bigger to fluctuate, and need detect the WDI signal.

In the prior art, the WDI signal mainly detects by oscillograph.A kind of is directly to measure the WDI signal voltage by analog oscilloscope, and by from left to right passing the electron beam of oscillograph screen, describes change in voltage in vertical direction.A kind of is a series of sample values of catching the WDI signal waveform by digital oscilloscope, and sample value is stored, and the storage limit can be depicted waveform for the sample value of accumulative total, subsequently, and the digital oscilloscope reconfiguration waveform.

The defective that detects the WDI signal by oscillograph is: because detected all the WDI signal pulses of oscillograph storage, and oscillographic storage space is very little, oscillograph can only carry out segmentation and detect and store, and causes producing intersegmental interval, makes the WDI signal at intersegmental interval can not get detecting.

Summary of the invention

The objective of the invention is to propose a kind of system and method that detects watchdog zero clearing signal, to guarantee that watchdog zero clearing signal can both be detected.

For achieving the above object, the invention provides a kind of system that detects watchdog zero clearing signal, comprising:

Maximum register is used for the maximum pulse width value of storing predetermined watchdog zero clearing signal;

Minimum register is used for the minimum pulse width value of storing predetermined watchdog zero clearing signal;

Statistical module, be used for changing by the level that detects watchdog zero clearing signal, under the constant situation of the level of watchdog zero clearing signal, obtain the pulse width of watchdog zero clearing signal, and described pulse width and described maximum pulse width value, minimum pulse width value are compared;

The alarm indicating module, be used for described pulse width greater than described maximum pulse width value or situation less than the minimum pulse width value under, indicator signal gives a warning.

For achieving the above object, the present invention also provides a kind of method that detects watchdog zero clearing signal, comprising:

Change by the level that detects watchdog zero clearing signal, under the constant situation of the level of watchdog zero clearing signal, obtain the pulse width in the watchdog zero clearing signal, and compare with predetermined maximum pulse width value, minimum pulse width;

Described pulse width greater than described maximum pulse width value or situation less than the minimum pulse width value under, send alarm indication signal.

Technique scheme by obtaining the pulse width of watchdog zero clearing signal, and compares the pulse width that obtains and maximum pulse width value, the minimum pulse width value of permission, exceeds permission in pulse width

Under the situation of scope, send alarm indication signal, the system that makes need not to preserve all pulse width values of watchdog zero clearing signal, whether just can detect watchdog zero clearing signal meets the demands, the system that guaranteed can detect all watchdog zero clearing signals, has simplified the operation that detects watchdog zero clearing signal greatly.

Below by drawings and Examples, technical scheme of the present invention is described in further detail.

Description of drawings

Fig. 1 detects the structural representation of the system embodiment one of watchdog zero clearing signal for the present invention;

Fig. 2 detects the synoptic diagram of the system embodiment two of watchdog zero clearing signal for the present invention;

Fig. 3 detects the synoptic diagram of the system embodiment three of watchdog zero clearing signal for the present invention;

Fig. 4 detects the synoptic diagram of the system embodiment four of watchdog zero clearing signal for the present invention;

Fig. 5 detects the synoptic diagram of the system embodiment five of watchdog zero clearing signal for the present invention;

Fig. 6 detects the synoptic diagram of the system embodiment six of watchdog zero clearing signal for the present invention;

Fig. 7 detects the synoptic diagram of the system embodiment seven of watchdog zero clearing signal for the present invention;

Fig. 8 detects the synoptic diagram of the system embodiment eight of watchdog zero clearing signal for the present invention;

Fig. 9 a carries out the process flow diagram that the WDI signal pulse width detects for the system embodiment that the present invention detects watchdog zero clearing signal;

Fig. 9 b detects the process flow diagram that the system embodiment of watchdog zero clearing signal is carried out data statistics for the present invention;

Figure 10 detects the process flow diagram of the method embodiment of watchdog zero clearing signal for the present invention.

Embodiment

Fig. 1 detects the structural representation of the system embodiment one of watchdog zero clearing signal for the present invention, system comprises: statistical module 11, maximum register 12, minimum register 13 and alarm indicating module 14, and maximum register 12 is used for the maximum pulse width value of storing predetermined watchdog zero clearing signal; Minimum register 13 is used for the minimum pulse width value of storing predetermined watchdog zero clearing signal; For ease of describing, maximum register 12, minimum register 13 are designated as R respectively _Max, R _Min, then the maximum pulse width value is R _MaxValue; The minimum pulse width value is R _MinValue, can be with maximum value register R _MaxWith minimum value register R _MinBe set to representative value, for example maximum value register is set to 0.9 second, and minimum value register was set to for 100 nanoseconds; Statistical module 11 is connected with watchdog zero clearing signal output terminal in the circuit under test, detects the pulse width of watchdog zero clearing (WDI) signal that obtains output, and with described pulse width and described R _Max, R _MinCompare; The alarm indicating module 14 can be hummer or pilot lamp, in described pulse width greater than described R _MaxOr less than R _MinUnder the situation of value, the indicator signal that gives a warning sounds the alarm or LED light is lighted as hummer.

The system of present embodiment detects by 11 pairs of watchdog zero clearings of statistical module (WDI) signal, is R with all pulse widths of WDI signal and the preset range that obtains _Max, R _MinCompare, the problem of having avoided the WDI signal not detected has fully guaranteed that all pulse widths of WDI signal can both be detected; And system is by alarm indicating module 14, and the pulse width of the WDI signal that can send at circuit to be detected is greater than predetermined R _MaxValue or less than predetermined R _MinUnder the situation of value, the indicator signal that gives a warning has guaranteed the accuracy that detects, and has simplified the detecting operation of WDI signal greatly, helps the hardware watchdog reset signal of typical products in mass production is detected.Statistical module 11, maximum register 12 and minimum register 13 can pass through CPLD (ComplexProgrammable Logic Device simultaneously, be called for short CPLD) or FPGA (FieldProgrammable Gate Array, be called for short FPGA) realize, lowered the cost that detects the WDI signal greatly.

In the foregoing description, statistical module 11 can comprise detecting device, counter, counter register and comparer; Detecting device is used to detect the level variation of WDI signal; Detecting watchdog zero clearing signal at described detecting device does not have under the situation of level variation, and counter carries out counting statistics to the pulse width of WDI signal, supposes that counter variable is R _{WDI_cunter}, promptly do not have under the situation of level variation R at the WDI signal _{WDI_cunter}Constantly add 1, change, at this moment R up to WDI signal generation level _{WDI_cunter}Value be the pulse width of WDI signal; Detecting watchdog zero clearing signal at described detecting device has under the situation of level variation, counter register storage R _{WDI_cunter}Value, suppose that the counter register variable is R _{WDI_width}, this moment R _{WDI_width}Value equal R _{WDI_cunter}Value; Detecting device generation simultaneously one is enable signal relatively, supposes that this signal is WDI_rdy, then preserves R _{WDI_cunter}Value the time, WDI_rdy is changed to high level, represent current R _{WDI_width}Value effective, promptly current R _{WDI_width}Value be the current pulse width of WDI signal, as yet not with R _MaxValue, R _MinValue compares, and at this moment, comparer is that high level is that described detecting device detects watchdog zero clearing signal and has under the situation that level changes at WDI_rdy, is R with described pulse width _{WDI_width}Value and described R _MaxValue, R _MinValue compares.

In the foregoing description, system also can further comprise big register, less register and output module; Big register is used for storing the pwm value of the maximum that the WDI signal is detected, and this variable is designated as R _{WDI_Max}Less register is used for storing the pwm value of the minimum that the WDI signal is detected, and this variable is designated as R _{WDI_Min}Described statistical module also is used for R _{WDI_width}With the pwm value in described big register, the less register be R _{WDI_Max}, R _{WDI_Min}, compare; And at described R _{WDI_width}Greater than described R _{WDI_Max}Situation under, use described R _{WDI_width}Replace the pwm value in the described big register, be about to R _{WDI_width}Value give R _{WDI_Max}At described R _{WDI_width}Less than described R _{WDI_Min}Situation under, use described R _{WDI_width}Replace the pwm value in the described less register, be about to R _{WDI_width}Value give R _{WDI_Min}Before the detection, store initial value in big register, the less register, store 0 in the big register, i.e. R _{WDI_Max}Initial value be set to 0, storing predetermined maximal value in the less register, i.e. R _{WDI_Min}Initial value be set to R _MaxValue; When detecting the WDI signal, with current detection to pulse width compare with value in big register, the less register, acquisition is by the maximum pulse value and the minimum pulse width value of current WDI signal, and the value in promptly big register, the less register changes; Value in the described big register of output module output, the less register offers computing machine (PC) or LCD and shows, so just can obtain maximum, the minimum pulse width value of WDI signal in real time.Big register, less register also can pass through CPLD, FPGA to be realized.

In the foregoing description, system can with circuit common-battery to be detected source altogether, the value in maximum register, minimum register, big register and the less register is R _Max, R _Min, R _{WDI_Max}, R _{WDI_Min}Can be solidificated in when dispatching from the factory in the register, just begin after system powers on to detect, deenergization just stops to detect.

The system that detects watchdog zero clearing signal can communicate with PC, by the system works of PC control by the detection watchdog zero clearing signal.At this moment, the system that detects watchdog zero clearing signal can further comprise serial port module, joint test dynamic group interface (Joint Test Action Group, be called for short JTAG) or serial bus interface interface modules such as (Universal Serial Bus are called for short USB).As shown in Figure 2, Fig. 2 detects the structural representation of the system embodiment two of watchdog zero clearing signal for the present invention, and the system 10 that detects watchdog zero clearing signal comprises serial port module 16, and the WDI signal end of system 10 connects the WDI signal of CPU in the circuit under test 2; System 10

Signal connects watchdog chip

Signal; And system 10 and circuit under test 2 be the common-battery source altogether; The serial ports of system 10 connects the serial ports of PC3, and PC 3 communicates with system 10 by serial port module 16, reads maximum, the minimum pulse width value of the WDI signal of circuit under test 2.As shown in Figure 3, Fig. 3 detects the structural representation of the system embodiment three of watchdog zero clearing signal for the present invention, and system 10 can comprise the jtag interface module, communicates by jtag interface module and PC 3; System 10 can comprise inter-IC bus interface (Inter Integrated-circuit BUS is called for short iic bus), and as shown in Figure 4, Fig. 4 detects the structural representation of the system embodiment four of watchdog zero clearing signal for the present invention; In actual use, system 10 also can be connected with other main control equipments 5 such as CPU, at this moment can connect by serial ports, also can connect main control equipment 5 by general purpose I/O of iic bus interface or CPU.

Like this, the output module in the foregoing description can be interface module, and PC is R by serial port module, jtag interface or USB interface from the value that the system that detects watchdog zero clearing signal reads big register and the less register _{WDI_Max}, R _{WDI_Min}Value, interface module also can receive and carry out detection initiation command, the detection of PC transmission and cease and desist order, the order that described statistical module receives according to described interface module begins or stops to detect, and the system that promptly detects watchdog zero clearing signal can detect under PC control.System also can further comprise the predicted time register, is used to store the predetermined detection time of watchdog zero clearing signal; The value of predicted time register is provided with by interface module by PC, and interface module receives and carry out the order that is provided with of PC, and the value of described predicted time register is set, and is designated as R _TimeStatistical module also is used for detecting in the time in described predetermined detection, relatively, obtain maximum, the minimum pulse width value of WDI signal, when exceed value in the predicted time register detection time, stop automatically detecting.For example with predetermined detection time register R _TimeBe set at zero, just do not limit detection time.

When the nucleus module in the system 10 is realized with FPGA, because FPGA is the very high novel high-performance programmable logic device (PLD) of a kind of integrated level, can finish complicated circuit function, be applicable to high speed, highdensity high-end digital logic circuit design field.Therefore FPGA is after all functions that realized detector C PLD module, and also having enough resource redundancies can use as other logic, so system 10 can obtain complex interface, and for example network interface etc. is realized remote detection and Long-distance Control.As shown in Figure 5, Fig. 5 detects the structural representation of the system embodiment five of watchdog zero clearing signal for the present invention; System 10 can communicate by network interface and remote terminal 6, realizes the remote detection and the Long-distance Control of 6 pairs of systems 10 of remote terminal.

The concrete operations that detect the WDI signal by PC control system 10 can comprise:

With the WDI of detection system signaling interface and WDT and

Signal connects, and powers on;

The back detection system that powers on will begin the WDI signal is detected with default setting automatically.WDI signal detecting result when the user can observe the starting up;

The user can move the serial ports application program, by register order is set each register value in the register space is set;

Operation serial ports application program begins to detect WDT by detecting initiation command;

If be provided with the predetermined detection time register, then detection system will arrive predetermined detection in detection time and stop after the time detecting.At this moment can check testing result by alarm indicator, also can on PC, obtain testing result by reading result command;

If the predetermined detection time register is not set, then detection system will be in detected state always.At this moment can send to detect and cease and desist order, stop detection system is checked testing result then to the detection of WDT;

Another WDI signal is being detected, perhaps same WDI signal is being carried out needing to send and detecting initiation command to the statistics zero clearing before a new round detects.Jump to then and carry out register and step is set and begins a new round and detect; If register no longer is set, then jump to operation serial ports application program step, utilize same register that a beginning new round is set and detect.

Under the situation of no PC, output module can be liquid crystal display (Liquid Crystal Display is called for short LCD) driver module, the pwm value in described big register, the less register is sent to the LCD device show.The LCD driver module comprises display interface device module and numerical value modular converter, and wherein, the interface sequence of the concrete LCD device of display interface device module basis requires to finish the driving to the LCD device, and the numerical value that will show sends to the LCD device and shows.The R that the numerical value conversion module provides statistical module _{WDI_Max}And R _{WDI_Min}Count value is scaled time numerical value, and the detection system of the embodiment of the invention adopts the 100MHz operating clock, and therefore the formula that converts is:

T _{WDI_Max}=R _{WDI_Max}* 10 nanoseconds=R _{WDI_Max}* 10 ^-8Second

T _{WDI_Min}=R _{WDI_Min}* 10 nanoseconds=R _{WDI_Min}* 10 ^-8Second.

Here the LCD device also can be used as the part of the system that detects watchdog zero clearing signal, makes system itself can show WDI input situation, and as shown in Figure 6, Fig. 6 detects the synoptic diagram of the system embodiment six of watchdog zero clearing signal for the present invention; In the system 10, alarm is designated as LED light, and can be with testing result R _{WDI_Max}And R _{WDI_Min}Show by LCD (Liquid CrystalDisplay is called for short LCD), under no PC condition, observe testing result to make things convenient for the user.

The system that detects watchdog zero clearing signal can further comprise manual operation switch, by the system of manual operation control detection watchdog zero clearing signal.Manual operation switch can comprise the detection reset switch, detect beginning switch and statistics end switch, detects reset switch with described counter O reset; Detection beginning switch is used to start described detecting device to begin to detect; The statistics end switch is used to stop described detecting device and detects.

The system that detects watchdog zero clearing signal can comprise further that also register is provided with switch, is used to be provided with described R _Max, R _MinAs shown in Figure 7, Fig. 7 detects the synoptic diagram of the system embodiment seven of watchdog zero clearing signal for the present invention; Described register is provided with switch and can be two groups of wire jumpers, is used for being provided with R respectively _Max, R _MinValue.When detecting under no PC condition, the register setting of detection system 10 can be adopted outside wire jumper selection mode, realizes the stepping setting.Two groups of wire jumpers are arranged among Fig. 7: wire jumper 71 is set maximum value register and minimum value register is provided with wire jumper 72.Maximum value register 71 is provided with the branch fourth gear, is respectively: 0.9 second, 1.6 seconds, 2.0 seconds and 2.5 seconds; Minimum value register 72 is provided with the branch fourth gear, is respectively: 100 nanoseconds, 200 nanoseconds, 300 nanoseconds and 400 nanoseconds.

Manual operation detects specifically can comprising of WDI signal:

With the WDI of detection system signaling interface and circuit under test and

Signal connects, and powers on;

After powering on, detection system will begin the WDI signal is detected with default setting automatically.WDI signal detecting result when the user can observe the starting up.

By detecting the beginning switch, detection system will begin the input of a new round.

By detecting shutdown switch, detection system will stop present input.

By detecting reset switch, detecting device will be to the statistics zero clearing.

The system that detects watchdog zero clearing signal also can possess PC communication and manual operation function simultaneously, and as shown in Figure 8, Fig. 8 detects the synoptic diagram of the system embodiment eight of watchdog zero clearing signal for the present invention; In the present embodiment, the system 10 that detects watchdog zero clearing signal mainly comprises CPLD module, alarm indication, signaling interface and four parts of operating switch, adopts 100MHz clock source as operating clock.Clock period was 10 nanoseconds, and therefore the detection to minimum pulse width and maximum pulse can be as accurate as for 10 nanoseconds; Adjust measuring accuracy if desired, can change, reached for 5 nanoseconds, then operating clock can be replaced by 200MHz as the needs precision to operating clock.Wherein, CPLD module 17 is the core of system, be mainly used to realize the function of modules such as statistical module 11, register space 15 and serial port module 16, register space 15 can be used to realize maximum register, minimum register, big register, less register and predicted time register, preserves R _Min, R _Max, R _{WDI_Max}, R _{WDI_Min}And R _TimeInformation such as value so that the data processing of statistical module 11.

Serial port module 16 realizes that serial interface drives, so that PC is provided with and operates by 31 pairs of systems of application program.Serial port module 16 comprises interface sub-module and order submodule two parts.Interface sub-module realizes basic serial communication; The order submodule is realized parsing and the execution to serial port command, and serial port command comprises:

Register is provided with order, is used for realizing the register assignment to register space;

Detect initiation command, be used for R statistical module _{WDI_Max}And R _{WDI_Min}Zero clearing, and initiation is to the detection of WDT;

Detection is ceased and desisted order, and is used to stop the detection to WDT;

Read result command, be used to read R when Pretesting _{WDI_Max}And R _{WDI_Min}Value.

Alarm indicating module 14 shows testing result, if the pulse width maximum count value R of WDI signal _{WDI_Max}With least count value R _{WDI_Min}Surpass predetermined scope, then light light emitting diode (LightEmitting Diode is called for short LED) pilot lamp.

Alarm indicating module 14 is used to show testing result, if the pulse width maximum count value of WDI signal and least count value surpass predetermined scope, then lights light emitting diode (Light Emitting Diode is called for short LED) pilot lamp.Signaling interface provides the interconnect port of detecting device and outer watchdog chip 21, CPU 22 signals, mainly comprises the port on WDI signal, rs 232 serial interface signal and power supply and ground.

Detect reset switch 41, detect operating switchs such as beginning switch 42 and statistics end switch 43, be convenient to manual operation.Wherein, detection reset switch 41 is used for the zero clearing to statistics, just to R _{WDI_cunter}Zero clearing is so that begin new detection; Detect beginning switch 42 and be used to start a new detecting operation; Statistics end switch 43 is used to stop a detecting operation, so that read testing result.

Among the said system embodiment, the operating process of statistical module 11 is divided into two parts: the WDI signal pulse width detects, data statistics.Wherein the WDI signal pulse width detects, and shown in Fig. 9 a, the concrete operations step is as follows:

Step 101, judgement are carried out and are detected initiation command or reset signal

Whether effective, if then execution in step 102; And, if

Effectively, then wait for

After invalid, the pulse width of a beginning new round detects; Detect initiation command if carry out, the pulse width that then begins a new round immediately detects;

Step 102, counter R _{WDI_counter}Zero clearing;

Step 103, judge whether the WDI signal does not have level and change, change that then execution in step 104 if the WDI signal has level; Otherwise, execution in step 104;

Step 104, counter R _{WDI_counter}Counting;

If step 105 WDI signal has level to change, then counter R _{WDI_counter}Value be saved in R _{WDI_width}In the register, and WDI_rdy is changed to high level, represents current R _{WDI_width}Effectively;

Step 106, whether judge detection time, or do not receive and stop sense command greater than the predetermined detection time, if, then no longer initiate new round pulse width and detect, enter waiting status; Otherwise counter R _{WDI_counter}Zero clearing continues to detect the WDI pulse width.

The data statistics operation is as Fig. 9 b, and the concrete operations step is as follows:

Step 201, judge whether to receive and detect initiation command or whether system powers on, detect initiation command or system powers on execution in step 202 if receive;

Step 202, with R _{WDI_Max}And R _{WDI_Min}Initialization, i.e. R _{WDI_Max}Be initialized as zero; R _{WDI_Min}Be initialized as maximal value;

Step 203, to judge whether to detect WDI_rdy be high level, is high level if detect WDI_rdy, promptly represents R _{WDI_width}Effectively, then execution in step 204;

Step 204, WDI_rdy is changed to low level, register R has been obtained in expression _{WDI_width}In the pulse width statistics; And comparison R _{WDI_width}With R _{WDI_Max}If, R _{WDI_width}Greater than R _{WDI_Max}, then execution in step 205; Otherwise, execution in step 206;

Step 205, with R _{WDI_width}Value preserve into R _{WDI_Max}

Step 206, comparison R _{WDI_width}With R _{WDI_Min}If, R _{WDI_width}Less than R _{WDI_Min}, then execution in step 207; Otherwise, execution in step 208;

Step 207, with R _{WDI_width}Value preserve into R _{WDI_Min}

Step 208, judgement R _{WDI_Max}And R _{WDI_Min}Value whether no longer be initial value and surpass preset range, if R _{WDI_Max}And R _{WDI_Min}Value no longer be initial value, and surpass preset range, then execution in step 209, otherwise, execution in step 210;

Step 209, the enable signal Alarm that will alarm indicating module are changed to high level;

Step 210, whether judge detection time,, then carry out the data statistics operation of no longer initiating a new round if arrive detection time to the schedule time; If do not arrive detection time, then initiate new round data statistics operation.

Figure 10 is the process flow diagram that the present invention detects the method embodiment of watchdog zero clearing signal, comprising:

Whether the pulse width that step 301, statistical module 11 obtains in the WDI signals, and compare with predetermined maximum pulse width value, minimum pulse width judges whether the WDI signal meets the demands, promptly within the scope of maximum pulse width value, minimum pulse width; If do not exist, represent that then the WDI signal does not meet the demands, execution in step 302;

Step 302, the alarm indicating module 14 described pulse width greater than described maximum pulse width value or situation less than the minimum pulse width value under, send alarm indication signal.

Said method embodiment also can comprise, the maximum pulse value R of the watchdog zero clearing signal of system's 10 outputs in testing process _{WDI_Max}, minimum pulse width value R _{WDI_Min}Show to the LCD device, or output to PC.

Said method embodiment can comprise that also by PC or register switch being set is provided with maximum pulse width value, minimum pulse width value, to satisfy different detection demands.

The system of the detection watchdog zero clearing signal that provides among the said system embodiment not only volume is little, in light weight, and lower, easy to use to the test environment requirement, can be widely used in the product sampling Detection stage under the volume production situation.Use the system of above-mentioned detection watchdog zero clearing signal simultaneously, avoided loaded down with trivial details oscillograph setting, only need in the circuit-under-test system, to reserve in advance to detect interface, just can pass through interface joint detection system.Through register setting intuitively or register is not set and adopts default setting, the start detection operation can be finished the detection to signal, has simplified detecting operation greatly.The system of above-mentioned detection watchdog zero clearing signal can observe watchdog zero clearing signal for a long time, thereby can detect the maximum pulse of WDI, has avoided the data of storage magnanimity again.The system of above-mentioned detection watchdog zero clearing signal provides the connecting interface with main control equipments such as PC, flexible operation.The user can be provided with by the application program on the PC and operate flexibly, and obtains testing result by application program.The system of above-mentioned detection watchdog zero clearing signal provides the statistics reset switch, and has visual display module, and the user can also can detect under the situation that does not have PC to connect easily.The user can set the working method of detection system flexibly by register, both can set maximum detection number of times, can not set again and detect number of times and artificially definite detection time.

One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of programmed instruction, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.

It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.

Claims

1. a system that detects watchdog zero clearing signal is characterized in that, comprising:

2. the system of detection watchdog zero clearing signal according to claim 1 is characterized in that, described statistical module comprises:

Detecting device is used to detect the level variation of watchdog zero clearing signal;

Counter, being used for detecting watchdog zero clearing signal at described detecting device does not have under the situation of level variation, counts, and obtains the pulse width of watchdog zero clearing signal;

Counter register, being used for detecting watchdog zero clearing signal at described detecting device has under the situation of level variation, stores described pulse width;

Comparer, being used for detecting watchdog zero clearing signal at described detecting device has under the situation of level variation, and described pulse width and described maximum pulse width value, minimum pulse width value are compared.

3. the system of detection watchdog zero clearing signal according to claim 1 is characterized in that, also comprises:

Big register is used for storing the pwm value of the maximum that watchdog zero clearing signal is detected;

Less register is used for storing the pwm value of the minimum that watchdog zero clearing signal is detected;

Output module is used for exporting the described value of register, less register greatly;

Described statistical module also is used for described pulse width and the described pwm value of register, less register are greatly compared; And under the situation of described pulse width, replace described with described pulse width than the pwm value in the big register greater than the pwm value in the described big register; Under the situation of described pulse width, replace pwm value in the described less register with described pulse width less than the pwm value in the described less register.

4. the system of detection watchdog zero clearing signal according to claim 3, it is characterized in that, described output module is an interface module, be used for receiving and carry out register order is set, the value of described maximum register, minimum register is set, and the described initial value of register, less register greatly, and in the process that described statistical module detects, export the pwm value in described big register, the less register.

5. the system of detection watchdog zero clearing signal according to claim 4, it is characterized in that, described interface module also is used for receiving and execution detects initiation command, detects and cease and desist order, and described statistical module also is used for beginning or stop to detect according to the order that described interface module receives.

6. the system of detection watchdog zero clearing signal according to claim 4 is characterized in that, also comprises:

The predicted time register, the predetermined detection time that is used to store watchdog zero clearing signal;

Described interface module also is used to receive and carry out the value that described predicted time register is set;

Described statistical module also is used for detecting in the time in described predetermined detection, compares.

7. the system of detection watchdog zero clearing signal according to claim 4 is characterized in that, described interface module is serial port module, joint test dynamic group interface JTAG, serial bus interface or inter-IC bus IIC interface.

8. the system of detection watchdog zero clearing signal according to claim 3 is characterized in that, described output module is the liquid crystal display driver module, is used for that the described pwm value of register, less register is greatly sent to LCD and shows; Described system comprises that also LCD is used to the value that shows that described liquid crystal display driver module sends.

9. the system of detection watchdog zero clearing signal according to claim 2 is characterized in that, also comprises:

Detect reset switch, be used for described counter O reset;

Detect the beginning switch, be used to start described detecting device and begin to detect;

The statistics end switch is used to stop described detecting device and detects.

10. the system of detection watchdog zero clearing signal according to claim 9 is characterized in that, also comprises:

Register is provided with switch, is used to be provided with the value of described maximum register, minimum register.

11. the system of detection watchdog zero clearing signal according to claim 10 is characterized in that, it is two groups of wire jumpers that described register is provided with switch, is used for being provided with the value of described maximum register, minimum register respectively.

12. the system according to each described detection watchdog zero clearing signal among the claim 1-11 is characterized in that, described alarm indicating module is pilot lamp or hummer.

13. a method that detects watchdog zero clearing signal is characterized in that, comprising:

14. the method for detection watchdog zero clearing signal according to claim 13 is characterized in that, also comprises:

The maximum pulse value of the watchdog zero clearing signal of output in testing process, minimum pulse width value.

15. the method for detection watchdog zero clearing signal according to claim 13 is characterized in that, also comprises:

Described maximum pulse width value, minimum pulse width value are set.