CN101276536B - Image display unit and method of driving the same - Google Patents
Image display unit and method of driving the same Download PDFInfo
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Abstract
The image display unit includes a cathode electrode driving portion which applies a cathode electrode applied voltage to a cathode electrode, a gate electrode driving portion which sequentially applies a gate electrode applied voltage to a gate electrode according to an inputted shift clock for gate electrode selection, an abnormality detecting portion which detects at least either an input abnormality in the shift clock for gate electrode selection or an operation abnormality in a shift register, and a three-state buffer which controls the gate electrode applied voltage in the case where at least either of the abnormalities is detected, so that a potential difference between the cathode electrode and the gate electrode is equal to or lower than a cutoff voltage.
Description
The explanation of dividing an application
The Chinese patent application No.200510098494.2 that the application is is on September 6th, 2005 applying date, be entitled as " image-display units and drive the method for this image-display units " divides an application.
Technical field
The present invention relates to come the image-display units of display image by selecting and drive the pixel that is arranged in matrix form, and the method that drives this image-display units.
Background technology
In recent years, as being used for one of two-d display panel of image-display units, developed field-emitter display (hereinafter referred to as FED).Because FED has so a kind of principle, the i.e. electron impact light emission surface launched of electron emission source from vacuum, on this light emission surface, disposed light-emitting layer, so that light is launched just as the situation in the cathode ray tube (CRT), so the flat-panel monitor that can realize having high brightness and high-contrast.But in CRT, single electron emission source is deployed in usually from light emission surface tens or tens centimetres of positions far away.On the other hand, FED has different basic structure, and promptly a plurality of electron emission sources are being aligned to matrix form in several millimeters far away position approximately from light emission surface.
Basic structure and the operation of typical FED below will be described now.FED comprises field emission type negative electrode as electron emission source, in the face of the gate and the anode electrode of this field emission type negative electrode, this anode electrode on a side opposite with that side of placing the field emission type negative electrode to gate, and coated light-emitting layer.The field emission type negative electrode comprises it for example being the negative electrode equipment (cold cathode device) of cone shape, and is deployed in the cathode electrode on the bottom surface of negative electrode equipment.When gating-cathode voltage Vgc was applied between the cathode electrode that faces with each other and the gate, electronics was emitted from negative electrode equipment, with the light-emitting layer of impinge anode electrode.Generally speaking, gate is arranged on the line direction (Row), and cathode electrode is arranged on the column direction (Column).Negative electrode equipment is deployed in their each intersection point place, so that arrange pixel with matrix form.Cathode electrode is connected to the cathode electrode drive part, and gate is connected to the gate drive part.The pixel that is arranged in matrix form is to be driven by above drive part in the following manner.
By will be from the scanning voltage Vrow of gate drive part as selecting signal to be applied to gate in the target line, to be applied to all cathode electrodes from the pixel voltage Vcol that is used for row of cathode electrode drive part simultaneously, carry out the driving of pixel.When order is carried out this operation on all row, show a screen image.Therefore, be created between gate and the cathode electrode with respect to the potential difference (PD) of cathode electrode (be gating-cathode voltage Vgc (=Vrow-Vcol)), and electronics since potential difference (PD) from negative electrode equipment, emit.The electronics process gate of launching, and attracted to the anode electrode that has applied high voltage HV, with the impinge anode electrode.At this moment, utilize the energy by the bump ejected electron, light-emitting layer is luminous.Thereby, show a screen image.
For example, technology about this FED is disclosed in the uncensored public announcement of a patent application No.2001-324955 of Japan.
Summary of the invention
As mentioned above, typical case FED has the matrix wiring structure that is used to apply the voltage that drives pixel, and have a kind of like this structure, pixel voltage is imported from the cathode electrode drive part in this structure, and scanning voltage is imported in proper order from the gate drive part.Scanning voltage generally produces in the gate drive part, is output according to the scan clock from the time schedule controller input then.Therefore, when pixel is driven, owing to reasons such as noises, scan clock periodically is not input in the gate drive part, and under the situation of the phase shifts of scan clock, the light of sweep trace (following the line that direction (generally speaking being the horizontal direction on the screen) is extended) is longer than normal time launch time, and therefore the light of emission is sent out other sweep trace height of brightness ratio.Therefore, occur in the problem that generates the abnormal show of high brightness line on the screen in the horizontal direction.
In addition, because unusual etc. former thereby interim in CPU or the peripheral circuit or suspend for a long time is input to scan clock under the situation of gate drive part, perhaps under the situation that the gate drive part is damaged, the scanning that shows may not be performed, and voltage may only be applied on the specific row constantly.In the case, not only on screen, generate the high brightness line in the horizontal direction, and the temperature that is continuously applied the parts of voltage become be higher than normal, thereby may take place because the display characteristic of the negative electrode equipment that loss causes descends or damages the such pixel damage of resistive layer on the bottom surface that is deployed in negative electrode equipment.
Consider the problems referred to above, be desirable to provide and can prevent because abnormal show, display characteristic former thereby that cause such as the damage of unusual scan clock, gate drive part descend and the image-display units of pixel damage, and the method that drives this image-display units.
According to one embodiment of present invention, provide a kind of image-display units, comprising:
(A) a plurality of first electrodes and a plurality of second electrode, these a plurality of first electrodes and a plurality of second electrode extend on column direction and line direction respectively, so that intersect each other at each locations of pixels place and face;
(B) first electrod driving device, it applies pixel voltage based on picture signal to a plurality of first electrodes;
(C) second electrod driving device, its scan clock according to input applies scanning voltage in proper order to a plurality of second electrodes, the pixel column that this scanning voltage selection will drive;
(D) abnormal detector, it detects in the operation exception in unusual and second electrod driving device of input in scan clock at least one; And
(E) scanning voltage control device; gated sweep voltage under at least one situation about being detected in the operation exception in unusual or second electrod driving device of its input in scan clock is equal to or less than predetermined value so that make with respect to a plurality of first electrodes of a plurality of first electrodes and the potential difference (PD) between a plurality of second electrode.
In the case, " predetermined value " cut-off voltage of preferably when minimum brightness shows (so-called black demonstration), applying; But the present invention is not limited to this, and this predetermined value can be the voltage a little more than cut-off voltage.In addition, " in the scan clock unusual " is meant that scan clock is not transfused to by correct sequential, and comprises under the situation that the input of situation that the input of scan clock suspended fully, scan clock suspended temporarily and situation that the phase place of scan clock is moved.In addition, " operation exception in second electrod driving device " is meant that second electrod driving device do not carry out predetermined normal running, and for example comprise that although scan clock is transfused to, scanning voltage apply the situation that is not moved to next second electrode from one second electrode.
As specific example, abnormal detector comprises following element.
(1) under the situation that the input in scan clock is detected unusually, abnormal detector comprises: capacitor; Charging circuit, it is to this capacitor charging; Discharge circuit, its input according to scan clock is discharged to this capacitor; And comparator circuit, its charging voltage with this capacitor is compared with reference voltage, so that the input that detects in the scan clock when charging voltage surpasses reference voltage is unusual.
In the case, " comparison " mean the level of the charging voltage of capacitor compared with the level of reference voltage.
(2) under the situation of the operation exception in detecting second electrod driving device, more specifically, under the situation of the operation exception in the shift register that detects one of element as second electrod driving device, abnormal detector comprises comparator circuit, this comparator circuit is compared vertical synchronizing signal with the final level output of shift register, and when comparative result shows that the final level output of vertical synchronizing signal and shift register does not match, detect the operation exception in second electrod driving device.
In the case, above-mentioned shift register has the function that the vertical synchronizing signal of input is shifted in proper order according to scan clock.In addition, in the case " comparison " mean the level of vertical synchronizing signal compared with the level of the final level output of shift register.
In order to make the scanning voltage control device can make that potential difference (PD) is equal to or less than predetermined value, can consider that following technology is as specific example.
(1) output of the scanning voltage in disconnection second electrod driving device
In the case, " disconnection " mean when second electrod driving device is operated and to turn-off the output of scanning voltage to second electrode.
(2) disconnect the output that the power supply of electric power is provided to second electrod driving device.
(3) reduce the output that the power supply of electric power is provided to second electrod driving device.
According to one embodiment of present invention, provide a kind of method that drives image-display units, this method may further comprise the steps:
(A) arrange a plurality of first electrodes and a plurality of second electrode, these a plurality of first electrodes and a plurality of second electrode extend on column direction and line direction respectively, so that intersect each other at each locations of pixels place and face;
(B) apply pixel voltage based on picture signal to a plurality of first electrodes;
(C) scan clock according to input applies scanning voltage in proper order to a plurality of second electrodes, the pixel column that this scanning voltage selection will drive;
(D) detect in the operation exception in unusual and second electrod driving device of input in the scan clock at least one; And
(E) input in scan clock reduces scanning voltage unusually or under at least one situation about being detected in the operation exception in second electrod driving device, so that be equal to or less than predetermined value with respect to a plurality of first electrodes of a plurality of first electrodes and the potential difference (PD) between a plurality of second electrode.
At image-display units according to an embodiment of the invention with drive in the method for image-display units; during in the operation exception in unusual or second electrod driving device of the input in detecting scan clock at least one; control is applied to the scanning voltage of second electrode from second electrod driving device, so that make potential difference (PD) be equal to or less than predetermined value.Therefore, can prevent when taking place above-mentionedly when unusual, the voltage that surpasses predetermined value is continuously applied the pixel that second electrod driving device is chosen.
At image-display units according to an embodiment of the invention with drive in the method for image-display units; when in scan clock, taking place to import unusual or in second electrod driving device, operation exception taking place; reduction is applied to the scanning voltage of second electrode from second electrod driving device; therefore so that make potential difference (PD) be equal to or less than predetermined value, can prevent owing to be used for abnormal show, display characteristic decline and the pixel damage that the unusual input of the shift clock that gate selects causes.
From following description, of the present invention other will more completely display with further target, feature and advantage.
Description of drawings
Fig. 1 is the schematic block diagram according to the image-display units of the first embodiment of the present invention;
Fig. 2 is along the sectional view perpendicular to the obtained image display in the plane of X-axis and Y-axis;
Fig. 3 is the skeleton view of image display;
Fig. 4 is the schematic block diagram of gate drive part and abnormality detection part;
Fig. 5 is the schematic block diagram of power supply;
Fig. 6 is the figure of the electron emission characteristic of image-display units;
Fig. 7 A to 7G is the oscillogram of the main signal of device drives part;
Fig. 8 A and 8B are the oscillograms of the voltage that is applied to cathode electrode of X-direction;
Fig. 9 A to 9E is the oscillogram that is used to describe the operation of abnormality detection part under the normal condition;
Figure 10 A to 10C is the oscillogram that is used to describe comparative example;
Figure 11 A to 11E is the oscillogram that is used to describe the operation of abnormality detection part under the abnormal conditions;
Figure 12 is used to describe the process flow diagram that detects unusual step;
Figure 13 is gate drive part and an abnormality detection schematic block diagram partly according to a second embodiment of the present invention;
Figure 14 A to 14F is the oscillogram that is used to describe the operation of abnormality detection part under the abnormal conditions;
Figure 15 is the gate drive part of a third embodiment in accordance with the invention and the schematic block diagram of abnormality detection part;
Figure 16 A to 16E is the oscillogram that is used to describe the operation of abnormality detection part under the normal condition;
Figure 17 A to 17C is the oscillogram that is used to describe comparative example;
Figure 18 A to 18E is the oscillogram that is used to describe the operation of abnormality detection part under the abnormal conditions;
Figure 19 is used to describe the process flow diagram that detects unusual step;
Figure 20 is the schematic block diagram according to the gate drive part of the modification of second embodiment and abnormality detection part; And
Figure 21 is the schematic block diagram of the power supply shown in Figure 20.
Embodiment
Describe preferred embodiment in detail below with reference to accompanying drawing.
[first embodiment]
Fig. 1 illustrates the schematic block diagram according to the image-display units of the first embodiment of the present invention.Therefore the method that drives image-display units according to this embodiment is illustrated by the image-display units according to this embodiment, also can describe this method below.
Image-display units comprises the image display 1 that is used for display image, be used to the power supply 3 that drives the device drives part 2 of image display 1 and be used for providing to device drives part 2 electric power.Fig. 2 illustrates along the sectional view perpendicular to the obtained image display 1 in the plane of line direction (X-axis) and column direction (Y-axis).In addition, Fig. 3 illustrates the skeleton view of the part amplification of image display 1.In the present embodiment, be used as the situation of drive system as example with describing passive matrix.In the following description, " top " is meant that " end " is meant the negative direction of Z axle perpendicular to the positive dirction of the direction (Z axle) of line direction (X-axis) and column direction (Y-axis).
Image display 1 comprises a plurality of cathode electrodes 20 (first electrode), and these cathode electrodes are in the supporter 22 upper edge Y directions extensions that have perpendicular to the plane of Z axle.Resistive layer 23 is formed on (referring to Fig. 2 and 3) on each cathode electrode 20.Supporter 22, cathode electrode 20 and resistive layer 23 have been capped insulation course 24.Image display 1 comprises a plurality of gates 21, and these gates extend in insulation course 24 upper edge X-directions.In the case, arranged the cathode electrode 20 of m row, and arranged the capable gate 21 of n.Here, m and n are positive integers.When from Z-direction, the position that each cathode electrode 20 and each gate 21 intersect each other is an electron emission region 33, and each pixel is formed in the electron emission region 33.In the gate 21 and insulation course 24 in electron emission region 33, formed a plurality of holes 30 that penetrate gate 21 and insulation course 24, and negative electrode equipment 25 is deployed on the resistive layer 23, this resistive layer is deployed in the bottom in hole 30.Cathode electrode 20 and negative electrode equipment 25 are electrically connected to each other via resistive layer 23 therebetween.All elements that form on supporter 22 and the supporter 22 are generically and collectively referred to as negative electrode panel 32 (referring to Fig. 2 and 3).
As mentioned above, image display 1 is used as light-emitting layer 27 with light-emitting layer 27R, 27G and 27B, but so that color display; But, in the present embodiment,, will under the situation of not distinguishing the color in colored the demonstration, present embodiment be described in order to simplify description.
As shown in Figure 1, device drives part 2 comprises that A/D conversion portion 10, image signal processing section 11, control signal produce part 12, cathode electrode drive part 13 (first electrode driver), gate drive part 14 (second electrode driver and scanning voltage controller) and abnormality detection part 15 (anomaly detector).Power supply 3 provides necessary voltage to these elements.
Fig. 4 illustrates the particular configuration of gate drive part 14 and abnormality detection part 15.Gate drive part 14 comprises shift register 14-1 and three-state buffer 14-2.Abnormality detection part 15 comprises capacitor 15-1, charging circuit 15-2, discharge circuit 15-3 and comparator circuit 15-4.
Next, below with reference to Fig. 1 and 4 annexation between all elements of device drives part 2 is described.
The output of A/D conversion portion 10 is connected to the input of Image Information Processing part 11.The output of Image Information Processing part 11 is connected to the input that control signal produces part 12 and cathode electrode drive part 13.The output of control signal generation part 12 is connected to the input of cathode electrode drive part 13, gate drive part 14 and abnormality detection part 15.The output of abnormality detection part 15 is connected to the input of gate drive part 14.The output of cathode electrode drive part 13 and gate drive part 14 is connected to the input of image display 1.
In gate drive part 14, the input of shift register 14-1 is connected to the output that control signal produces part 12.The input of three-state buffer 14-2 is connected to the output of shift register 14-1 and abnormality detection part 15, and the output of three-state buffer 14-2 is connected to gate 21.Three-state buffer 14-2 is also connected to power supply 3.
In abnormality detection part 15, charging circuit 15-2 is connected in series to capacitor 15-1.The output-parallel of discharge circuit 15-3 is to capacitor 15-1, and the input of discharge circuit 15-3 is connected to the output that control signal produces part 12.The input of comparator circuit 15-4 is connected to the hot side of capacitor 15-1, and the output of comparator circuit 15-4 is connected to the input of three-state buffer 14-2.
Next, the function of the element of device drives part 2 is described below with reference to Fig. 1 and 4.
A/D conversion portion 10 will convert data image signal 10A to from the analog picture signal 9A of image signal source (not shown), and data image signal 10A is offered Image Information Processing part 11.Data image signal 10A comprises horizontal-drive signal 11B and vertical synchronizing signal 11C.In the picture signal that provides from image signal source is under the situation of digital signal, and A/D conversion portion 10 is dispensable.
Image Information Processing part 11 extracts from data image signal 10A and is used for the capable picture signal 11A of j, be input to cathode electrode drive part 13 will be used for the capable picture signal 11A of j, and from data image signal 10A, extract horizontal-drive signal 11B and vertical synchronizing signal 11C, and they are input in the control signal generation part 12.In this case, j is from the interior value of the scope of 1 to n (n is the total number of gate 21).
Control signal produces part 12 and generates picture signal seizure beginning pulse 12A and cathode electrode driving beginning pulse 12B according to horizontal-drive signal 11B and vertical synchronizing signal 11C, so that they are input in the cathode electrode drive part 13.In addition, control signal produces part 12 and generates gate driving beginning pulse 12C and be used for the shift clock 12D (scan clock) that gate is selected according to horizontal-drive signal 11B and vertical synchronizing signal 11C, so that they are input in the gate drive part 14.The shift clock 12D that control signal generation part 12 also will be used for the gate selection is input to abnormality detection part 15.
Cathode electrode drive part 13 is used for the capable picture signal 11A of j by modulation and generates the voltage 13A (pixel voltage) that is applied to cathode electrode, is input in the image display 1 so that will be applied to the voltage 13A of cathode electrode.
Fig. 5 illustrates the part of the detailed structure of power supply 3.Power supply 3 is AC-DC converters, and wherein chopper circuit 62 is connected in series to rectifier smoothing circuit 61, and power supply 3 provides electric power to other elements.Fig. 5 illustrates the specific example of detailed structure that the element of the necessary power supply 3 of electric power is provided to three-state buffer 14-2.Below the detailed structure shown in Fig. 5 will be described.
Next, the operation that below description is had the image-display units of said structure.
At first, referring to Fig. 2 and 3, below photoemissive principle will be described.
(=Vcol (Ci, Rj)) is applied to cathode electrode 20, and the voltage 14A (=Vrow (Rj)) that is applied to gate is applied to gate 21 to be applied to the voltage 13A of cathode electrode.Thereby, with respect to the gating-cathode voltage of cathode electrode 20 (Vgc (and Ci, Rj)=Vcol (Ci, Rj)-Vrow (Rr)) be applied in the capable gate of j 21 (=Rj) and between the cathode electrode 20.Therefore, by the electric field by its generation, electronics 29 is emitted (referring to Fig. 2) from negative electrode equipment 25.At this moment, when being applied to anode electrode 28, electronics 29 attracted to anode electrode 27K as voltage HV (＞Vrow (Rj)), with impinge anode electrode 27K.Thereby anode current Ia is by 20 direction flows from anode electrode 28 to cathode electrode.At this moment, anode electrode 28 is coated light-emitting layer 27, so light-emitting layer 27 is by the energy emission light of electron impact.In the following description, gating-cathode voltage Vgc (Ci, Rj) expression " gating-cathode voltage Vgc " or just expression " voltage Vgc ".
Next, referring to Fig. 6, below gray level display will be described.
Fig. 6 illustrates the relation (electron emission characteristic) between gating-cathode voltage Vgc and the anode current Ia.From figure, obviously see, in electron emission characteristic, when gating-cathode voltage Vgc is equal to or less than cut-off voltage 40 (for example 20V), then be difficult to launch the electronics that emission contributes to light, on the other hand, when voltage Vgc is higher than cut-off voltage 40, the emission electronics that emission contributes to light.Therefore, by using this characteristic, carry out gray level display.
For example, suppose that gate drive part 14 selects the gate (for example voltage be set as 35V) of j in capable.At this moment, to be set to the maximum brightness level (be so-called white level to the voltage 13A that is applied to cathode electrode; 0V for example), gating-cathode voltage Vgc is 35V.Obviously as seen, (electric current I is a) bigger, and therefore the light of launching from light-emitting layer 27 has high brightness owing to the amount of electrons of launching from negative electrode equipment 25 this moment from Fig. 6.
On the other hand, being set to the minimum brightness level at the voltage 13A that is applied to cathode electrode (is so-called black level; 15V for example) time, gating-cathode voltage Vgc is 20V.The voltage Vgc that be applied to cathode electrode this moment is near cut-off voltage 40, and (electric current I is a) minimum, so the emission of the light of light-emitting layer 27 takes place hardly, so luminance brightness is low for the amount of electrons of launching from negative electrode equipment 25.
Therefore, the voltage 13A that will be applied to cathode electrode when the value according to data image signal 10A is limited in 0V in the scope of 15V the time, can show various gray scales, and can carry out required gray level display.
Next, the operation of device drives part 2 below will be described.
Fig. 7 A to 7G illustrates the sequential of the main signal in the device drives part 2.The transverse axis express time, Z-axis is represented voltage.Fig. 8 A and 8B illustrate the capable voltage 13A that is applied to cathode electrode of j and are applied to relation between the voltage 14A of gate.Transverse axis is represented the number of the cathode electrode that directions X is arranged, and Z-axis is represented voltage.In Fig. 8 A and 8B,, a cathode electrode CRi (i=1 is to m) who is used for R (red) only is shown in order to simplify description.
At first, A/D conversion portion 10 converts analog picture signal 9A to data image signal 10A.At this moment, data image signal 10A for example comprises 8 bit digital picture signals, horizontal-drive signal 11B and the vertical synchronizing signal 11C that is used for R (red), G (green) and B (indigo plant).A/D conversion portion 10 is input to data image signal 10A in the Image Information Processing part 11.
The data image signal 10A of 11 pairs of inputs of Image Information Processing part carries out various signal Processing, for example picture quality adjustment, and from data image signal 10A, extract horizontal-drive signal 11B and vertical synchronizing signal 11C, produce in the part 12 they are input to control signal.Image Information Processing part 11 also is synchronized with the reference clock (not shown), and the picture signal 11A (referring to Fig. 7 B) that will be used for delegation's (being that j is capable in the case) is input to cathode electrode drive part 13.Cathode electrode drive part 13 is caught picture signal 11A, and interim memory image signal 11A.
Control signal produces part 12 according to horizontal-drive signal 11B and vertical synchronizing signal 11C, and the picture signal seizure beginning pulse 12A (referring to Fig. 7 A) that the picture catching in the indication cathode electrode drive part 13 is begun sequential is input in the cathode electrode drive part 13.Control signal produces part 12 according to horizontal-drive signal 11B and vertical synchronizing signal 11C, will be used for instructing the cathode electrode that the capable picture signal 11A of j is input to image display 1 of being used for that will temporarily be stored in cathode electrode drive part 13A to drive beginning pulse 12B (referring to Fig. 7 C) and be input in the cathode electrode drive part 13.
Cathode electrode drive part 13 is synchronized with cathode electrode and drives beginning pulse 12B, and the voltage 13A (referring to Fig. 7 D) that almost will be applied to cathode electrode simultaneously is as each cathode electrode 20 that outputs to image display 1 corresponding to the modulation signal that is used for the capable picture signal of j.Thereby Fig. 8 B is illustrated to be applied to the voltage 13A of cathode electrode (=Vcol (Ci, Rj), (i=1 is to m)) is output to cathode electrode 20.
Control signal produces part 12 and according to horizontal-drive signal 11B and vertical synchronizing signal 11C gate driving beginning pulse 12C is input to gate drive part 14 (referring to Fig. 7 E and 7F) with the shift clock 12D that is used for the gate selection.Produced from control signal under the situation of part 12 inputs when drive beginning pulse 12C at gate, when being used for shift clock 12D that gate selects and being produced part 12 inputs from control signal, gate drive part 14 is synchronously dried to be used for the shift clock 12D that gate is selected, and the voltage 14A (=Vrow (R1)) that is applied to gate is outputed to gate 21 (referring to Fig. 7 G) in first row.On the other hand, do not produce under the situation of part 12 inputs when drive beginning pulse 12C at gate from control signal, when being used for shift clock 12D that gate selects and being produced part 12 inputs from control signal, (=Vrow (Rj), 2≤j≤n) are synchronized to and output to the capable gate of j 21 (referring to Fig. 7 G) with being used for shift clock 12D that gate selects to be applied to the voltage 14A of gate.
Repeat above step for n gate 21.Therefore, finish the process that is used to show a screen image.In addition, can be by showing a screen image with synchronous each signal of any other method in addition to the above methods.
Above-mentioned when being used to show the process of a screen image when repeating, in image-display units, can show the multi-screen image continuously.
Next, below will describe the operation of abnormality detection part 15 in detail.
Fig. 9 A to 9E illustrate be used for describing present embodiment be used for shift clock 12D that gate selects just often abnormity detection portion divide the sequential chart of 15 operation.Figure 10 A to 10C illustrates and is used to be described in the sequential chart that is used for shift clock 12D that gate the selects state when unusual under the situation that does not comprise abnormality detection part 15, example as a comparison.More specifically, Figure 10 A to 10C illustrates owing to noise or similar reason, is used for the backward situation that is used for the shift clock 12D one-period of gate selection normally of shift clock 12D that gate is selected.Figure 11 A to 11E illustrates and is used for describing present embodiment is used for the sequential chart that the operation of abnormality detection part 15 under the unusual situation takes place for shift clock 12D that gate selects shown in Figure 10 A to 10C.Figure 12 illustrates abnormality detection part 15 and detects unusual step.
When device drives part 2 was operated, abnormality detection part 15 regularly monitored the shift clock 12D that gate is selected that is used for that produces part 12 outputs from control signal.Shown in Fig. 9 A, the shift clock 12D that is used for the gate selection has pulse waveform, and generally has the fixed cycle.This cycle is confirmed as optimally adjusting the brightness of image, and is to determine under the situation of considering the characteristic such such as luminance saturation.Thereby generally speaking, pulse waveform periodically is input among the discharge circuit 15-3.Shown in Fig. 9 D, before charging voltage Vc surpassed reference voltage Vs, discharge circuit 15-3 discharged to charging voltage Vc by the recurrent pulse waveform that produces part 12 inputs from control signal.Be no more than at charging voltage Vc under the situation of reference voltage Vs, comparator circuit 15-4 constantly is input to output enable signal 15A among the three-state buffer 14-2.In other words, be under the situation of normal condition at the shift clock 12D that is used for the gate selection, more specifically saying so is no more than under the situation of reference voltage Vs at charging voltage Vc, and abnormality detection part 15 allows to output to three-state buffer 14-2 (step S101).
Now, consider that the shift clock 12D that is used for the gate selection takes place under the unusual situation, abnormality detection part 15 is not included in the state in the device drives part 2, example as a comparison.For example, shown in Figure 10 A, below the phase lag of considering to be used for the shift clock 12D that gate selects is used for the situation of the shift clock 12D one-period that gate selects normally.When the phase lag one-period, shown in Figure 10 C, the voltage Vrow (R2) that is applied to gate is applied to the gate (R2) in second row, and the time that applies is the twice of normal time.In other words, the gating-cathode voltage Vgc that surpasses cut-off voltage 40 is applied to pixel corresponding to the gate (R2) of second row (Ci, R2), application time is the twice of normal time.
Thereby (Ci, light emission brightness R2) is higher than other row to pixel, thereby generates the high brightness line of horizontal direction on screen.In addition, except above-mentioned unusually, for example, be input to being used under the situation that shift clock 12D that gate selects disappears in the gate drive part 14 making owing to unusual etc. in CPU or the peripheral circuit, voltage Vrow (Rj) is applied in as sweep signal, and application time is longer than the application time in the situation of above-mentioned phase lag.Therefore, when this unusual generation, except the horizontal direction on screen generates the high brightness line, the negative electrode device characteristics decline that causes owing to loss may take place also, the damage to the resistive layer of the bottom surface that is deployed in negative electrode equipment perhaps may take place.
But, in present embodiment, when having comprised abnormality detection part 15 in the device drives part 2, can address the above problem.More specifically, as mentioned above, be used under the situation that shift clock 12D that gate selects disappears causing owing to CPU or peripheral circuit unusual etc., perhaps causing that owing to noise etc. the phase lag that is used for the shift clock 12D that gate selects is under the situation that is used for the shift clock 12D that gate selects normally, the pulse waveform that is used for the shift clock 12D of gate selection is not imported into discharge circuit 15-3, perhaps is imported into discharge circuit 15-3 after the shift clock 12D that is used for the gate selection normally.Shown in Figure 11 D, before the pulse waveform of the shift clock 12D that is used for the gate selection was imported into discharge circuit 15-3, charging voltage Vc had surpassed reference voltage Vs.When comparator circuit 15-4 detected charging voltage Vc above reference voltage Vs, shown in Figure 11 E, the output of output enable signal 15A was suspended immediately.In addition, comparator circuit 15-4 keeps suspending the output of output enable signal 15A, detects charging voltage Vc up to comparator circuit 15-4 and is reduced to (step S102) below the reference voltage Vs.Thereby, take place under the unusual situation being used for the shift clock 12D that gate selects, shown in Figure 11 C, abnormality detection part 15 is suspended from three-state buffer 14-2 to gate 21 output.Even in order to prevent shown in Figure 11 D, to provide predetermined allowance tm in the output that is used for also suspending under the situation that shift clock 12D that gate selects is in normal condition output enable signal 15A.
Now, will be described with reference to figure 6.As mentioned above, by suspending from three-state buffer 14-2 to gate 21 output, the voltage 14A that is applied to gate drops to 0V from 35V.At this moment, according to picture signal, the voltage 13A that is applied to cathode electrode is that 0V is to 15V.Therefore, be that 0V arrives-15V with respect to the gating-cathode voltage Vgc of cathode electrode 20, so voltage Vgc is no more than cut-off voltage 40 (for example 20V), electronics 29 is by emission from negative electrode equipment 25, thus light-emitting layer 27 is not launched light.In addition, the absolute value of gating-cathode voltage Vgc is no more than cut-off voltage 40.
Therefore, take place under the unusual situation, can prevent that the gating-cathode voltage Vgc that surpasses cut-off voltage 40 is applied to pixel with the duration that surpasses normal time far away at the shift clock 12D that is used for the gate selection.
Therefore, in the present embodiment, can not occur on the screen abnormal show that generates the high brightness line on the horizontal direction, and in the negative electrode equipment that can not take place to cause owing to loss etc. display characteristic decline or be deployed in the such pixel damage of resistive layer of the bottom surface of negative electrode equipment such as damage.
Thereby, in the present embodiment, take place under the unusual situation at the shift clock 12D that is used for the gate selection, 21 output is suspended from gate drive part 14 to gate, therefore so that gating-cathode voltage Vgc is equal to or less than cut-off voltage 40, can prevent owing to be used for abnormal show, display characteristic decline and the pixel damage that the unusual input of the shift clock 12D that gate selects causes.
When the pulse waveform that is used for the shift clock 12D that gate selects after the output at gate drive part 14 is suspended is transfused to discharge circuit 15-3, as mentioned above, charging voltage Vc is discharged, so charging voltage Vc is reduced to below the reference voltage Vs.Detect charging voltage Vc at comparator circuit 15-4 and be reduced under the situation below the reference voltage Vs (step S103), shown in Figure 11 E, the output of output enable signal 15A is restarted (step S104).Therefore, removed outputing to the time-out of gate drive part 14.Therefore, in the present embodiment, be restored under the situation of normal condition at the shift clock 12D that is used for the gate selection, more specifically, be imported into again under the situation of abnormality detection part 15 at the shift clock 12D that is used for the gate selection, gate drive part 14 can continue the sweep gate electrode.
[second embodiment]
Next, second embodiment of the present invention will be described below.
In first embodiment, take place under the unusual situation at the shift clock 12D that is used for the gate selection, mean by time-out and the output of the output enable signal 15A of the voltage 14A that allows output to be applied to gate to suspend the output of the voltage 14A that is applied to gate.On the other hand, in the present embodiment, taking place under the above-mentioned unusual situation, meaning the output of permission, suspending the output of the voltage 44A that is applied to gate from the input enable signal 15C of power supply 3 input input voltages (gate voltage 3A) by time-out.
In other words, the difference of present embodiment is to comprise switch that between power supply 3 and three-state buffer 14-2 this switch is switched on or switched off the input voltage (gate voltage 3A) from power supply 3 according to the input enable signal 15C from 15 inputs of abnormality detection part.Structure, operation and the function identical with first embodiment can not further describe, and below will describe above-mentioned difference in detail.
Figure 13 illustrates the gate drive part 44 (second electrode driver and scanning voltage controller) according to present embodiment and the schematic block diagram of abnormality detection part 15.Gate drive part 44 comprises shift register 44-1, three-state buffer 44-2 and switch 44-4.
The input of shift register 44-1 is connected to the output that control signal produces part 12.The input of three-state buffer 44-2 is connected to the output of shift register 44-1 and the output of switch 44-4.The output of three-state buffer 44-2 is connected to gate 21.The input of switch 44-4 is connected to the output of power supply 3 and the output of abnormality detection part 15.
Figure 14 A to 14F shows the sequential chart of the operation that is used to describe gate drive part 44.More specifically, Figure 14 A to 14F shows at the shift clock 12D that is used for the gate selection and takes place to offer the cut state of gate voltage 3A of three-state buffer 44-2 under the unusual situation identical with Figure 11 A to 11E.
Take place under the unusual situation at the shift clock 12D that is used for the gate selection, shown in Figure 14 F, the supply voltage 44B that offers three-state buffer 44-2 is cut off, and shown in Figure 14 C, 21 output is suspended from three-state buffer 44-2 to gate.Therefore, described in first embodiment, gating-cathode voltage Vgc can be equal to or less than cut-off voltage 40, can prevent that therefore gating-cathode voltage the Vgc that surpasses cut-off voltage 40 was applied on the pixel with the duration that surpasses normal time far away.
Therefore, in the present embodiment, can not occur on the screen abnormal show that generates the high brightness line on the horizontal direction, and in the negative electrode equipment that can not take place to cause owing to loss etc. display characteristic decline or be deployed in the such pixel damage of resistive layer of the bottom surface of negative electrode equipment such as damage.
Thereby, in the present embodiment, take place under the unusual situation at the shift clock 12D that is used for the gate selection, 21 output is suspended from gate drive part 44 to gate, therefore so that gating-cathode voltage Vgc is equal to or less than cut-off voltage 40, can prevent owing to be used for abnormal show, display characteristic decline and the pixel damage that the unusual input of the shift clock 12D that gate selects causes.
Input pulse at the shift clock 12D that is used for the gate selection is imported under the situation of discharge circuit 15-3, charging voltage Vc is reduced to below the reference voltage Vs, therefore shown in Figure 14 E, detect charging voltage Vc and be reduced to the following comparator circuit 15-4 of reference voltage Vs and export input enable signal 15C once more.Therefore, removed time-out to the output of three-state buffer 44-2.Therefore, in the present embodiment, as in first embodiment, return under the situation of normal condition at the shift clock 12D that is used for the gate selection, more specifically be to be equal to or less than under the situation of reference voltage Vs at charging voltage Vc, gate drive part 44 can continue the sweep gate electrode.
[the 3rd embodiment]
Next, below the third embodiment of the present invention will be described.
The purpose of first embodiment is 21 output to take place to suspend under the unusual situation from gate drive part 14 to gate being used for shift clock 12D that gate selects.On the other hand, the purpose of present embodiment is that 21 output takes place to suspend under the unusual situation in gate drive part 14 from gate drive part 14 to gate.
The difference of the present embodiment and first embodiment is to comprise abnormality detection part 45 rather than abnormality detection part 15, and has changed the annexation between abnormality detection part 45, control signal generation part 12 and the gate drive part 14.Below will be not described further structure, operation and the function identical, and will describe above-mentioned difference in detail with first embodiment.
Figure 15 illustrates according to the gate drive part 14 of present embodiment and the schematic block diagram of abnormality detection part 45.Abnormality detection part 45 comprises delay circuit 45-1, comparator circuit 45-2 and latchs part 45-3.
In abnormality detection part 45, the input of delay circuit 45-1 is connected to the final level output 14C of shift register 14-1.The input of comparator circuit 45-2 is connected to the output of delay circuit 45-1 and control signal generation part 12.The input of latching part 45-3 is connected to the output of comparator circuit 45-2, and the output of latching part 45-3 is connected to the input of three-state buffer 14-2.
Drive beginning pulse 12C at gate and be output as " 1 ", and the final level output 14C of shift register 14-1 is output as under the situation of " 0 ", promptly at shift register 14-1 abnormal operation, so that be difficult to the suitable cycle output that gate drives beginning pulse 12C be become under the situation of " 1 ", abnormality detection part 45 is suspended the output of output enable signal 45A.On the other hand, the final level output 14C that is output as " 1 " and shift register 14-1 at gate driving beginning pulse 12C is output as under the situation of " 1 ", be thereby that shift register 14-1 normal running can become the output that gate drives beginning pulse 12C under the situation of " 1 " with the suitable cycle, output enable signal 45A is output.
But in first cycle after opening power, when gate driving beginning pulse 12C was output as " 1 ", the final level output 14C of shift register 14-1 was output as " 0 ".Therefore, latch the suitably output of control abnormity test section 45 of part 45-3, with the output that prevents to suspend output enable signal 45A under the normal condition situation of above-mentioned situation comprising.
In latching part 45-3, determine shift register 14-1 whether the moment of normal running be that gate drives the moment (TRG) in the time durations that beginning pulse 12C is output as " 1 ", as shown in figure 16.In case determine that output enable signal 45A is output under the situation of shift register 14-1 normal running, up to determine whether normal running of shift register 14-1 in next moment (TRG).On the other hand, determining under the situation of shift register 14-1 abnormal operation in a single day that consider that the possibility of shift register 14-1 recovery is very little, afterwards, the output of output enable signal 45A is suspended by lasting.
Next, below will describe the operation of gate drive part 14 and abnormality detection part 45 in detail.
Figure 16 A to 16E illustrates the sequential chart that is used for describing the abnormality detection part 45 under the situation that present embodiment shift register 14-1 is in normal condition.Figure 17 A to 17C illustrates and is used for being described in the sequential chart that unusual state takes place for shift register 14-1 under the situation that does not comprise abnormality detection part 45, example as a comparison.More specifically, second register that shift register 14-1 has been shown among Figure 17 A to 17C damages, and output is always " 1 ", so voltage Vrow (R2) is continuously applied the situation of the gate 21 in second row.Figure 18 A to 18E illustrates and is used for describing the sequential chart that the operation of abnormality detection part 45 under the unusual situation shown in Figure 17 A to 17C takes place among the present embodiment shift register 14-1.Figure 19 illustrates abnormality detection part 45 and detects unusual step.
When device drives part 2 was operated, abnormality detection part 45 supervision regularly was used for the shift clock 12D of gate selection and the final level output 14C of shift register 14-1.Shown in Figure 16 B and 16D, be used for the shift clock 12D of gate selection and the final level output 14C of shift register 14-1 and have the identical pulse waveform of level, so they generally have same period.Thereby under normal condition, pulse waveform periodically is input among the delay circuit 45-1.
Delay circuit 45-1 postpones the final level output 14C of shift register 14-1, and be half of cycle that is used for the shift clock 12D that gate selects time delay.Next, in comparator circuit 45-2, the comparative result between the level of the level of the output of gate driving beginning pulse 12C and the final level output 14C of shift register 14-1 is imported into and latchs among the part 45-3.In other words, when their voltage has same level, determine shift register 14-1 normal running, and " 1 " be input to latch among the part 45-3.On the other hand, they voltage level not simultaneously, determine shift register 14-1 upset operation, therefore " 0 " is input to and latchs among the part 45-3.
In latching part 45-3, locate comparative result under the situation of " 1 " in above moment (TRG), output enable signal 45A is continued to be input among the three-state buffer 14-2, up to following (TRG) in a flash.On the other hand, the comparative result in above moment (TRG) is under the situation of " 0 ", and the output of output enable signal 45A is continued to suspend, no matter whether next input is arranged.But, as mentioned above, in period 1 after opening power, determine shift register 14-1 upset operation, and " 0 " be input to latch among the part 45-3, therefore in this case, the output of output enable signal 45A is not suspended, and output enable signal 45A is continued to be input among the three-state buffer 14-2, and the comparative result of locating up to following (TRG) in a flash is transfused to.In other words, be at shift register 14-1 under the situation of normal condition, abnormality detection part 45 allows to output among the three-state buffer 14-2.
Now, example is below considered to take place in shift register not comprise the state of abnormality detection part in the device drives part under the unusual situation as a comparison.For example, shown in Figure 17 C, now will consider a kind of abnormal conditions, promptly second register in the shift register damages, and output is always " 1 ", and the voltage 114A (=Vrow (R2)) that therefore is applied to gate is continuously applied the gate in second row.When this voltage Vrow (R2) taking place be continuously applied gate in second row unusual, the voltage that is equal to or higher than cut-off voltage 40 is continuously applied in the pixel in second row, and application time is very long.Therefore, in horizontal direction on screen, generate the high brightness line, the characteristic decline of the negative electrode equipment that causes owing to loss also may take place, perhaps be deployed in the damage of resistive layer of the bottom surface of negative electrode equipment.
But, in present embodiment, comprise in the device drives part 2 under the situation of abnormality detection part 45, can address the above problem.More specifically, as mentioned above, take place in shift register 14-1 under the unusual situation, comparator circuit 45-2 input " 0 " is latched the output that part 45-3 suspends output enable signal 45A immediately, shown in Figure 18 E to latching among the part 45-3.In addition, latch the output that part 45-3 keep to suspend output enable signal 45A, be closed with till preventing that voltage Vrow (R2) is continuously applied gate 21 in second row once more up to for example power supply of device drives part 2.
Thereby, in gate drive part 14, take place under the unusual situation, shown in Figure 18 C, can suspend from gate drive part 14 to gate 21 output.Therefore, as described in first embodiment, gating-cathode voltage Vgc can be lowered to and be lower than cut-off voltage 40, can prevent that therefore gating-cathode voltage the Vgc that surpasses cut-off voltage 40 was applied on the pixel with the duration that surpasses normal time far away.
Therefore, in the present embodiment, can not occur on the screen abnormal show that generates the high brightness line on the horizontal direction, and in the negative electrode equipment that can not take place to cause owing to loss etc. display characteristic decline or be deployed in the such pixel damage of resistive layer of the bottom surface of negative electrode equipment such as damage.
Therefore, in the present embodiment, in gate drive part 14, take place under the unusual situation, 21 output is suspended from gate drive part 14 to gate, therefore gating-cathode voltage Vgc equals cut-off voltage 40, therefore can prevent owing to be used for abnormal show, display characteristic decline and the pixel damage that the unusual input of the shift clock 12D that gate selects causes.
Though described the present invention with reference to three embodiment and modification, the present invention is not limited to these embodiment and modification, and can be modified by different modes.
For example, in first embodiment and the 3rd embodiment, take place to take place under the situation of operation exception among the unusual or shift register 14-1 of input being used for shift clock 12D that gate selects, be suspended to the input of three-state buffer 14-2; But the present invention is not limited to this.Take place to import under the situation that operation exception takes place among unusual or the shift register 14-1 at the shift clock 12D that is used for the gate selection; can be suspended as long as be applied to the voltage of gate, gate drive part and abnormality detection partly can have any structure.
In the 3rd embodiment, comprised gate drive part 14; But, in second embodiment, can comprise gate drive part 44 rather than gate drive part 14.Even, also can obtain the effect identical with the 3rd embodiment because comprised gate drive part 44.
With the 3rd embodiment and in revising, the input that perhaps detects the shift clock 12D that is used for the gate selection is unusual, perhaps detects the operation exception among shift register 14-1 or the shift register 44-1 at first, second; But, can detect these two kinds simultaneously unusually.More specifically, can comprise abnormality detection part 15 and abnormality detection part 45 both.
In the modification of second embodiment and the 3rd embodiment, take place to import under the situation that operation exception takes place among unusual or the shift register 44-1 at the shift clock 12D that is used for the gate selection, provide the output (gate voltage 3A) of the power supply 3 of electric power to be suspended to three-state buffer 44-2, so gating-cathode voltage Vgc is equal to or less than cut-off voltage 40; But, the invention is not restricted to this.Take place to import under the situation that operation exception takes place in unusual or the shift register in the shift clock that is used for the gate selection, the output that is applied to the voltage of gate can be lowered, so that gating-cathode voltage is equal to or less than cut-off voltage.With describing the modification of second embodiment in detail, as representative illustration.
Figure 20 illustrates gate drive part 54, abnormality detection part 15 and the power supply 4 in this modification.Figure 21 illustrates the schematic block diagram of power supply 4.The difference of this modification and second embodiment is the output of abnormality detection part 15 is connected to the input of the pwm circuit 74 of power supply 4, and the output of power supply 4 is directly connected to three-state buffer 54-2.Below will can not further describe with second embodiment in identical structure, operation and effect, and will describe above-mentioned difference in detail.
Under the output enable signal 15B that means the output voltage (gate voltage 4A) that allows out-put supply 4 was not imported into situation in the pwm circuit 74 of power supply 4, pulse signal 74A was not output to driving circuit 73.Under pulse signal 74A was not imported into situation in the driving circuit 73, driving circuit 73 can not output to pulse signal 67A the grid of MOSFET 68.
In this is revised, take place under the unusual situation at the shift clock 12D that is used for the gate selection, provide the output (gate voltage 4A) of the power supply 4 of electric power to be lowered to three-state buffer 54-2, be reduced to 20V from for example 35V so that be applied to the voltage 54A of gate.At this moment, according to picture signal, the voltage 13A that is applied to cathode electrode is that 0V is to 15V.Therefore, with respect to the gating-cathode voltage Vgc of cathode electrode 20 be 0V to 20V, so voltage Vgc is no more than cut-off voltage 40 (for example 20V), electronics 29 is not launched from negative electrode equipment 25, thereby light-emitting layer 27 is not launched light.
Therefore, as described in first embodiment, gating-cathode voltage Vgc can be equal to or less than cut-off voltage 40, can prevent that therefore gating-cathode voltage the Vgc that surpasses cut-off voltage 40 is applied to pixel with the duration that surpasses normal time far away.
Therefore, in this is revised, can not occur on the screen abnormal show that generates the high brightness line on the horizontal direction, and in the negative electrode equipment that can not take place to cause owing to loss etc. display characteristic decline or be deployed in the such pixel damage of resistive layer of the bottom surface of negative electrode equipment such as damage.
Thereby, in this is revised, take place under the unusual situation at the shift clock 12D that is used for the gate selection, 21 output is lowered from gate drive part 54 to gate, therefore so that gating-cathode voltage Vgc is equal to or less than cut-off voltage 40, can prevent owing to be used for abnormal show, display characteristic decline and the pixel damage that the unusual input of the shift clock 12D that gate selects causes.
In this was revised, gating-cathode voltage Vgc was controlled as and is equal to or less than cut-off voltage 40; But, taking place under the situation that display characteristic descends or the possibility of pixel damage is very little, gating-cathode voltage Vgc can be a little more than cut-off voltage 40.For example, gating-cathode voltage Vgc can be roughly 20V to 25V.
In addition, the present invention not only may be used on above-mentioned field emission display, also may be used on such as OLED display and the such image-display units of LCD.In addition, the present invention may be used on passive matrix display, also may be used on Active Matrix Display.
In addition, in image-display units according to an embodiment of the invention, as mentioned above, cathode electrode drive part 13 and gate drive part 14,44 and 54 are according to horizontal-drive signal 11B included among the data image signal 10A and vertical synchronizing signal 11C display image.Therefore, for example, in these signals, take place under the unusual situation, perhaps take place under the unusual situation the problems referred to above to take place at the shift clock 12D that is used for the gate selection that generates according to these signals.Therefore, can consider separately to generate the synchronizing signal that is different from these signals, and according to this synchronizing signal display image, thereby promptly in horizontal-drive signal 11B etc., take place unusually that image-display units also can prevent owing to be somebody's turn to do unusual the problems referred to above that cause.But,, in this synchronizing signal, take place also identical problem may take place under the unusual situation even image-display units has this new construction.Therefore, in abnormality detection part 15 or 45,, also can prevent from this synchronizing signal, to take place contingent same problem under the unusual situation even used above-mentioned different synchronizing signal according to embodiment.
It should be appreciated by those skilled in the art,, various modifications, combination, sub-portfolio and change can take place, as long as these modifications, combination, sub-portfolio and change belong in the scope of claims and equivalent thereof according to designing requirement and other factors.
Claims (5)
1. one kind by selecting and drive the image-display units that the pixel that is arranged to matrix form is come display image, and this image-display units comprises:
A plurality of first electrodes and a plurality of second electrode, described a plurality of first electrodes and a plurality of second electrode extend on column direction and line direction respectively, so that intersect each other at each locations of pixels place and face;
First electrod driving device, it applies pixel voltage based on picture signal to described a plurality of first electrodes;
Second electrod driving device, its scan clock according to input applies scanning voltage in proper order to described a plurality of second electrodes, the pixel column that described scanning voltage selection will drive;
Abnormal detector, it detects the operation exception in described second electrod driving device; And
The scanning voltage control device, the described scanning voltage of control under the situation that its operation exception in described second electrod driving device is detected, so that make described a plurality of first electrode and be equal to or less than predetermined value, wherein with respect to the potential difference (PD) between described a plurality of second electrodes of described a plurality of first electrodes
Described second electrod driving device comprises shift register, and this shift register is shifted in proper order according to the vertical synchronizing signal of described scan clock to input, and
Described abnormal detector comprises comparator circuit, this comparator circuit is compared described vertical synchronizing signal with the final level output of described shift register, and when comparative result shows that the final level output of described vertical synchronizing signal and described shift register does not match, detect the operation exception in described second electrod driving device.
2. image-display units as claimed in claim 1, wherein
Described scanning voltage control device disconnects the output from the described scanning voltage of described second electrod driving device, so that make described potential difference (PD) be equal to or less than described predetermined value.
3. image-display units as claimed in claim 1, wherein
Described scanning voltage control device disconnects provides the output of the power supply of electric power to described second electrod driving device, so that make described potential difference (PD) be equal to or less than described predetermined value.
4. image-display units as claimed in claim 1, wherein
Described scanning voltage control device reduces provides the output of the power supply of electric power to described second electrod driving device, so that make described potential difference (PD) be equal to or less than described predetermined value.
5. a driving is by selecting and drive the method that the pixel that is arranged to matrix form is come the image-display units of display image, and this method may further comprise the steps:
Arrange a plurality of first electrodes and a plurality of second electrode, described a plurality of first electrodes and a plurality of second electrode extend on column direction and line direction respectively, so that intersect each other at each locations of pixels place and face;
Apply pixel voltage based on picture signal to described a plurality of first electrodes;
Scan clock according to input applies scanning voltage in proper order to described a plurality of second electrodes, the pixel column that described scanning voltage selection will drive;
Detect the operation exception in described second electrod driving device; And
Reduce described scanning voltage under the situation that operation exception in described second electrod driving device is detected, so that make described a plurality of first electrode and be equal to or less than predetermined value with respect to the potential difference (PD) between described a plurality of second electrodes of described a plurality of first electrodes
Operation exception in wherein said second electrod driving device is detected by following steps:
The final level of the shift register that being used in vertical synchronizing signal and described second electrod driving device of input is shifted to the vertical synchronizing signal of described input in proper order according to described scan clock is exported and is compared, and when comparative result shows that the final level output of described vertical synchronizing signal and described shift register does not match, detect the operation exception in described second electrod driving device.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
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| JP2004258162 | 2004-09-06 | ||
| JP2004-258162 | 2004-09-06 | ||
| JP2005179912A JP4247631B2 (en) | 2004-09-06 | 2005-06-20 | Image display device |
| JP2005-179912 | 2005-06-20 |
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| CNB2005100984942A Division CN100489931C (en) | 2004-09-06 | 2005-09-06 | Image display unit and method for driving the same |
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| CN101276536A CN101276536A (en) | 2008-10-01 |
| CN101276536B true CN101276536B (en) | 2010-04-14 |
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| CN2008100944830A Expired - Fee Related CN101276536B (en) | 2004-09-06 | 2005-09-06 | Image display unit and method of driving the same |
| CNB2005100984942A Expired - Fee Related CN100489931C (en) | 2004-09-06 | 2005-09-06 | Image display unit and method for driving the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| WO2010041649A1 (en) * | 2008-10-10 | 2010-04-15 | シャープ株式会社 | Display device and method for driving the same |
| CN102097064B (en) * | 2009-12-09 | 2013-06-12 | 奇景光电股份有限公司 | Method and system for controlling scanning pause and reply of liquid crystal display |
| JP2016224187A (en) * | 2015-05-28 | 2016-12-28 | 株式会社ジャパンディスプレイ | Display |
| TWI579820B (en) * | 2015-06-11 | 2017-04-21 | 友達光電股份有限公司 | Display and driving method thereof |
| US9419597B1 (en) * | 2015-06-15 | 2016-08-16 | Analog Devices Global | Power-efficient chopping scheme for offset error correction in MEMS gyroscopes |
| JP6827753B2 (en) * | 2016-09-28 | 2021-02-10 | ラピスセミコンダクタ株式会社 | Interface circuit |
| US10872576B2 (en) * | 2016-10-05 | 2020-12-22 | Rohm Co., Ltd. | Display driver IC |
| CN106448522B (en) * | 2016-10-20 | 2019-03-26 | 京东方科技集团股份有限公司 | Detection circuit, gate driving circuit and display panel |
| CN110579720B (en) * | 2018-06-08 | 2022-08-30 | 台达电子工业股份有限公司 | Power supply monitor |
| CN113920936B (en) * | 2021-10-18 | 2024-03-12 | 京东方科技集团股份有限公司 | Signal monitoring circuit, display control circuit and display device |
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| EP0487742A1 (en) * | 1990-06-18 | 1992-06-03 | Seiko Epson Corporation | Flat displaying device and device for driving displaying elements |
| US5903260A (en) * | 1990-06-18 | 1999-05-11 | Seiko Epson Corporation | Flat device and display driver with on/off power controller used to prevent damage to the LCD |
| JP2002023712A (en) * | 2000-07-12 | 2002-01-25 | Fujitsu Ltd | Display device and its driving method |
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- 2005-09-06 CN CN2008100944830A patent/CN101276536B/en not_active Expired - Fee Related
- 2005-09-06 CN CNB2005100984942A patent/CN100489931C/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP0487742A1 (en) * | 1990-06-18 | 1992-06-03 | Seiko Epson Corporation | Flat displaying device and device for driving displaying elements |
| US5903260A (en) * | 1990-06-18 | 1999-05-11 | Seiko Epson Corporation | Flat device and display driver with on/off power controller used to prevent damage to the LCD |
| JP2002023712A (en) * | 2000-07-12 | 2002-01-25 | Fujitsu Ltd | Display device and its driving method |
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| CN1746949A (en) | 2006-03-15 |
| CN100489931C (en) | 2009-05-20 |
| CN101276536A (en) | 2008-10-01 |
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