CN101242382A - Receiving method for low-complexity digital middle-frequency data - Google Patents
Receiving method for low-complexity digital middle-frequency data Download PDFInfo
- Publication number
- CN101242382A CN101242382A CNA2007100372470A CN200710037247A CN101242382A CN 101242382 A CN101242382 A CN 101242382A CN A2007100372470 A CNA2007100372470 A CN A2007100372470A CN 200710037247 A CN200710037247 A CN 200710037247A CN 101242382 A CN101242382 A CN 101242382A
- Authority
- CN
- China
- Prior art keywords
- data
- circuit
- intermediate frequency
- baseband
- time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/50—Reducing energy consumption in communication networks in wire-line communication networks, e.g. low power modes or reduced link rate
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
The invention discloses a low-complexity digital intermediate frequency data receiving method. After the intermediate frequency is sampled in A/D sampling end with 4-time baseband sampling rate, and separated into I-channel and Q-channel data, the I-channel data is first delayed m beats, then 4-time down-sampled to get baseband I-channel data, and is output at single-time speed; the Q-channel data is first 2-time down-sampled, then multiplied with (-1)<p>, and filtered, so that only needed baseband frequency signals can be passed, at the same time, one point data corresponding to every two input sampling points is output, the two-time speed data is lowered to single-time speed when filtered to extract needed Q-channel data, and output at single-time speed. The invention makes maximum use of characteristics of hardware circuit and 4-time speed sampling, removes the invalid calculating process, at baseband speed, each sampling point only needs a fixed-coefficient multiplication to greatly reduce consumption and complexity.
Description
Technical field
The present invention relates to a kind of data receive method, especially a kind of low-complexity digital intermediate frequency data method of reseptance.
Background technology
In the receiving course of wireless signal, often adopt the scheme of digital intermediate frequency Data Receiving, promptly the method with digital Design realizes the conversion of signal frequency from the intermediate frequency to the base band.At present, digital intermediate frequency implementation commonly used has three kinds, and first kind is NCO (digital controlled oscillator) scheme, the string ripple signal that promptly produces one group of quadrature respectively is as digital mixing, its advantage is an accurate and flexible, but amount of calculation is big, and the realization of NCO needs multiplier and bigger ROM to store to support.Second kind of scheme is the improvement of first kind of scheme, as shown in Figure 1, samples with 4 times of baseband sampling rates at the A/D sampling end, so digital NCO is operated under the situation of 4 frequencys multiplication, and its output just can be reduced to { 1,0,-1,0....}, thus simplify circuit complexity greatly.The third scheme then is called the delta sigma modulation, makes if sampling for narrow band signal, forms the I/Q data in digital end, can well solve the I/Q matching problem.
Above-mentioned second method can be referring to shown in Figure 1, and wherein intermediate frequency data can be expressed as Icos (ω
IFT)-Qsin (ω
IFT), ω wherein
IFBe the angular frequency of intermediate frequency, t is the time, to this intermediate frequency data after the A/D sampling end is sampled with 4 times of baseband sampling rates and is separated into I road and Q road two paths of data, the I circuit-switched data be multiply by cos (ω
IFNT
4x), T
4xBe the sampling period, carry out filtering by a filter afterwards, 4 times of down-samplings obtain the I circuit-switched data then, and with its single doubly speed output; Simultaneously the Q circuit-switched data be multiply by-sin (ω
IFNT
4x), carrying out filtering by another filter afterwards, 4 times of down-samplings obtain the Q circuit-switched data then, and with its single doubly speed output.This method still exists amount of calculation bigger in the process that reality is used, the waste problem of resource.
Summary of the invention
Technical problem to be solved by this invention provides a kind of low-complexity digital intermediate frequency data method of reseptance, can optimize the correlation step that receives data greatly when assurance function is correct, reduces design complexities, and reduces resource requirement.
For solving the problems of the technologies described above, the technical scheme of low-complexity digital intermediate frequency data method of reseptance of the present invention is, to intermediate frequency data after the A/D sampling end is sampled with 4 times of baseband sampling rates and is separated into I road and Q road two paths of data,
With the time-delay m bat earlier of I circuit-switched data, carry out 4 times of down-samplings then, obtain the I circuit-switched data of base band, and with its single doubly speed output;
The Q circuit-switched data is carried out 2 times of down-samplings earlier, and then multiply by (1)
p, afterwards data are carried out filtering, make and have only required baseband frequency signal to pass through, export the data of a point simultaneously for the sampled point correspondence of per two inputs, data with twice speed in filtering drop to single doubly speed, extract required Q circuit-switched data, and with its single doubly speed output.
The present invention is maximized to have utilized the characteristics of hardware circuit and 4 times of speed samplings, optimizes and has fallen wherein invalid computational process, as long as average each full pattern point is done the multiplication of a fixed coefficient under base band speed, greatly reduces power consumption and complexity.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the schematic diagram of existing digital intermediate frequency data receive method;
Fig. 2 is the schematic diagram of low-complexity digital intermediate frequency data method of reseptance of the present invention;
Fig. 3 is the schematic diagram of the used filtering method of low-complexity digital intermediate frequency data method of reseptance of the present invention.
Embodiment
Low-complexity digital intermediate frequency data method of reseptance of the present invention can be referring to shown in Figure 2, to intermediate frequency data after the A/D sampling end is sampled with 4 times of baseband sampling rates and is separated into I road and Q road two paths of data,
With the time-delay m bat earlier of I circuit-switched data, carry out 4 times of down-samplings then, obtain the I circuit-switched data of base band, and with its single doubly speed output.The demodulation component cos (ω that I multiply by on the road
IFNT
4x), can be reduced to 1,0 ,-1,0, the sequence of 1....}, and four times of down-samplings of back make that multiply by 0 and-1 point in this sequence can save, the step that therefore multiply by this sequence just can save fully; Because the Q circuit-switched data has certain time-delay through filter, keep homophase again, also need the time-delay that adds that m claps on the I road in order to make I circuit-switched data and Q circuit-switched data.
The Q circuit-switched data is carried out 2 times of down-samplings earlier, and then multiply by (1)
pBe about to data and multiply by { 1 ,-1,1 successively,-1,1....} sequence is carried out filtering to data afterwards, makes to have only required baseband frequency signal to pass through, export the data of a point simultaneously for the sampled point correspondence of per two inputs, data with twice speed in filtering drop to single doubly speed, extract required Q circuit-switched data, and with its single doubly speed output.Because demodulation component-sin (ω on Q road
IFNT
4x) in half point all be to multiply by 0, multiply by 0 point in order to remove the sequence the inside, can multiply by (1) again behind the first twice down-sampling
p
When described Q circuit-switched data was carried out filtering, input data X (i) through after three displacements, obtained X (i-1), X (i-2) and X (i-3) respectively earlier, will multiply by coefficient a after X (i) and X (i-3) addition then
1, multiply by coefficient a after another road X (i-1) and X (i-2) addition equally
2,, obtain filtering output Y (i)=a at last again with these two results added
1[X (i)+X (i-3)]+a
2[X (i-1)+X (i-2)].This filtering mode is applicable to that in the T-DMB system IF spot is the situation of 2.048M.
The maximized characteristics of having utilized hardware circuit and 4 times of speed samplings of low-complexity digital intermediate frequency data method of reseptance of the present invention, optimize and fallen wherein invalid computational process, as long as average each full pattern point is done the multiplication of a fixed coefficient under base band speed, greatly reduce power consumption and complexity.This structure can be useful in IF-FRE f simultaneously
IFBe the baseband sampling rate (4n ± 1) or (2n ±
1/
2) under doubly the situation.
The employed intermediate-frequency receiver scheme of low-complexity digital intermediate frequency data method of reseptance of the present invention can well be operated in the T-DMB system signal receiving system, in the actual test of IF-FRE 2.048MHz, suppress to reach more than the 45db for harmonic wave, can be good at satisfying the performance that system receives, implementation complexity is, as long as average each full pattern point is done the multiplication of a fixed coefficient under base band speed.Simultaneously, select the digital filter of different performance, this programme also can be suitable for the situation of different IF frequency.
Claims (2)
1. a low-complexity digital intermediate frequency data method of reseptance is characterized in that, to intermediate frequency data after the A/D sampling end is sampled with 4 times of baseband sampling rates and is separated into I road and Q road two paths of data,
With the time-delay m bat earlier of I circuit-switched data, carry out 4 times of down-samplings then, obtain the I circuit-switched data of base band, and with its single doubly speed output;
The Q circuit-switched data is carried out 2 times of down-samplings earlier, and then multiply by (1)
p, afterwards data are carried out filtering, make and have only required baseband frequency signal to pass through, export the data of a point simultaneously for the sampled point correspondence of per two inputs, data with twice speed in filtering drop to single doubly speed, extract required Q circuit-switched data, and with its single doubly speed output.
2. low complex degree intermediate frequency data method of reseptance according to claim 1, it is characterized in that when described Q circuit-switched data was carried out filtering, input data X (i) were earlier through after three displacements, obtain X (i-1), X (i-2) and X (i-3) respectively, will multiply by coefficient a after X (i) and X (i-3) addition then
1, multiply by coefficient a after another road X (i-1) and X (i-2) addition equally
2,, obtain filtering output Y (i)=a at last again with these two results added
1[X (i)+X (i-3)]+a
2[X (i-1)+X (i-2)].
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2007100372470A CN101242382A (en) | 2007-02-07 | 2007-02-07 | Receiving method for low-complexity digital middle-frequency data |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2007100372470A CN101242382A (en) | 2007-02-07 | 2007-02-07 | Receiving method for low-complexity digital middle-frequency data |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101242382A true CN101242382A (en) | 2008-08-13 |
Family
ID=39933597
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2007100372470A Pending CN101242382A (en) | 2007-02-07 | 2007-02-07 | Receiving method for low-complexity digital middle-frequency data |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101242382A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102148679A (en) * | 2010-02-05 | 2011-08-10 | 西瑞克斯(北京)通信设备有限公司 | Low-complexity bandwidth signal digital frequency selection method |
CN103095220A (en) * | 2013-01-25 | 2013-05-08 | 西安电子科技大学 | Design method of miniature synthetic aperture radar (SAR) digital down converter based on rapidly-moving finite impulse response (FIR) filter |
-
2007
- 2007-02-07 CN CNA2007100372470A patent/CN101242382A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102148679A (en) * | 2010-02-05 | 2011-08-10 | 西瑞克斯(北京)通信设备有限公司 | Low-complexity bandwidth signal digital frequency selection method |
CN102148679B (en) * | 2010-02-05 | 2013-09-18 | 西瑞克斯通信技术股份有限公司 | Low-complexity bandwidth signal digital frequency selection method |
CN103095220A (en) * | 2013-01-25 | 2013-05-08 | 西安电子科技大学 | Design method of miniature synthetic aperture radar (SAR) digital down converter based on rapidly-moving finite impulse response (FIR) filter |
CN103095220B (en) * | 2013-01-25 | 2015-09-02 | 西安电子科技大学 | Based on the miniature SAR Digtal Down Converter Designing method of fast row FIR filter |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN101657974B (en) | Transceiver front end for software radio systems | |
US7966360B2 (en) | Finite impulse response filter and digital signal receiving apparatus | |
CN101075814B (en) | Digital receiver system based on special digital medium-frequency structure | |
CN102170414B (en) | Demodulation and timing synchronization combined method for GFSK (Gauss Frequency Shift Key) | |
CN110300079B (en) | MSK signal coherent demodulation method and system | |
CN109361634A (en) | The compensation method and system of receiver carrier wave frequency deviation | |
KR20060121126A (en) | Bandpass sampling receiver and the sampling method | |
JP2001517403A (en) | Symbol timing recovery network for carrierless amplitude phase (CAP) signal | |
CN107528805B (en) | PSK signal synchronization method and device suitable for signal analyzer | |
RU122818U1 (en) | DEMODULATOR OF PHASOMANIPULATED SIGNALS | |
CN101242382A (en) | Receiving method for low-complexity digital middle-frequency data | |
CN103596260B (en) | The slotted synchronous method and system of multicarrier gsm system | |
CN200980092Y (en) | A frequency shift keying demodulator based on the locked loops of a password lock | |
CN201048372Y (en) | Special digital intermediate frequency structure based digital receiver system | |
US20020097819A1 (en) | Circuit and method for symbol timing recovery using phase demodulation | |
KR100959229B1 (en) | Data receiving device | |
CN113709073A (en) | Demodulation method of quadrature phase shift keying modulation signal | |
US20080062029A1 (en) | Apparatus and method for demodulating a modulated signal | |
CN114900405B (en) | Soc-based Acars signal demodulation method | |
WO2005107202A1 (en) | Timing reproduction circuit and reception device | |
JP2002300224A (en) | Receiver | |
Hwang et al. | FPGA implementation of an all-digital T/2-spaced QPSK receiver with Farrow interpolation timing synchronizer and recursive Costas loop | |
WO2005006694A1 (en) | Timing extraction device and method, and demodulation device using the timing extraction device | |
JP3623185B2 (en) | Received data demodulator | |
Xiao et al. | Improved implementation of costas loop for dqpsk receivers using fpga |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C12 | Rejection of a patent application after its publication | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20080813 |