CN101237235B - Circuit filter and lock phase circuit - Google Patents

Abstract

The invention relates to a loop filter and a phase-locking loop, wherein, the loop filter comprises a first resistor, a first capacitor, a second resistor, an operational amplifier and a second capacitor; the first resistor is provided with a first end which is coupled to a first node and a second end which is coupled to a second node; the first capacitor is coupled between the second node and earth voltage; the second resistor is provided with a first end which is coupled to the first node and a second end which is coupled to a third node; the operational amplifier is provided with an noninverting input end which is coupled to the second node, an inverted input end which is coupled to the third node, and an output end; the second capacitor is coupled between the output end of the operational amplifier and the third node. The loop filter and the phase-locking loop can provide the same equivalent capacitance values by using smaller area or provide large equivalent capacitance values by utilization of the same area.

Description

Loop filter and phase-locked loop

Technical field

The present invention is relevant for loop filter, especially about a kind of loop filter that can increase capacitance.

Background technology

In present synchronous system (as computer system and communication apparatus), clock generating circuit is unusual part and parcel.For example, (Phase LookLoop, PLL) circuit is widely used in that frequency synthesis, sequential are proofreaied and correct, clock pulse distributes and phase demodulating or the like in the phase-locked loop.

Generally speaking, traditional phase-locked loop can comprise a phase frequency detector (phase/frequency detector, PFD), a current pump (charge pump), a loop filter (loop filter), a voltage-controlled oscillator (voltage controloscillator, VCO) and a frequency divider (divider).The phase frequency detector is a feedback clock pulse and a variation edge (transitional edges) with reference to clock pulse relatively, produces comparison signal, and then makes current pump discharge and recharge.Moreover loop filter can produce control voltage according to the discharging and recharging of current pump, VCO is according to the control voltage swing, determine the frequency of the clock pulse of its output, frequency divider then carries out frequency division to the clock pulse that VCO exported, and output feedback clock pulse is to the phase frequency detector.

Loop filter can comprise at least one capacitor usually in order to filtering noise, and the conference of healing of its equivalent capacitance value makes that the bandwidth (bandwidth) of phase-locked loop is littler, makes phase margin (phase margin) bigger simultaneously.Yet the capacitance of loop filter is bigger, and employed electric capacity also can take the big area of healing.

Summary of the invention

The invention provides a kind of loop filter, comprise one first resistance, have one first end and be coupled to a first node, and one second end is coupled to a Section Point; One first electric capacity is coupled between a Section Point and the earthed voltage; One second resistance has one first end and be coupled to first node, and one second end is coupled to one the 3rd node; One operational amplifier has that a non-inverting input is coupled to Section Point, an inverting input is coupled to the 3rd node, and an output; And one second electric capacity, be coupled between the output and the 3rd node of operational amplifier; This loop filter also comprises: an offset cancellation circuit, in order to the above-mentioned output voltage on the output of detecting above-mentioned operational amplifier, so as to controlling at least one bias current of above-mentioned operational amplifier, make output voltage on the output of above-mentioned operational amplifier equal the input voltage on the above-mentioned non-inverting input; Above-mentioned offset cancellation circuit comprises: a comparator, and detect the above-mentioned output voltage on the output of above-mentioned operational amplifier, and produce the control signal of a correspondence; And a substrate bias controller, in order to according to above-mentioned control signal, control the above-mentioned bias current of above-mentioned operational amplifier; Wherein when the above-mentioned output voltage of above-mentioned operational amplifier was lower than one first reference voltage, above-mentioned comparator produced above-mentioned control signal, made above-mentioned substrate bias controller can adjust above-mentioned bias current, so as to increasing the above-mentioned output voltage of above-mentioned operational amplifier.

The present invention also provides a kind of phase-locked loop, comprises a phase frequency detector, in order to compare the variation edge and the variation edge with reference to clock pulse of a feedback clock pulse, produces a comparison signal; One loop filter comprises one first resistance, have one first end and be coupled to a first node, and one second end is coupled to a Section Point; One first electric capacity is coupled between a Section Point and the earthed voltage; One second resistance has one first end and be coupled to first node, and one second end is coupled to one the 3rd node; One operational amplifier has that a non-inverting input is coupled to Section Point, an inverting input is coupled to the 3rd node, and an output; And one second electric capacity, be coupled between the output and the 3rd node of operational amplifier; One current pump couples first node, according to comparison signal, loop filter is carried out charge or discharge, to produce a control voltage on first node; One voltage controlled oscillator according to control voltage, is exported a pair of clock pulse of answering; And a frequency divider, carry out frequency division in order to the corresponding clock pulse that voltage controlled oscillator is exported, with output feedback clock pulse to the phase frequency detector; This loop filter also comprises: an offset cancellation circuit, use so that the output voltage on the output of above-mentioned operational amplifier equals the input voltage on the above-mentioned non-inverting input; Above-mentioned offset cancellation circuit is detected the above-mentioned output voltage on the output of above-mentioned operational amplifier, so as to controlling at least one bias current of above-mentioned operational amplifier, make the output voltage of above-mentioned operational amplifier equal the above-mentioned input voltage on the above-mentioned non-inverting input; Above-mentioned offset cancellation circuit comprises: a comparator, and detect the above-mentioned output voltage on the output of above-mentioned operational amplifier, and produce the control signal of a correspondence; And a substrate bias controller, in order to according to above-mentioned control signal, control the above-mentioned bias current of above-mentioned operational amplifier; Wherein when the above-mentioned output voltage of above-mentioned operational amplifier was lower than one first reference voltage, above-mentioned comparator produced above-mentioned control signal, made above-mentioned substrate bias controller can adjust above-mentioned bias current, so as to increasing the above-mentioned output voltage of above-mentioned operational amplifier.

Loop filter of the present invention and phase-locked loop can use less area that identical equivalent capacitance value is provided, or utilize area identical that bigger equivalent capacitance value is provided.

Description of drawings

Fig. 1 is an embodiment of a loop filter.

Fig. 2 A is another embodiment of loop filter.

Fig. 2 B is the equivalent circuit diagram of loop filter among Fig. 2 A.

Fig. 3 A is another embodiment of loop filter.

Fig. 3 B is the equivalent circuit diagram of loop filter among Fig. 3 A.

Fig. 4 is another embodiment of loop filter.

Fig. 5 is another embodiment of loop filter.

Fig. 6 is another embodiment of loop filter.

Fig. 7 is an embodiment of phase-locked loop.

Embodiment

For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended diagram, be described in detail below.

Fig. 1 is an embodiment of a loop filter.As shown in Figure 1, this loop filter 11A comprises that a capacitor C 1 has that one first end is coupled to end points ND1 and one second end is coupled to an earth terminal.For example, end points ND1 is the output of the current pump (as shown in Figure 7) of phase-locked loop, but is not limited to this.

Suppose that across the voltage of capacitor C 1 be V1, the electric current I c of the capacitor C of then flowing through 1 can be expressed as:

$\mathrm{Ic}=\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="S2008100855432E00022.png"\; state="\{\{state\}\}">C</figure-callout>}1\&times;\frac{\mathrm{<figure-callout\; id="1"\; label="dV"\; filenames="S2008100855432E00022.png"\; state="\{\{state\}\}">dV</figure-callout>}1}{\mathrm{dt}}---\left(1\right)$

In other words, exist

During for fixing (being that V1 fixes), electric current I c can become a proportional relation with the capacitance of capacitor C 1.

Fig. 2 A is another embodiment of loop filter, and Fig. 2 B is the equivalent circuit diagram of loop filter among Fig. 2 A.Shown in Fig. 2 A, this loop filter 11B is similar to that shown in Figure 1, but comprises that also a current source CS is coupled between node ND1 and the earth terminal, and in parallel with capacitor C 1, in order to provide K doubly to the electric current of electric current I c.In other words, electric current I eq can equal (1+K) doubly to the electric current (being Ieq=Ic+KIc=(1+K) Ic) of electric current I c.

Because the cross-pressure of capacitor C 1 all is V1 among loop filter 11A and the 11B, and electric current I eq be Ic's (1+K) times, so formula (1) can be rewritten into

$\mathrm{Ieq}=(1+K)\&times;\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="S2008100855432E00022.png"\; state="\{\{state\}\}">C</figure-callout>}1\&times;\frac{\mathrm{<figure-callout\; id="1"\; label="dV"\; filenames="S2008100855432E00022.png"\; state="\{\{state\}\}">dV</figure-callout>}1}{\mathrm{dt}}=\mathrm{Ceq}\&times;\frac{\mathrm{<figure-callout\; id="1"\; label="dV"\; filenames="S2008100855432E00022.png"\; state="\{\{state\}\}">dV</figure-callout>}1}{\mathrm{dt}}---\left(2\right)$

Wherein, Ceq is the equivalent capacity of the loop filter 11B shown in Fig. 2 A (being capacitor C 1 and current source CS).Because

With equating among Figure 1A electric current I eq be Ic's (1+K) doubly, so the capacitance of the equivalent capacity Ceq of loop filter 11B can (be Ceq=(1+K) * C1) doubly for (1+K) of the capacitance of capacitor C 1.In other words, loop filter 11B is by the cross-pressure of fixed capacity C1, and (1+K) that will be increased to electric current I c by the electric current I eq that node ND1 flows to earth terminal is doubly, so as the equivalent capacity Ceq of loop filter 11B to be increased to capacitor C 1 capacitance (1+K) doubly.

Therefore, compared to using traditional capacitor to increase equivalent capacitance value, the method can not need to increase considerably area, can also reach the effect that increases capacitance.

Fig. 3 A is another embodiment of loop filter.As shown in Figure 3A, loop filter 11C comprises resistance R X and RY, capacitor C A and an operational amplifier OP1.Operational amplifier OP1 is connected between node ND3 and the resistance R Y in the mode of voltage follower device (source follower).For example, operational amplifier OP1 comprises that a non-inverting input is coupled to node ND3, an output is coupled to resistance R Y, and an inverting input is coupled to its output and resistance R Y.Resistance R X has two ends, and described two ends couple node ND2 and ND3 respectively, and capacitor C A is coupled between node ND3 and the earth terminal, and resistance R Y has one first end and is coupled to output and the inverting input that node ND2 and one second end couple operational amplifier OP1.

Because inverting input and the noninverting input meeting imaginary short (virtual short) of operational amplifier OP1, so resistance R X and RY can be considered and be connected in parallel, so the resistance value of the equivalent resistance RZ of resistance R X and RY will be lower than the resistance value of RX or RY, thereby the electric current of the capacitor C A that flows through also can increase.

Fig. 3 B is the equivalent circuit diagram of loop filter 11C.Because the resistance value of equivalent resistance RZ can be lower than the resistance value of resistance R X or RY, and the capacitance of the equivalent capacity Ceff among the loop filter 11C can be expressed as $\mathrm{Ceff}=\mathrm{CA}\&times;\frac{\mathrm{RX}}{\mathrm{RY}}.$ In other words, the capacitance of equivalent capacitor C eff can increase by the ratio of adjusting resistance R X and RY among the loop filter 11C.Therefore, loop filter 11C can avoid using traditional capacitor to make area increase significantly.Or say that loop filter 11C can use less area that identical equivalent capacitance value is provided compared to traditional capacitor.

Yet, under dc state, have a leakage path at this circuit between node ND3 and the earth terminal, and when frequency analysis, produce a limit, so use the phase-locked loop of this loop filter can't carry out phase-locked exactly near zero point.

Fig. 4 is another embodiment of loop filter.As shown in Figure 4, loop filter 11D is coupled between node ND4 and the earthed voltage, and comprises resistance R 1 and R2, capacitor C 1 and a C2 and an operational amplifier OP2.Operational amplifier OP2 is connected between node ND5 and the resistance R 2 in the mode of voltage follower device (source follower).For example, operational amplifier OP2 comprises that a non-inverting input is coupled to node ND5, an output couples resistance R 2 and node ND6 by capacitor C 2, and an inverting input is coupled to node ND6, and is coupled to its output by capacitor C 2.Resistance R 1 has two ends, described two ends couple node ND4 and ND5 respectively, capacitor C 1 is coupled between node ND5 and the earth terminal, and resistance R 2 has one first end and is coupled to inverting input and the capacitor C 2 that node ND4 and one second end couple operational amplifier OP2.

Similarly, the capacitance of the equivalent capacity of loop filter 11D can increase by the ratio of adjusting resistance R 1 and R2.Because the capacitor C 2 between node ND6 and the operational amplifier OP2, so the leakage path among the loop filter 11C will be blocked among Fig. 3 A, and limit that leakage path produces also can be eliminated in the lump.

Fig. 5 is another embodiment of loop filter.As shown in Figure 5, loop filter 11E is similar to the loop filter 11D among Fig. 4, but comprises that also a capacitor C 3 is coupled between node ND4 and the earthed voltage.Similarly, the capacitance of the equivalent capacity of loop filter 11D can increase by the ratio of adjusting resistance R 1 and R2.

Fig. 6 is another embodiment of loop filter.As shown in Figure 6, loop filter 11F is similar to the loop filter 11E among Fig. 5, but comprise that also an offset cancellation circuit (offset elimination circuit) 121 is in order to the output voltage V 3 on the output of detecting operational amplifier OP2, produce a control signal CS, bias current I+ and the I-of control operational amplifier OP2 make the output voltage V 3 of operational amplifier OP2 approximate its input voltage V1.Offset cancellation circuit 121 comprises a comparator C P and a substrate bias controller 123.Comparator C P comprises that a first input end is coupled to the output that the first reference voltage VREF1 (for example 1.0V), one second input are coupled to operational amplifier CP2, and one the 3rd input is coupled to one second reference voltage VREF2 (for example 1.5V).Generally speaking, the input voltage V1 of operational amplifier OP2 can drop between two reference voltage VREF1 and the VREF2.

For example, when the output voltage V 3 of operational amplifier OP2 is lower than reference voltage VREF1, comparator C P can control substrate bias controller 123 by control signal CS, so that adjust bias current I+ and the I-of operational amplifier OP2, makes the output voltage V 3 of operational amplifier OP2 rise.When the output voltage V 3 of operational amplifier OP2 is higher than reference voltage VREF2, comparator C P can control substrate bias controller 123 by control signal CS, so that adjust bias current I+ and the I-of operational amplifier OP2, make the output voltage V 3 of operational amplifier OP2 descend.Therefore, the output voltage V 3 of operational amplifier OP2 will remove to follow input voltage V1, and meaning is that the direct current offset (capacitor C 2 causes) of input voltage V1 and output voltage V 3 can be eliminated.In addition, when the output voltage V 3 of operational amplifier OP2 fell between two reference voltage VREF1 and the VREF2, offset cancellation circuit 121 was just no longer adjusted bias current I+ and the I-of operational amplifier OP2.

Fig. 7 is an embodiment of phase-locked loop.As shown in Figure 7, phase-locked loop 100 comprises a phase frequency detector (phase/frequency detector, PFD) 11, one current pump (charge pump), 13, one loop filter (loop filter), 15, one voltage controlled oscillator (voltage control oscillator, VCO) 17 and one frequency divider (divider) 19.Phase frequency detector 11 relatively feed back clock pulse CLK_FB and with reference to the variation of clock pulse CLK_REF along (transitional edges), produce comparison signal UP and DN, and then make current pump 13 discharge and recharge.

For example, when the variation of feedback clock pulse CLK_FB along be ahead of with reference to the variation of clock pulse CLK_REF along the time, phase frequency detector 11 will pass through comparison signal UP and DN, in order to switch SW 1 disconnection, simultaneously with switch SW 2 conductings, so that the action that loop filter 15 is discharged.On the contrary, when the variation of feedback clock pulse CLK_FB along lag behind with reference to the variation of clock pulse CLK_REF along the time, phase frequency detector 11 will pass through comparison signal UP and DN, in order to switch SW 1 conducting, simultaneously switch SW 2 is disconnected, so that the action that loop filter 15 is charged.

Loop filter 15 is coupled to the node ND7 in the current pump 13, in order to according to the discharging and recharging of current pump 13, produces control voltage V _CFor example, when but loop filter 15 is when being realized by the loop filter 11D～11F among Fig. 4 to Fig. 6, node ND4 among loop filter 11D～11F is coupled to the node ND7 of current pump 13, and as control voltage, export VCO17 to across the system of the voltage between node ND4 and the earth terminal.

VCO 17 is according to control voltage V _CSize determines the frequency of the clock pulse CLK_VCO of its output.For example, as control voltage V _CWhen (being the current potential on the node ND4) increased, the frequency of the clock pulse CLK_VCO that VCO 17 is exported also can increase.On the contrary, when control voltage VC (being the current potential on the node ND4) reduced, the frequency of the clock pulse CLK_VCO that VCO17 exported also can reduce.19 of frequency dividers carry out frequency division in order to the clock pulse CLK_VCO that VCO 17 is exported, and output feedback clock pulse CLK_FB is to phase frequency detector 11.

In this embodiment, because loop filter 11D～11F compared to traditional capacitor, can use less area that identical equivalent capacitance value is provided, or utilize area identical that bigger equivalent capacitance value is provided.Therefore, use the phase-locked loop of loop filter 11D, 11E or 11F can use less area or under area identical, have littler bandwidth (bandwidth) and bigger phase margin (phasemargin).

The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.

Being simply described as follows of symbol in the accompanying drawing:

11: the phase frequency detector

13: current pump

15: loop filter

17: voltage controlled oscillator

19: frequency divider

11A～11F: loop filter

121: offset cancellation circuit

123: substrate bias controller

100: the phase-locked loop

OP1～OP2: operational amplifier

CP: comparator

CS: current source

C1～C3, CA, Ceff: electric capacity

RX, RY, RZ, R1～R2: resistance

ND1～ND7: node

V1～V3: voltage

VREF1, VREF2: reference voltage

Vc: control voltage

CS: control signal

I+, I-: bias current

Ic, Ieq: electric current

UP, DN: comparison signal

CLK_FB: feedback clock pulse

CLK_REF: with reference to clock pulse

CLK_VCO: clock pulse.

Claims (8)

1. a loop filter is characterized in that, comprising:

One first resistance has one first end and be coupled to a first node, and one second end is coupled to a Section Point;

One first electric capacity is coupled between an above-mentioned Section Point and the earthed voltage;

One second resistance has one first end and be coupled to above-mentioned first node, and one second end is coupled to one the 3rd node;

One operational amplifier has that a non-inverting input is coupled to above-mentioned Section Point, an inverting input is coupled to above-mentioned the 3rd node, and an output; And

One second electric capacity is coupled between the output and above-mentioned the 3rd node of above-mentioned operational amplifier;

This loop filter also comprises:

One offset cancellation circuit, in order to the output voltage on the output of detecting above-mentioned operational amplifier, so as to controlling at least one bias current of above-mentioned operational amplifier, make the above-mentioned output voltage of above-mentioned operational amplifier equal the input voltage on the above-mentioned non-inverting input;

Above-mentioned offset cancellation circuit comprises:

One comparator is detected the above-mentioned output voltage on the output of above-mentioned operational amplifier, and produces the control signal of a correspondence; And

One substrate bias controller in order to according to above-mentioned control signal, is controlled the above-mentioned bias current of above-mentioned operational amplifier;

Wherein when the above-mentioned output voltage of above-mentioned operational amplifier was lower than one first reference voltage, above-mentioned comparator produced above-mentioned control signal, made above-mentioned substrate bias controller can adjust above-mentioned bias current, so as to increasing the above-mentioned output voltage of above-mentioned operational amplifier.

2. loop filter according to claim 1 is characterized in that, also comprises:

One the 3rd electric capacity is coupled between above-mentioned first node and the above-mentioned earthed voltage.

3. loop filter according to claim 1, it is characterized in that, when the above-mentioned output voltage of above-mentioned operational amplifier is higher than one second reference voltage, above-mentioned comparator produces above-mentioned control signal, make above-mentioned substrate bias controller can adjust above-mentioned bias current, so as to reducing the above-mentioned output voltage of above-mentioned operational amplifier, above-mentioned first reference voltage is less than above-mentioned second reference voltage.

4. loop filter according to claim 3, it is characterized in that, when the above-mentioned output voltage of above-mentioned operational amplifier was between above-mentioned first reference voltage, above-mentioned second reference voltage, above-mentioned offset cancellation circuit was not adjusted the above-mentioned bias current of above-mentioned operational amplifier.

5. a phase-locked loop is characterized in that, comprising:

One phase frequency detector in order to compare the variation edge and the variation edge with reference to clock pulse of a feedback clock pulse, produces a comparison signal;

One loop filter comprises:

One first resistance has one first end and be coupled to a first node, and one second end is coupled to a Section Point;

One first electric capacity is coupled between an above-mentioned Section Point and the earthed voltage;

One second resistance has one first end and be coupled to above-mentioned first node, and one second end is coupled to one the 3rd node;

One operational amplifier has that a non-inverting input is coupled to above-mentioned Section Point, an inverting input is coupled to above-mentioned the 3rd node, and an output; And

One second electric capacity is coupled between the output and above-mentioned the 3rd node of above-mentioned operational amplifier;

One current pump couples above-mentioned first node, according to above-mentioned comparison signal, above-mentioned loop filter is carried out charge or discharge, to produce a control voltage on above-mentioned first node;

One voltage controlled oscillator according to above-mentioned control voltage, is exported a pair of clock pulse of answering; And

One frequency divider carries out frequency division in order to the above-mentioned corresponding clock pulse that above-mentioned voltage controlled oscillator is exported, to export above-mentioned feedback clock pulse to above-mentioned phase frequency detector;

This loop filter also comprises:

One offset cancellation circuit is used so that the output voltage on the output of above-mentioned operational amplifier equals the input voltage on the above-mentioned non-inverting input;

Above-mentioned offset cancellation circuit is detected the above-mentioned output voltage on the output of above-mentioned operational amplifier, so as to controlling at least one bias current of above-mentioned operational amplifier, make the output voltage of above-mentioned operational amplifier equal the above-mentioned input voltage on the above-mentioned non-inverting input;

Above-mentioned offset cancellation circuit comprises:

One comparator is detected the above-mentioned output voltage on the output of above-mentioned operational amplifier, and produces the control signal of a correspondence; And

One substrate bias controller in order to according to above-mentioned control signal, is controlled the above-mentioned bias current of above-mentioned operational amplifier;

Wherein when the above-mentioned output voltage of above-mentioned operational amplifier was lower than one first reference voltage, above-mentioned comparator produced above-mentioned control signal, made above-mentioned substrate bias controller can adjust above-mentioned bias current, so as to increasing the above-mentioned output voltage of above-mentioned operational amplifier.

6. phase-locked loop according to claim 5 is characterized in that, also comprises:

One the 3rd electric capacity is coupled between above-mentioned first node and the above-mentioned earthed voltage.

7. phase-locked loop according to claim 5, it is characterized in that, when the above-mentioned output voltage of above-mentioned operational amplifier is higher than one second reference voltage, above-mentioned comparator produces above-mentioned control signal, make above-mentioned substrate bias controller can adjust above-mentioned bias current, so as to reducing the above-mentioned output voltage of above-mentioned operational amplifier, above-mentioned first reference voltage is less than above-mentioned second reference voltage.

8. phase-locked loop according to claim 7, it is characterized in that, when the above-mentioned output voltage of above-mentioned operational amplifier was between above-mentioned first reference voltage, above-mentioned second reference voltage, above-mentioned offset cancellation circuit was not adjusted the above-mentioned bias current of above-mentioned operational amplifier.

Images