CN101227246A - Method and apparatus for master-salve clock synchronization - Google Patents

Abstract

The invention discloses a method and a device for synchronizing a master clock and a slave clock, the method comprises: sending synchronous request message to the master clock for many times in a simultaneous cycle by the slave clock, recording the corresponding the time value, then, utilizing a median average filtering algorithm to obtain the optimum time migration amount, utilizing the time migration amount to adjust the slave clock, eliminating the delay inequality which is caused by stochastic disturbance and burst interference of a network communication channel between the master clock and the slave clock, guaranteeing the stability of slave clock signals, and increasing the synchronous preciseness of the master clock and the slave clock.

Description

A kind of method of principal and subordinate's clock synchronization and device

Technical field

The present invention relates to universal Clock Synchronization Technology, relate in particular to a kind of method and device of principal and subordinate's clock synchronization.

Background technology

Institute for Electrical and Electronics Engineers 1588 agreements, full name is the precision interval clock synchronous protocol standard of network measure and control system, claim precise synchronization clock protocols (PTP again, Precision Time Protocol), it is a kind of network clocking synchronous protocol that IEEE proposes, be used to the environment of realizing that high accuracy clock is synchronous, because its precision can reach the microsecond level, be widely used in Ethernet, communication system at present, distributed system is measured and field such as control.

The IEEE1588 agreement realizes clock synchronization by the switching clock sync message.In synchronizing process, by from the time clockwise master clock initiate the synchronization request message, after master clock is received the synchronization request message that sends from clock, to return the sync response message from clock, from clock according to the timestamp the sync response message and master clock to from the time-delay calculating of clock and the deviation of master clock, utilize time deviation that the clock of this locality is adjusted and calibrated then.

Its expression formula of calculating synchronously is as follows:

Offset _i＝Tm _i+Delay-Ts _i(1)

${\mathrm{Ts}}_i^{\mathrm{\Δ}}={\mathrm{Ts}}_i^{\mathrm{\Γ}}+{\mathrm{Offset}}_i---\left(2\right)$

Wherein, in the formula (1), Tm _iAnd Ts _iBe respectively i when subsynchronous, master clock and from the timestamp of clock at the bottom record;

In the formula (2), Offset _iBe i when subsynchronous, that go out from clock calculation and deviation master clock;

Ts _i ^ΓBe the PTP system time before this subsynchronous modification system clock;

Ts _i ^ΔBe this PTP system time after subsynchronous;

Delay is that master clock arrives the circuit time delay value from clock.

Suppose that the circuit time-delay is symmetrical between principal and subordinate's clock, then can calculate that promptly time delay value can be calculated by following formula and learn by timestamp:

${\mathrm{Delay}}_i=\frac{[({\mathrm{Ts}}_i-{\mathrm{Tm}}_i)+({\mathrm{Tm}}_i^{\′}-{\mathrm{Ts}}_i^{\′})]}{2}---\left(3\right)$

Wherein, Ts in the formula (3) _iIt is i time from clock tranmitting data register synchronization request message when subsynchronous;

Tm _iReceive the time of synchronization request message for master clock;

Tm _i' send the time of sync response message for master clock;

Ts _i' for receive the time of sync response message from clock.

Fig. 1 (a) is existing single clock synchronization mode process schematic diagram based on the IEEE1588 agreement, and shown in Fig. 1 (a), this process comprises:

At first, send synchronization request message 103 to master clock side 102 from clock side 101, and the time T s of record synchronization request message 103 transmissions _iMaster clock side 102 receives synchronization request message 103, and notes the time T m that receives synchronization request message 103 _i

Secondly, master clock side 102 is asked response message 104 to sending from clock side 101, and the transmitting time Tm of record request response message 104 _i'; Receive the time of reception Ts of request response message 104 and record request response message 104 from clock side 101 _i';

Then, master clock side 102 sends sync response follow-up message 105, informs from the time of reception Tm of clock side 101 synchronization request messages 103 _iTransmitting time Tm with request response message 104 _i';

At last, according to four time point Ts from the clock side _i, Tm _i, Tm _i' and Ts _i' substitution formula (3) is calculated, and draws time delay value, and time delay value substitution formula (1) is obtained time offset value, then time offset value substitution formula (2) is obtained the fiducial time from clock, thus calibrating this locality from clock.

But because the application of IEEE1588 agreement is to be based upon under this ideal conditions that the propagation delay time of principal and subordinate's clock signal is a symmetry, and the real network channel is difficult to satisfy this condition.If when having random disturbances, bursty interference in the clock transfer channel, measured time-delay can exist than mistake, thereby has destroyed the symmetry of time delay, and then has influenced the stability of principal and subordinate's clock synchronization state and from the precision of clock.

Summary of the invention

In view of this, main purpose of the present invention is to provide a kind of method of principal and subordinate's clock synchronization, eliminates random error and sudden error, guarantees the synchronization accuracy of the stable and raising of principal and subordinate's clock synchronization state from clock.

Another object of the present invention is to provide a kind of device of principal and subordinate's clock synchronization, by from clock the equipment of company provide and the master clock clock signal synchronous.

For achieving the above object, technical scheme of the present invention is achieved in that

A kind of method of principal and subordinate's clock synchronization, this method comprises:

A, from the time clockwise master clock initiate the exchange of synchronised clock sync message, and write down each time value of this process of transmitting;

B, utilize each time value of described record to calculate the time delay value of this synchronizing process;

C, in same synchronizing cycle, repeat repeatedly the process of step a～step b, obtain a plurality of time delay values, and utilize described a plurality of time delay value to obtain the optimum delay value, and try to achieve the Best Times side-play amount;

D, select corresponding weights for use, in conjunction with described Best Times side-play amount and from the current time value of clock, to calibrating from clock according to the Best Times side-play amount.

Wherein, described each time value of step a is respectively from the time T s of clock tranmitting data register synchronization request message ₁, master clock receives the time T m of synchronization request message ₁, master clock sends the time T m of sync response message ₁', receive the time T s of sync response message from clock ₁'.

The time delay value of described this synchronizing process of calculating is with described each time value Ts ₁, Tm ₁, Tm ₁' and Ts ₁', the substitution formula:

${\mathrm{<figure-callout\; id="1"\; label="Delay"\; filenames="S2008100569661E00021.png"\; state="\{\{state\}\}">Delay</figure-callout>}}_1=\frac{[({\mathrm{Ts}}_1-{\mathrm{Tm}}_1)+({\mathrm{<figure-callout\; id="1"\; label="Tm"\; filenames="S2008100569661E00021.png"\; state="\{\{state\}\}">Tm</figure-callout>}}_1^{\&prime;}-{\mathrm{<figure-callout\; id="1"\; label="Ts"\; filenames="S2008100569661E00021.png"\; state="\{\{state\}\}">Ts</figure-callout>}}_1^{\&prime;})]}{2},$ Calculate gained;

Wherein, Delay ₁Time delay value for this synchronizing process.

The described a plurality of time delay values of step c are the exchanges through k clock synchronization message, obtain k time delay value.

Wherein, the process of utilizing described a plurality of time delay value to obtain the optimum delay value is:

A more described k time delay value removes a maximum and a minimum value, then with remaining k-2 value substitution formula:

$\stackrel{\&OverBar;}{\mathrm{Delay}}=\frac{1}{k-2}\underset{i=1}{\overset{k-2}{\mathrm{\&Sigma;}}}{\mathrm{Delay}}_i=\frac{1}{k-2}\underset{i=1}{\overset{k-2}{\mathrm{\&Sigma;}}}\frac{[({\mathrm{Ts}}_i-{\mathrm{Tm}}_i)+({\mathrm{Tm}}_i^{\&prime;}-{\mathrm{Ts}}_i^{\&prime;})]}{2}$ By calculating;

Wherein,

Be the optimum delay value of this synchronizing process, the span of k is 2 times at least,

Ts ₁Be the time from clock tranmitting data register synchronization request message, Tm ₁For master clock receives time of synchronization request message, Tm ₁' send time of sync response message, Ts for master clock ₁' for receive the time of sync response message from clock.

The described process of asking the Best Times side-play amount is the optimum delay value with this synchronizing cycle

The substitution formula:

$\stackrel{\&OverBar;}{\mathrm{Offset}}={\mathrm{Tm}}_i+\stackrel{\&OverBar;}{\mathrm{Delay}}-{\mathrm{Ts}}_i,$ By calculating gained;

Wherein,

Best Times side-play amount for this synchronizing cycle;

Tm _iAnd Ts _iBe respectively when i is subsynchronous in this synchronizing cycle, master clock is at the time point of bottom record with from the time value of clock at the time point of bottom record.

The described process of corresponding weights of selecting for use is: when the absolute value of Best Times side-play amount during greater than preset threshold, weights are 1～2 value, and the big more then weights of the absolute value of Best Times side-play amount are more little, but all the time greater than 1; When the absolute value of Best Times side-play amount during less than preset threshold, weights are 0～1 value, and the big more then weights of the absolute value of Best Times side-play amount are big more, but all the time less than 1.

Described to carrying out calibration process: as to be according to formula from clock:

${\mathrm{Ts}}^{\mathrm{\&Delta;}}={\mathrm{Ts}}^{\mathrm{\&Gamma;}}+P*\stackrel{\&OverBar;}{\mathrm{Offset}};$

Calculate gained; Wherein, Ts ^ΓFor in this synchronizing cycle from the clock current system time; Ts ^ΔFor in this synchronizing cycle from clock through the calibration after system time; P is selected weights in this synchronizing cycle.

Described the i time, be meant described k-2 calculation delay value Delay in this synchronizing cycle _iProcess in, time delay value that is calculated and optimum delay value

Compare that time of difference minimum.

Further comprise after the described steps d:

E, adjust synchronization times k ' and the synchronization of time intenals T ' of next synchronizing cycle according to the Best Times side-play amount, and by calculating the optimum delay value of described next synchronizing cycle;

F, return step a, carry out principal and subordinate's clock adjustment process of described next synchronizing cycle, until the Best Times side-play amount be zero or synchronization times reach maximum.

Described synchronization times and the synchronization of time intenals value of adjusting next synchronizing cycle, be that the Best Times side-play amount of a current Best Times side-play amount and a last synchronizing cycle is divided by, obtain a ratio, (k T) is worth conduct synchronization times k ', the synchronization of time intenals value T ' of next synchronizing cycle to selection is preset according to described ratio size one group; Wherein, k is a synchronization times, and T is the synchronization of time intenals value.

The process of described optimum delay value by calculating next synchronizing cycle is:

If k ' 〉=k, in then next synchronizing cycle according to sync interval T ' carry out (k '-k+1) inferior clock synchronization message switching, obtain (k '-k+1) individual new time delay value, abandon first time delay value of previous synchronizing cycle of gained then, and (k-1) the individual time delay value that will be left and described (k '-k+1) individual time delay value is formed the new individual time delay value of k ', utilize median average filter algorithm at last, obtain the average delay value, as the optimum delay value of a back synchronizing cycle; Wherein, k is the synchronization times of this synchronizing cycle;

If k '＜k, carry out the clock synchronization message switching again 1 time according to sync interval T ' in then next synchronizing cycle, that counts last synchronizing cycle in obtains k, obtain (k+1) individual time delay value altogether, abandon (k-k '+1) inferior time delay value of last synchronizing cycle, the remaining individual time delay value of k ' is carried out the median average filter again calculate, obtain the optimum delay value of average delay value as next synchronizing cycle; Wherein, k is the synchronization times of this synchronizing cycle.

A kind of device of principal and subordinate's clock synchronization, this device comprise master clock, time-delay calculation module, and side-play amount computing module, state transformation device reach from clock; Wherein,

Master clock is used to described principal and subordinate's clock synchronization calibrating installation that standard clock signal is provided;

The time-delay calculation module, be used for according to from the time clockwise master clock sent the clock synchronization message time Time Calculation optimum delay value of gathering;

The side-play amount computing module is used for according to described optimum delay value calculating optimum time offset;

The state transformation device is used for selecting suitable weights according to the size of described Best Times side-play amount; And

From clock, be used for calibrating in conjunction with self current system time according to described Best Times side-play amount and corresponding weights, and the system time after will calibrating is as local clock, for the time-delay calculation module and other equipment provides and master clock keeps clock signal synchronous.

Wherein, described time-delay calculation module also is used for the synchronization times of next synchronizing cycle and the adjustment of synchronization of time intenals value.

The method of principal and subordinate's clock synchronization provided by the present invention and device have the following advantages:

1) the inventive method adopts in the synchronizing cycle repeatedly tranmitting data register sync message, and try to achieve a plurality of time delay values by sampling, utilize filtering algorithm to ask optimum delay value and Best Times side-play amount again, to the mode of adjusting from clock, the random disturbances of network channel between principal and subordinate's clock and the time delay error that bursty interference causes have been eliminated, guarantee the stability of principal and subordinate's clock status, improved the synchronization accuracy of principal and subordinate's clock.

2) among the present invention, default many group synchronization times and synchronization of time intenals value in the time-delay calculation module, compare with the Best Times side-play amount of synchronizing cycle last time by utilizing this Best Times side-play amount, select described default synchronization times and synchronization of time intenals according to ratio, utilize once more as next time synchronization times and synchronization of time intenals, make from clock to possess the ability of adjusting synchronization times and synchronization of time intenals according to the network condition self adaptation, further improved from clock and master clock maintenance synchronization performance.

Description of drawings

Fig. 1 (a) is existing single clock synchronization mode process schematic diagram based on the IEEE1588 agreement;

Fig. 1 (b) is k clock synchronization mode process schematic diagram in the embodiment of the invention;

Fig. 2 is the implementation method flow chart of principal and subordinate's clock synchronization in the embodiment of the invention;

Fig. 3 is principal and subordinate's clock synchronization calibrating installation and a course of work schematic diagram in the embodiment of the invention.

Embodiment

Below in conjunction with accompanying drawing and embodiments of the invention method of the present invention is described in further detail.

Fig. 1 (b) is k clock synchronization mode process schematic diagram in the embodiment of the invention, shown in Fig. 1 (b), from the promoter of clock as the synchronization request message, in a synchronizing cycle, carry out clock synchronization j time with master clock, each clock synchronization need be carried out the exchange of k clock synchronization message.

Fig. 2 is the method flow diagram of principal and subordinate's clock synchronization in the embodiment of the invention, and as shown in Figure 2, the principal and subordinate's clock synchronization process in synchronizing cycle is that example describes, and this method comprises:

Step 201: from the time clockwise master clock initiate the exchange of clock synchronization message, obtain the time value Ts of four time points ₁, Tm ₁, Tm ₁' and Ts ₁'.

From the time clockwise master clock initiate the exchange of clock synchronization message, be to initiate according to the mode of IEEE1588 agreement regulation.

Described Ts ₁Be the 1st when subsynchronous, send time of synchronization request message, Tm from clock ₁For master clock receives time of synchronization request message, Tm ₁' send time of sync response message, Ts for master clock ₁' for receive the time of sync response message from clock.

Step 202: the time delay value that calculates this synchronizing process.

Here, calculating the synchronizing process time delay value, is with time value Ts ₁, Tm ₁, Tm ₁' and Ts ₁', substitution formula (3) obtains:

${\mathrm{<figure-callout\; id="1"\; label="Delay"\; filenames="S2008100569661E00021.png"\; state="\{\{state\}\}">Delay</figure-callout>}}_1=\frac{[({\mathrm{Ts}}_1-{\mathrm{Tm}}_1)+({\mathrm{<figure-callout\; id="1"\; label="Tm"\; filenames="S2008100569661E00021.png"\; state="\{\{state\}\}">Tm</figure-callout>}}_1^{\&prime;}-{\mathrm{<figure-callout\; id="1"\; label="Ts"\; filenames="S2008100569661E00021.png"\; state="\{\{state\}\}">Ts</figure-callout>}}_1^{\&prime;})]}{2}---\left(4\right)$

Formula (4) is calculated, obtained this time delay value.

Step 203: in a synchronizing cycle, repeat the process of k step 201～step 203, obtain k time delay value.

Wherein, the size of k value can be adjusted according to the quality of Network Transmission situation and the time delay size adaptation of transmission line, and the value of k is at least greater than 2.

Step 204: ask the optimum delay value.

Here, adopt filtering algorithm to ask the optimum delay value, with the optimum delay value as the synchronous time delay value of this synchronizing cycle of internal clock.

Fig. 3 is principal and subordinate's clock synchronization calibrating installation and a course of work schematic diagram in the embodiment of the invention, and as shown in Figure 3, this filtering algorithm is finished in time-delay calculation module 302.

Described filtering algorithm, comprise median average filter algorithm etc., with median average filter algorithm is example, be specially: compare k time delay value, remove a maximum and a minimum value, with the time delay value of remaining k-2 mean value that is worth as this synchronizing cycle of inter-sync process, computing formula is as follows:

$\stackrel{\&OverBar;}{\mathrm{Delay}}=\frac{1}{k-2}\underset{i=1}{\overset{k-2}{\mathrm{\&Sigma;}}}{\mathrm{Delay}}_i=\frac{1}{k-2}\underset{i=1}{\overset{k-2}{\mathrm{\&Sigma;}}}\frac{[({\mathrm{Ts}}_i-{\mathrm{Tm}}_i)+({\mathrm{Tm}}_i^{\&prime;}-{\mathrm{Ts}}_i^{\&prime;})]}{2}---\left(5\right)$

Wherein, in the formula (5)

Optimum delay value for this synchronizing process.

Step 205: calculate Best Times side-play amount, and select suitable weights according to the Best Times side-play amount from clock, and then to calibrating from clock.

As shown in Figure 3, calculate Best Times side-play amount, finish by side-play amount computing module 303 from clock.

Described calculating optimum time offset is with the optimum delay value

Substitution formula (1) is by calculating the Best Times side-play amount

, as the formula (6):

$\stackrel{\&OverBar;}{\mathrm{Offset}}={\mathrm{Tm}}_i+\stackrel{\&OverBar;}{\mathrm{Delay}}-{\mathrm{Ts}}_i---\left(6\right)$

Wherein, Tm _iAnd Ts _iBe respectively when i is subsynchronous in this synchronizing cycle, master clock is at the time point of bottom record with from the time value of clock at the time point of bottom record.

Described the i time, be meant described k-2 calculation delay value Delay in this synchronizing cycle _iProcess in, time delay value that is calculated and optimum delay value

Compare that time of difference minimum.

Described according to the Best Times side-play amount

Selecting weights, is that state transformation device 304 is selected corresponding weights according to the size of Best Times side-play amount with Best Times side-play amount input state converter 304, and then to being that local clock is calibrated from clock 305.

Described weights are to be used to compensate parameter from clock jitter according to the real network environment set; If

For negative, then be embodied in from the clock current time more leading than the current time of master clock; If

For just, then be embodied in from the clock current time and lag behind than the master clock current time. The value of size decision weights of absolute value, determine different threshold values according to different network conditions; When

Absolute value during greater than preset threshold, weights are 1～2 value,

The big more then weights of absolute value are more little, but all the time greater than 1; When Absolute value during less than preset threshold, weights are 0～1 value,

Big more then weights are big more, but all the time less than 1.

For example, given threshold is set at 1, if

Absolute value be 1.3＞1 o'clock, then weights select 1.5; If Absolute value be 1.9＞1 o'clock, then weights select 1.2; If

Absolute value be 0.7＜1 o'clock, then weights select 0.9; If

Absolute value be 0.4＜1 o'clock, then weights select 0.7 or the like.

As follows to the process of calibrating from clock: Best Times side-play amount and corresponding weights are multiplied each other, add in this synchronizing cycle from the clock current system time, thus the system time after obtaining calibrating from clock.Described to calibrating from clock, carry out according to following formula:

${\mathrm{Ts}}^{\mathrm{\&Delta;}}={\mathrm{Ts}}^{\mathrm{\&Gamma;}}+P*\stackrel{\&OverBar;}{\mathrm{Offset}}---\left(7\right)$

Ts in the formula (7) ^ΓFor in this synchronizing cycle from the clock current system time;

Ts ^ΔFor in this synchronizing cycle from clock through the calibration after system time;

P is selected weights in this synchronizing cycle.

Step 206: the synchronization times k and the synchronization of time intenals T that adjust next synchronizing cycle according to the Best Times side-play amount.

Be specially: the Best Times side-play amount is fed back in the time-delay calculation module 302 as parameter, and (k, T) value is as (k to be preset with one group in the time-delay calculation module 302 ₁, T ₁), (k ₂, T ₂), (k ₃, T ₃) ... (k _n, T _n), with the Best Times side-play amount of Best Times side-play amount and previous synchronizing cycle

Be divided by, draw ratio n, promptly $n=\frac{{\stackrel{\&OverBar;}{\mathrm{Offset}}}_i}{{\stackrel{\&OverBar;}{\mathrm{Offset}}}_{i-1}},$ Select one group of corresponding (k according to the size of ratio n then _i, T _i) value, be used for further determining next synchronizing cycle of interior synchronization times k ', and with T _iSynchronization of time intenals T ' as next synchronizing cycle.

Described size according to ratio n is selected corresponding (k _i, T _i) process of value is: if described ratio n greater than 1, illustrates the Network Transmission situation just in variation, then need the one group of (k that selects the k value less _i, T _i); If described ratio less than 1, illustrates that the Network Transmission situation improves, then need the one group of (k that selects for use the k value bigger _i, T _i).

If k ' 〉=k, in then next synchronizing cycle according to sync interval T ' carry out (k '-k+1) inferior clock synchronization message switching, obtain (k '-k+1) individual new time delay value, abandon first time delay value of previous synchronizing cycle of gained then, and (k-1) the individual time delay value that will be left and described (k '-k+1) individual time delay value is formed the new individual time delay value of k ', utilize median average filter algorithm at last, obtain the average delay value, as the optimum delay value of a back synchronizing cycle; Wherein, k is the synchronization times of this synchronizing cycle.First time delay value that abandons previous synchronizing cycle of gained is to carry out according to the regulation of sliding window algorithm, promptly adds new value and then needs to abandon a top value, slides successively and handles, and the step-length of window is constant.

If k '＜k, carry out the clock synchronization message switching again 1 time according to sync interval T ' in then next synchronizing cycle, that counts last synchronizing cycle in obtains k, obtain (k+1) individual time delay value altogether, abandon (k-k '+1) individual time delay value of last synchronizing cycle, the remaining individual time delay value of k ' is carried out the median average filter again calculate, obtain the optimum delay value of average delay value as next synchronizing cycle; Wherein, k is the synchronization times of this synchronizing cycle.

Described median average filter algorithm, its formula is as follows:

${\stackrel{\&OverBar;}{\mathrm{Delay}}}^{\&prime;}=\frac{1}{k^{\&prime;}-2}\underset{i=1}{\overset{k^{\&prime;}-2}{\mathrm{\&Sigma;}}}{\mathrm{Delay}}_i=\frac{1}{k^{\&prime;}-2}\underset{i=1}{\overset{k^{\&prime;}-2}{\mathrm{\&Sigma;}}}\frac{[({\mathrm{Ts}}_i-{\mathrm{Tm}}_i)+({\mathrm{Tm}}_i^{\&prime;}-{\mathrm{Ts}}_i^{\&prime;})]}{2}---\left(8\right).$

In the formula (8), k ' is the synchronization times of next synchronizing cycle;

Optimum delay value for next synchronizing cycle.

Step 207: return step 201, carry out principal and subordinate's clock adjustment process of described next synchronizing cycle, until the Best Times side-play amount be zero or the clock synchronization number of times reach the maximum clock synchronization times.

Fig. 3 is principal and subordinate's clock synchronization calibrating installation and a course of work schematic diagram in the embodiment of the invention, and as shown in Figure 3, this device comprises master clock 301, time-delay calculation module 302, side-play amount computing module 303, state transformation device 304 and from clock 305, wherein,

Master clock 301 is used to described principal and subordinate's clock synchronization calibrating installation that standard clock signal is provided.

Time-delay calculation module 302, be used for the Time Calculation optimum delay value of gathering when the clock synchronization message that master clock 301 is sent and synchronization times and the synchronization of time intenals of adjusting next synchronizing cycle according to the Best Times side-play amount that side-play amount computing module 303 is fed back according to from clock 305.

Side-play amount computing module 303 is used for according to optimum delay value calculating optimum time offset, and the Best Times side-play amount is fed back to time-delay calculation module 302 and is sent to state transformation device 304.

State transformation device 304 is used for selecting corresponding weights according to the size of Best Times side-play amount, weights is offered from clock 305 be used for the calibration from clock 305.

From clock 305, be used for calibrating in conjunction with self current system time according to Best Times side-play amount and corresponding weights, and the system time after will calibrating is as local clock, for the time-delay calculation module and other equipment provides and master clock 301 keeps clock signal synchronous.

Master clock 301 passes through time-delay calculation module 302, side-play amount computing module 303 and state transformation device 304 and links to each other from clock 305 successively; Wherein, provide local clock signal by holding wire for time-delay calculation module 302 from the output signal of clock 305, the signal of side-play amount computing module 303 outputs feeds back to time-delay calculation module 302 by holding wire.

The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.

Claims (14)

1. the method for principal and subordinate's clock synchronization is characterized in that, this method comprises:

A, from the time clockwise master clock initiate the exchange of synchronised clock sync message, and write down each time value of this process of transmitting;

B, utilize each time value of described record to calculate the time delay value of this synchronizing process;

C, in same synchronizing cycle, repeat repeatedly the process of step a～step b, obtain a plurality of time delay values, and utilize described a plurality of time delay value to obtain the optimum delay value, and try to achieve the Best Times side-play amount;

D, select corresponding weights for use, in conjunction with described Best Times side-play amount and from the current time value of clock, to calibrating from clock according to the Best Times side-play amount.

2. method according to claim 1 is characterized in that, described each time value of step a is respectively from the time T s of clock tranmitting data register synchronization request message ₁, master clock receives the time T m of synchronization request message ₁, master clock sends the time T m of sync response message ₁', receive the time T s of sync response message from clock ₁'.

3. method according to claim 2 is characterized in that, the time delay value of described this synchronizing process of calculating is with described each time value Ts ₁, Tm ₁, Tm ₁' and Ts ₁', the substitution formula:

${\mathrm{Delay}}_1=\frac{[({\mathrm{Ts}}_1-{\mathrm{Tm}}_1)+({\mathrm{Tm}}_1^{\&prime;}-{\mathrm{Ts}}_1^{\&prime;})]}{2},$ Calculate gained;

Wherein, Delay ₁Time delay value for this synchronizing process.

4. method according to claim 1 is characterized in that, the described a plurality of time delay values of step c are the exchanges through k clock synchronization message, obtain k time delay value.

5. method according to claim 4 is characterized in that, the process of utilizing described a plurality of time delay value to obtain the optimum delay value is:

A more described k time delay value removes a maximum and a minimum value, then with remaining k-2 value substitution formula:

$\stackrel{\&OverBar;}{\mathrm{Delay}}=\frac{1}{k-2}\underset{i=1}{\overset{k-2}{\mathrm{\&Sigma;}}}{\mathrm{Delay}}_i=\frac{1}{k-2}\underset{i=1}{\overset{k-2}{\mathrm{\&Sigma;}}}\frac{[({\mathrm{Ts}}_i-{\mathrm{Tm}}_i)+({\mathrm{Tm}}_i^{\&prime;}-{\mathrm{Ts}}_i^{\&prime;})]}{2}$ By calculating;

Wherein,

Be the optimum delay value of this synchronizing process, the span of k is 2 times at least,

Ts ₁Be the time from clock tranmitting data register synchronization request message, Tm ₁For master clock receives time of synchronization request message, Tm ₁' send time of sync response message, Ts for master clock ₁' for receive the time of sync response message from clock.

6. method according to claim 5 is characterized in that, the described process of asking the Best Times side-play amount is the optimum delay value with this synchronizing cycle The substitution formula:

$\stackrel{\&OverBar;}{\mathrm{Offset}}={\mathrm{Tm}}_i+\stackrel{\&OverBar;}{\mathrm{Delay}}-{\mathrm{Ts}}_i,$ By calculating gained;

Wherein, Best Times side-play amount for this synchronizing cycle;

Tm _iAnd Ts _iBe respectively when i is subsynchronous in this synchronizing cycle, master clock is at the time point of bottom record with from the time value of clock at the time point of bottom record.

7. method according to claim 1, it is characterized in that the described process of corresponding weights of selecting for use is: when the absolute value of Best Times side-play amount during greater than preset threshold, weights are 1～2 value, the big more then weights of the absolute value of Best Times side-play amount are more little, but all the time greater than 1; When the absolute value of Best Times side-play amount during less than preset threshold, weights are 0～1 value, and the big more then weights of the absolute value of Best Times side-play amount are big more, but all the time less than 1.

8. method according to claim 6 is characterized in that, and is described to carrying out calibration process from clock: as to be according to formula:

${\mathrm{Ts}}^{\mathrm{\&Delta;}}={\mathrm{Ts}}^{\mathrm{\&Gamma;}}+P*\stackrel{\&OverBar;}{\mathrm{Offset}};$

Calculate gained; Wherein, Ts ^ΓFor in this synchronizing cycle from the clock current system time; Ts ^ΔFor in this synchronizing cycle from clock through the calibration after system time; P is selected weights in this synchronizing cycle.

9. method according to claim 6 is characterized in that, described the i time, is meant described k-2 calculation delay value Delay in this synchronizing cycle _iProcess in, time delay value that is calculated and optimum delay value

Compare that time of difference minimum.

10. method according to claim 1 is characterized in that, further comprises after the described steps d:

E, adjust synchronization times k ' and the synchronization of time intenals T ' of next synchronizing cycle according to the Best Times side-play amount, and by calculating the optimum delay value of described next synchronizing cycle;

F, return step a, carry out principal and subordinate's clock adjustment process of described next synchronizing cycle, until the Best Times side-play amount be zero or synchronization times reach maximum.

11. method according to claim 10, it is characterized in that, described synchronization times and the synchronization of time intenals value of adjusting next synchronizing cycle, be that the Best Times side-play amount of a current Best Times side-play amount and a last synchronizing cycle is divided by, obtain a ratio, (k T) is worth conduct synchronization times k ', the synchronization of time intenals value T ' of next synchronizing cycle to selection is preset according to described ratio size one group; Wherein, k is a synchronization times, and T is the synchronization of time intenals value.

12., it is characterized in that the process of described optimum delay value by calculating next synchronizing cycle is according to claim 10 or 11 described methods:

If k ' 〉=k, in then next synchronizing cycle according to sync interval T ' carry out (k '-k+1) inferior clock synchronization message switching, obtain (k '-k+1) individual new time delay value, abandon first time delay value of previous synchronizing cycle of gained then, and (k-1) the individual time delay value that will be left and described (k '-k+1) individual time delay value is formed the new individual time delay value of k ', utilize median average filter algorithm at last, obtain the average delay value, as the optimum delay value of a back synchronizing cycle; Wherein, k is the synchronization times of this synchronizing cycle;

If k '＜k, carry out the clock synchronization message switching again 1 time according to sync interval T ' in then next synchronizing cycle, that counts last synchronizing cycle in obtains k, obtain (k+1) individual time delay value altogether, abandon (k-k '+1) inferior time delay value of last synchronizing cycle, the remaining individual time delay value of k ' is carried out the median average filter again calculate, obtain the optimum delay value of average delay value as next synchronizing cycle; Wherein, k is the synchronization times of this synchronizing cycle.

13. the device of principal and subordinate's clock synchronization is characterized in that, this device comprises master clock, time-delay calculation module, and side-play amount computing module, state transformation device reach from clock; Wherein,

Master clock is used to described principal and subordinate's clock synchronization calibrating installation that standard clock signal is provided;

The time-delay calculation module, be used for according to from the time clockwise master clock sent the clock synchronization message time Time Calculation optimum delay value of gathering;

The side-play amount computing module is used for according to described optimum delay value calculating optimum time offset;

The state transformation device is used for selecting suitable weights according to the size of described Best Times side-play amount; And

From clock, be used for calibrating in conjunction with self current system time according to described Best Times side-play amount and corresponding weights, and the system time after will calibrating is as local clock, for the time-delay calculation module and other equipment provides and master clock keeps clock signal synchronous.

14. device according to claim 13 is characterized in that, described time-delay calculation module also is used for the synchronization times of next synchronizing cycle and the adjustment of synchronization of time intenals value.

Images