CN101217252A - A soft start circuit for PDM DC-DC switching power supply - Google Patents
A soft start circuit for PDM DC-DC switching power supply Download PDFInfo
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- CN101217252A CN101217252A CNA2008100466222A CN200810046622A CN101217252A CN 101217252 A CN101217252 A CN 101217252A CN A2008100466222 A CNA2008100466222 A CN A2008100466222A CN 200810046622 A CN200810046622 A CN 200810046622A CN 101217252 A CN101217252 A CN 101217252A
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Abstract
The invention discloses a soft starting circuit for a pulse width modulation DC-DC switch power, comprising a frequency splitting count module, a current threshold module, a current sampling module, a current limiting comparator, a two input or-gate, an oscillator and an RS trigger. The current in a power inductance is sampled when an external switch rectifier is conducted, and the current changes from small to big by stage by limiting the peak value of the current so as to control the step change of the duty ratio, thus leading the output voltage to increase by stage gradually, avoiding surge current in starting procedure and realizing the soft starting function. The invention has the advantages of integrating to the inside of large scale integrated circuit without high capacitance in the outside or a microcontroller to control, limiting the load current directly with good soft starting effect and being suitable for a voltage control mode and a current control mode; the circuit is simple correspondingly by adopting a current gating network; the soft starting time can be regulated automatically according to different loads.
Description
Technical field
The invention belongs to the ic core chip technology, be specifically related to a kind of soft starting circuit of pulse-width modulation DC-DC Switching Power Supply.
Background technology
The DC-DC Switching Power Supply is in start-up course, because input voltage rises to maximum from minimum value, the duty ratio of the pwm control signal of switching tube begins to change from maximum, diminishes gradually.Owing to there is electric capacity to exist in the circuit, to electric capacity generation surge current easy to charge, this moment, the electric current by switching tube can reach very big, damaged Circuits System easily.For fear of this situation, need in switching power source chip, add soft starting circuit.
The soft starting circuit needed value that is the duty ratio that is used for controlling pwm pulse waveform in the power input voltage uphill process when minimum value progressively changes to operate as normal, thus control output voltage progressively changes.Because duty ratio is to begin progressively to change from minimum value, can not make the conducting always of switching tube long period, has avoided the generation of surge current.Mainly contain following a few class in the soft start circuit of switch power supply of using at present: a class is to adopt electric capacity and resistance, and the characteristic that voltage index rises when utilizing the electric capacity charging is controlled the voltage uphill process.This soft starting circuit need add the constant-current source and the external capacitive of charging, and the capacitance that needs is bigger, generally needs tens nF to a few μ F, and so big electric capacity is not easy to be integrated into large scale integrated chip inside.Another kind of is to adopt microcontroller to control the pure digi-tal control of start-up course.Though this soft starting circuit can be integrated into chip internal, owing to being microprocessor controls that need be other and need before power circuit partly powers on, just starting working.For general purpose Switching Power Supply, too complicated, cost is high too.
United States Patent (USP) U.S.6 has described the novel soft starting circuit that a kind of output voltage rises stage by stage among 337,480 B1.This soft starting circuit does not use external capacitive and microcontroller, is made up of several sections such as oscillator, digital control, PWM comparator, resistor networks.PWM comparator negative terminal connects oscillator output, the partial pressure value of positive terminating resistor network.The PWM comparator is by the partial pressure value of comparison resistance and the triangular signal of oscillator output, the conducting that produces PWM pulse-width control signal power controlling switching tube.Digital counting partly sample oscillator triangular signal and the counting, counting reaches set point just changes resistor network by control switch partial pressure value, make dividing potential drop rise, thereby duty ratio is risen stage by stage by minimum, realize soft start function since 0 by ladder.But sort circuit has remedied the shortcoming of preceding two kinds of circuit has also brought new deficiency.The first, the control of sort circuit sampled voltage only is suitable for voltage mode control, is not suitable for current control mode.The second, because what adopt is resistance pressure-dividing network, when needs suitably increased the soft start ascent stage and reach better soft start effect, circuit was too complicated.The 3rd, soft-start time can not be regulated according to different load currents automatically by digital counting part and output voltage decision.
Summary of the invention
The object of the present invention is to provide a kind of soft starting circuit of pulse-width modulation DC-DC Switching Power Supply, this soft starting circuit goes for voltage mode control and current control mode, and circuit is simple relatively, and soft-start time can be regulated automatically according to different loads.
To achieve these goals, the soft starting circuit of pulse-width modulation DC-DC Switching Power Supply provided by the invention comprises the frequency division counter module, current threshold module, current sample module, current limliting comparator, two inputs or door, oscillator, rest-set flip-flop;
Rest-set flip-flop
Output connects the grid level of external switch rectifying tube, the conducting of control switch rectifying tube and shutoff, the output of the S termination oscillator of rest-set flip-flop, the output of two inputs of R termination or door; Two inputs of two inputs or door are received in the output of the pulse-width signal of switching power circuit and current limliting comparator; The input anode of current limliting comparator and negative terminal connect the output of current threshold module and the output of current sample module respectively;
The input of frequency division counter module connects the gate drive signal of reset signal, asserts signal and switching and rectifying pipe respectively, produce first to the 3rd code signal by frequency division and coding, link to each other with three inputs of current threshold module respectively the gate drive signal of switch rectifying tube; One termination power voltage of switching and rectifying pipe, the grid of the other end and switching and rectifying pipe connect two inputs of current sample module.
Soft starting circuit of the present invention does not need externally to add big electric capacity, does not need to use microprocessor controls, can be integrated into large scale integrated circuit inside; Direct restriction load current softly opens effectively, and goes for voltage mode control and current control mode; Adopt the electric current gating network, circuit is simple relatively; Soft-start time can be regulated automatically according to different loads.Particularly, the present invention has following technical characterstic:
(1) during pulse-width modulation DC-DC Switching Power Supply of the present invention, the electric current on the sampled power inductance during conducting of switching and rectifying pipe externally, by limiting the ascending stage by stage variation of its peak current, control the duty ratio notch cuttype and change, output voltage is slowly risen stage by stage.Because this circuit is the peak current of restriction external inductors, has directly avoided the surge current in the start-up course, soft start is effective.
(2) current threshold that provides of electric current on the external inductors that relatively samples of current limliting comparator and current threshold module, and just in the soft duty ratio that opens in the process with the common control switching circuit of oscillator, and after soft start finishes, the current limliting comparator just plays the effect of restriction maximum output current, do not participate in the duty ratio of control switching circuit, therefore function opposite independent can be used for voltage mode control, can be used for current control mode again.
(3) the present invention passes through the grid level drive signal frequency division counter of frequency division counter module to outside switching and rectifying pipe, and fractional frequency signal is encoded, and outputs in the current threshold module, and the different current branch of gating changes current threshold.The frequency division counter module is relative with the design of electric current gating network flexible, can change soft opening the number of stages of rising and the time in each stage by simply restructuring.
(4) effect of the set end of frequency division counter module is after detecting switch power source output voltage and rising to the required voltage value, by the value that changes output encoder current threshold is made as the highlyest, and soft start finishes, and circuit enters normal mode of operation.Soft-start time is relevant with frequency division counter module, output voltage and load current.For example under light load condition, because the output load current under the normal operation is very little, soft start perhaps only need be gone through one or two the stage, the required voltage value when output voltage just reaches the circuit operate as normal, thus enter normal mode of operation.
Description of drawings
Fig. 1 is the structural representation of soft starting circuit of the present invention;
Fig. 2 is applied to structural representation in the Switching Power Supply Buck structure for soft starting circuit of the present invention;
Fig. 3 is the variation schematic diagram of soft starting circuit of the present invention current threshold in soft start-up process;
Fig. 4 is a kind of structural representation of frequency division counter module 4 among Fig. 1;
Fig. 5 is a kind of structural representation of current threshold module 3 among Fig. 1;
Fig. 6 is a kind of structural representation of current sample module 2 among Fig. 1;
Fig. 7 is the sequential chart of key control signal in the soft start-up process;
Fig. 8 is the oscillogram of Switching Power Supply output VOUT in soft start-up process.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing and example.
As shown in Figure 1, soft starting circuit 30 provided by the invention comprises following components: frequency division counter module 4, current threshold module 3, current sample module 2,1, two input of current limliting comparator or door 5, oscillator 7, rest-set flip-flop 6.
Adopting power tube PMOS 8 with outside switching and rectifying pipe below is that example illustrates concrete structure of the present invention.
Rest-set flip-flop 6
Output connects the grid level of external switch rectifying tube power tube PMOS 8, the conducting and the shutoff of power controlling PMOS pipe 8, thereby the duty ratio of control switching circuit.The output of the S termination oscillator 7 of rest-set flip-flop 6, the output of two inputs of R termination or door 5; Two inputs of two inputs or door 5 are received in the pulse-width signal VPWM of switching power circuit and the output of current limliting comparator 1; The positive input terminal of current limliting comparator 1 and negative input end meet the output V1 of current threshold module 3 and the output V2 of current sample module 2 respectively; Frequency division counter module 4 is controlled by the grid level drive signal VP of outside reset signal RST, asserts signal LD and power tube PMOS 8, produce three code signal D0, D1, D2 by frequency division and coding, link to each other with three inputs of current threshold module 3 respectively the grid level drive signal VP of power tube PMOS 8; Current sample module 2 is controlled by the grid level drive signal VP of power tube PMOS 8, and the magnitude of voltage at the drain electrode SW place of sampled power PMOS pipe 8 is actually the conducting current value on the power tube PMOS 8 of having sampled when power tube PMOS 8 conductings.In soft starting circuit, reset signal RST is the output of under-voltage protection module in the switching power circuit, and as the output voltage VO UT that samples switching power circuit during greater than the needed output voltage of its operate as normal, asserts signal LD is by " 0 " jumping " 1 ".
Fig. 2 is applied to structural representation in the Switching Power Supply Buck structure for soft starting circuit of the present invention.External switch rectifying tube power tube PMOS 8, inductance L 0, capacitor C 0, afterflow diode D0 constitutes Switching Power Supply Buck structure.The output of switching power circuit is VOUT, and load is ROUT.
Reset signal RST is controlling the beginning of soft start.After the chip power, the output signal RST of under-voltage protection module triggers soft start and starts working, and at this moment oscillator 7 has been started working; produce pulse signal; open power tube PMOS 8 by rest-set flip-flop 6, the bias voltage of afterflow diode D0 is anti-inclined to one side, so not conducting of D0.Electric current begins to rise on the power tube PMOS 8 at this moment, current sample module 2 is also opened simultaneously, current value on the sampling external inductors L0 also raises gradually, when current value rises to the current threshold that current threshold module 3 sets, current limliting comparator 1 output hopping is high level and the R end of having received rest-set flip-flop 6 by two inputs or door 5, output signal VP is a high level, switch-off power PMOS pipe 8, current value on the external inductors L0 reduces, and current sample module 2 is controlled by signal VP at this moment, the electric current on the current power of the not sampling PMOS pipe 8.When next oscillator output pulse arrived, the output VP of rest-set flip-flop 6 jumped again and is low level, and power tube PMOS 8 is opened once more, carries out the control of next cycle.The current threshold that current threshold module 3 provides is controlled by branch frequency counting circuit 4, and current threshold rises stage by stage.Like this, soft starting circuit well limits the peak current on the external inductors L0, thereby has limited surge current, and the output VOUT of Switching Power Supply is slowly risen stage by stage, reaches the effect of soft start.
As shown in Figure 3, when circuit end under-voltage protection state, soft starting circuit is started working, and frequency division counter module 4 is provided with current threshold size 2*I0 and the time tsoft1 of phase I.In this stage, dark linear zone is opened and be operated in to power tube PMOS 8, and this moment, 8 equivalences of PMOS pipe were linear zone resistance and resistance R
ONIn ambient temperature one regularly is definite constant.The magnitude of voltage at current sample module 2 sampling SW places, corresponding and external inductors L0 goes up current value, its output V2 links to each other with the negative input end of current limliting comparator 1, the positive input terminal of current limliting comparator 1 links to each other with the output V1 of current threshold module 3, and the magnitude of voltage at output V1 place is set by frequency division counter module 4.In time, the peak current on the external inductors L0 can not surpass the current threshold that frequency division counter module 4 sets for current threshold module 3 at tsoff1, and the duty ratio of the gate drive signal VP of power tube PMOS 8 also can be limited to a smaller value.When arriving tsoft2, it is 4*I0 that frequency division counter module 4 changes current threshold, peak current on the external inductors L0 can rise to higher numerical value, and according to the course of work of phase I, the duty ratio of the gate drive signal VP of power tube PMOS 8 also rises to a higher numerical value.Like this, the ascending variation of duty ratio of power tube PMOS 8 gate drive signal VP, control output voltage VOUT rises stage by stage, till output voltage values reaches the required magnitude of voltage of switching power circuit operate as normal.
Illustrate a kind of specific implementation circuit of frequency division counter module 4, current sample module 2 and current threshold module 3 below.
As shown in Figure 4, frequency division counter module 4 comprises: frequency divider 51, encoder 52, two input nand gates 48,49; Frequency divider 51 is made of n d type flip flop, and n is determined by the soft-start time of designed circuit, and 8≤n≤12 are that example illustrates its structure below with n=10.
The reset signal of 10 d type flip flops meets RST, and clock signal clk connects the clock end of first order d type flip flop, d type flip flop
The input D end of output termination self, and the clock end of access next stage d type flip flop, these 10 d type flip flops are concatenated into frequency divider 51 by this connection, and output signal Q8, the Q9 of d type flip flop 38,39 is respectively 512 frequency divisions and 1024 frequency divisions of clock signal clk.Fractional frequency signal Q8, Q9 are input to the gate drive signal VP of the output signal of two input nand gates, 48, two input nand gates 48 and external power PMOS pipe 8 through two input nand gates, 49 clock signal CLK.Encoder 52 is by two input NOR gate 40,41,45, and not gate 42,43,46,47 and two input nand gates 44 constitute.The output signal Q8 of d type flip flop 38 and asserts signal LD are input to two input NOR gate 40 and pass through not gate 42 output signal L80 again, the output signal Q9 of d type flip flop 39 and asserts signal LD are input to two input NOR gate 41--again through second not gate, 43 output signal L60, the output signal L80 of not gate 42 delivers to output D1, the output signal L80 of the output signal L60 of not gate 43 and not gate 42 is input to two input nand gates 44 and delivers to output D0 through not gate 46 again, and the output signal L80 of the output signal L60 of not gate 43 and not gate 42 is input to two input NOR gate 45 and delivers to output D2 through not gate 47 again.When asserts signal LD is " 0 ", encoding D 0D1D2 in the change procedure of fractional frequency signal Q8, Q9 successively according to 000,001,011,111 changes, and when asserts signal LD is " 1 ", it is 111 that encoding D 0D1D2 jumps, and no longer is subjected to the influence of fractional frequency signal Q8, Q9.Open in the process soft, when fractional frequency signal Q8, Q9 do not jump to " 1 " simultaneously, the grid control signal VP of clock signal clk sampled power PMOS pipe 8, when fractional frequency signal Q8, Q9 jump to " 1 " simultaneously, the clock signal clk perseverance is " 1 ", has shielded the grid control signal VP of power tube PMOS 8, and encoding D 0D1D2 is jumped is 111, the highest selected current threshold, soft start finishes.Asserts signal LD is set after detecting switch power source output voltage VOUT to rise to the required voltage value, when connecing underload, soft start-up process does not need just can make output voltage VO UT rise to specified magnitude of voltage by four-stage, only needs still less two or three phases just to finish soft start.
As shown in Figure 5, the structure of current threshold module 3 is: PMOS pipe MN1, MN2, MN3, MN4, MN6, MN8, MN9, constant-current source I0 and resistance R 1 constitute current-mirror structure.Output V1 is the drain electrode of PMOS pipe MN2.PMOS pipe MN5 connects with PMOS pipe MN6, and PMOS pipe MN7 connects with PMOS pipe MN8, and PMOS pipe MN9 connects with PMOS pipe MN10, all is connected between output V1 and the ground.D0 connects the turn-on and turn-off of the grid control PMOS pipe MN6 place current branch of PMOS pipe MN5, D1 connects the turn-on and turn-off of the grid control PMOS pipe MN8 place current branch of PMOS pipe MN7, and D2 connects the turn-on and turn-off of the grid control PMOS pipe MN10 place current branch of PMOS pipe MN9.
In soft start-up process, the variation of encoding D 0D1D2 is the conducting successively of Control current branch road respectively, thus the electric current I on the branch road of controlling resistance R1 place
R1Variation.The breadth length ratio that might as well establish MN4, MN6, MN8 and MN10 is respectively 2 times of MN3 breadth length ratio, 8 times, 4 times and 2 times, and when encoding D 0D1D2 changed by 000,001,011,111, the electric current that flows through resistance R became 2I successively so
0, 4I
0, 8I
0, 16I
0, the voltage that then outputs to current limliting comparator 1 anode is:
V1＝VIN-I
R1*R1
As shown in Figure 6, the structure of current sample module 2 is: current sample props up route resistance R 10 and PMOS pipe MP12 polyphone constitutes, and the leakage level of MP12 pipe meets output V2.The MN19 that the MP11 that diode connects receives between the source class of supply voltage VIN and MP12, diode connects receives between the source class and ground of MP12, plays the effect of protective circuit.Control signal VP links MP12, the grid of MP13, and link the grid of MP14 by the 5th not gate 16.MP13 and MP14 polyphone back and capacitor C 12 parallel connections are connected between supply voltage VIN and the output V2 capacitor C 11 and MP13 parallel connection.When control signal VP is low level, i.e. during power tube PMOS 8 conductings, MP12 and MP13 conducting, MP14 turn-offs, and sampling is by the electric current I on the power tube PMOS 8
L, output V2, and on capacitor C 12, stored electric charge.External power PMOS pipe is operated in dark linear zone, and equivalence is the linear zone resistance R
ON, ignore the pressure drop that is operated on the sampling branch road on the saturation region pipe MP12, the voltage that outputs to current limliting comparator 1 negative terminal that obtains is:
V2＝VIN-I
L*(R
ON+R10)
Make V1=V2 so:
Promptly ought sample the electric current I on the external power PMOS pipe 8
LGreater than setting current threshold I
L0The time, the output of current limliting comparator 1 is by " 0 " jumping " 1 ".
During chip power, current limliting comparator 1 output initial value is " 0 ", and the output of oscillator 7 makes control signal VP jump " 0 ", and power tube PMOS 8 is opened the electric current I on the external inductors L0
LRise, sampling V2 value reduces, and works as I
LValue rises when surpassing preset threshold, and " 1 " is jumped in 1 output of current limliting comparator, makes control signal VP jump " 1 ", closes power tube PMOS 8, the control switching duty ratio.
When control signal VP jumps to behind the high level, MP12 and MP13 turn-off, the MP14 conducting, and V2 is the electric current I on the sampled power PMOS pipe 8 not
L, supply voltage VIN makes the output rebound of current limliting comparator 1 be " 0 " by the value that C11 draws high output V2.When will arriving at the rising edge of oscillator 7, power tube PMOS 8 opens once more, repeat above process rises to next stage up to current threshold current value, soft start also enters into next stage, needed magnitude of voltage when the output voltage VO UT of switching power circuit rises to operate as normal.
Fig. 7 is the sequential chart of key control signal in the soft start-up process.Fractional frequency signal Q8, Q9 are respectively 512 frequency divisions and 1024 frequency divisions of the grid level drive signal VP of power tube PMOS 8, and D0, D1, D2 then obtain by fractional frequency signal Q8, Q9 are encoded.
Fig. 8 is the oscillogram of the output VOUT of switching power circuit in soft start-up process.Can see that VOUT slowly rises stage by stage, has well limited surge current.
Though the present invention is illustrated as illustration through specific embodiment, should be clear and definite be that the present invention is not limited to embodiment disclosed herein, can not be considered to the restriction to claim of the present invention.If other staff should belong to the scope that claim of the present invention is protected according to change or improvement that the present invention has made unsubstantiality.
Claims (4)
1. the soft starting circuit of a pulse-width modulation DC-DC Switching Power Supply, it is characterized in that: this circuit comprises frequency division counter module (4), current threshold module (3), current sample module (2), current limliting comparator (1), two inputs or door (5), oscillator (7), rest-set flip-flop (6);
Rest-set flip-flop (6)
Output connects the grid level of external switch rectifying tube, the conducting of control switch rectifying tube and shutoff, the output of the S termination oscillator (7) of rest-set flip-flop (6), the output of two inputs of R termination or door (5); Two inputs of two inputs or door (5) are received in the output of the pulse-width signal of switching power circuit and current limliting comparator (1); The input anode of current limliting comparator (1) and negative terminal connect the output (V1) of current threshold module (3) and the output (V2) of current sample module (2) respectively;
The input of frequency division counter module (4) connect respectively reset signal (RST), asserts signal (LD) and switching and rectifying pipe gate drive signal (VP), produce first to the 3rd code signal (D0, D1, D2) by frequency division and coding, link to each other with three inputs of current threshold module (3) respectively the gate drive signal (VP) of switch rectifying tube; One termination power voltage of switching and rectifying pipe, the grid of the other end (SW) and switching and rectifying pipe connect two inputs of current sample module (2).
2. soft starting circuit according to claim 1 is characterized in that: frequency division counter module (4) comprises frequency divider (51), first, second two input nand gate (48,49) and encoder (52);
Frequency divider (51) is made of n d type flip flop, 8≤n≤12, the zero clearing termination reset signal (RST) of each d type flip flop, the clock signal (CLK) of clock termination the two or two input nand gate (49) output of first order d type flip flop, each d type flip flop
The input D end of output termination self, and the clock end of access next stage d type flip flop, each d type flip flop constitutes frequency divider (51) by this connection serial connection, and (Q8 Q9) is 2 of clock signal (CLK) respectively to the output signal of n-1 level and n level d type flip flop
N-1Frequency division and 2
nFrequency division;
The output signal of n-1 level and n level d type flip flop (Q8, Q9) connect two inputs of the one or two input nand gate (48), the gate drive signal (VP) of the output signal of the one or two input nand gate (48) and switching and rectifying pipe is input in the two or two input nand gate (49), clock signal (CLK); Encoder (52) comprises first to the 3rd NOR gate (40,41,45), first to fourth not gate (42,43,46,47), and NAND gate (44);
2 of the clock signal (CLK) that an output (Q8) of asserts signal (LD) and frequency divider (51) is provided
N-1Fractional frequency signal is input to first NOR gate (40) jointly, again through first not gate (42) output signal (L80),
2 of the clock signal (CLK) that another output Q9 of asserts signal (LD) and frequency divider (51) provides
nFractional frequency signal is successively by second NOR gate (41) and second not gate (43) output signal (L60);
Above-mentioned two output signals (L60, L80) through NAND gate (44) again through the output of the 3rd not gate (46) as first code signal (D0);
The output of first not gate (42) output signal (L80) is as second code signal (D1);
Above-mentioned two output signals (L60, L80) through the 3rd NOR gate (45) again through the output of the 4th not gate (47) as the 3rd code signal (D2).
3. soft starting circuit according to claim 1 and 2 is characterized in that: the structure of current threshold module (3) is:
PMOS pipe MN1, MN2, MN3, MN4, MN6, MN8, MN9, constant-current source I0 and resistance R 1 constitute current-mirror structure;
PMOS pipe MN5 connects with PMOS pipe MN6, and PMOS pipe MN7 connects with PMOS pipe MN8, and PMOS pipe MN9 connects with PMOS pipe MN10, all is connected between the output (V1) and ground of current threshold module (3);
First code signal (D0) connects the turn-on and turn-off of the grid control PMOS pipe MN6 place current branch of PMOS pipe MN5, the second code signal D1 connects the turn-on and turn-off of the grid control PMOS pipe MN8 place current branch of PMOS pipe MN7, and the 3rd code signal D2 connects the turn-on and turn-off of the grid control PMOS pipe MN10 place current branch of PMOS pipe MN9.
4. soft starting circuit according to claim 1 and 2 is characterized in that: the structure of current sample module (2) is:
Resistance R 10 and PMOS pipe MP12 series connection, the leakage level of PMOS pipe MP12 connects the output (V2) of current sample module (2);
PMOS pipe MP11 is diode with MP19 and is connected, and PMOS pipe MP11 receives between the source class of supply voltage VIN and MP12, and PMOS pipe MN19 receives between the source class and ground of PMOS pipe MP12;
PMOS manages MP12, and the grid of MP13 connects the gate drive signal (VP) of switching and rectifying pipe, and links the grid of PMOS pipe MP14 by the 5th not gate (16);
PMOS pipe MP13 and MP14 polyphone back and capacitor C 12 parallel connections are connected between the output (V2) of supply voltage (VIN) and current sample module (2), capacitor C 11 and PMOS pipe MP13 parallel connection.
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2008
- 2008-01-04 CN CN2008100466222A patent/CN101217252B/en not_active Expired - Fee Related
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