CN101201731B - Binary digit subtracter - Google Patents
Binary digit subtracter Download PDFInfo
- Publication number
- CN101201731B CN101201731B CN2007101939252A CN200710193925A CN101201731B CN 101201731 B CN101201731 B CN 101201731B CN 2007101939252 A CN2007101939252 A CN 2007101939252A CN 200710193925 A CN200710193925 A CN 200710193925A CN 101201731 B CN101201731 B CN 101201731B
- Authority
- CN
- China
- Prior art keywords
- power
- borrow
- result
- binary
- subtracter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a binary digital subtracter and is mainly used for implementing the subtraction between two binary numbers with multiple bits in the field of digital arithmetic and computation. The invention synchronously decides either corresponding weight bits generate borrow or transmit borrow according to the feature of the two subtracted binary numbers, and the potential borrow is transmitted quickly from low bits to high bits along a corresponding transmission channel. When the subtraction between the two numbers in the same weight bit is implemented, OR gate or XOR gate are used for generating two opposite intermediate results, and under the control of the potential borrow in lower weight bits, the intermediate results are output as final results optionally. MOS tubes are used for designing a circuit of borrow generation and transmission as well as a result selection circuit in the circuit, thus leading the borrow channel to be taken as a conducting wire and simplifyingresult computation. The binary digital subtracter is characterized by simple structure, low hardware cost, fast running speed and convenience for extending operated bits, etc.
Description
Technical field:
The invention belongs to the Digital Electronic Technique field, the subtraction that is mainly used in digital algorithm calculations field is realized, is to finish the subtraction circuit that two binary numbers subtract each other.
Background technology:
At present, in the research and application of binary digit subtraction circuit, mainly can reduce three classes: the first kind is the subtracter that adopts gunn effect device to implement.This subtracter comes across the seventies in last century, utilizes gunn effect device to realize the generation and the transmission of difference and borrow.This subtracter has certain calculation speed.But, because gunn effect device has specific volume, and be nonlinear material, can advise, thereby there is trueness error in this subtracter into simulation device, volume is big, can not adopt silicon chip integrated, is not suitable for modernized ULSI manufacture craft.So far, few people adopt this device to carry out subtracter research more.
Second class is based on the subtraction circuit that adder structure adopts the two's complement scheme.This subtraction circuit is counted if subtract each other or negative for input, can adopt negate to add 1, again through the adding circuit addition, just can obtain subtraction result.Clearly, because the negate when making subtrahend, cause subtraction circuit to Duo the time-delay of one-level door virtually than adding circuit.Both just like this, in existing adder designs, also exist a lot of not enough.Because subtraction can realize by the adding circuit of this modification.Therefore, in existing research, people mainly put into energy in the research of adding circuit, and typical high-speed adder has: carry lookahead adder, and carry saltus step totalizer, carry is selected totalizer, and conditional-sum adder etc.Differentiation through top various totalizers, a lot of totalizer variants have appearred again, as: by Brent and Kung at A regular layout for parallel adders.IEEETrans.comput.1982, vol c-301, the binary lookahead adder that proposes among the pp.260-264; At High-speed binary adder.IBM.J.Res.Develop.1981, vol.25 has proposed the distortion add with carry musical instruments used in a Buddhist or Taoist mass of a formulism among the pp.156-166 by Lmg; By Brinivas and Parhi at A fast VLSIadder architecture.IEEE Journal solid-state circuits.1992, Vol.27, No.5, propose redundant symbol among the pp.761-767 and counted adding circuit, also have and occur the more various hybrid digital totalizers and the digital adder of dissimilar project organizations now in the international conference collection of thesis and in the periodical.As adopt the totalizer of Manchester carry chain, and adopt the totalizer of self synchronization circuit, adopt the totalizer of differential cascade switching voltage logic, and adopt the totalizer of selecting circuit etc.In addition, can't find when breaking through from theoretical analysis, computational algorithm and project organization people, some researchists begin from design technology, wish to find new discovery.So employing ECL technology has appearred in succession, static CMOS technology, and dynamic CMOS technology reaches the totalizer with making such as BiCMOS technologies.All these have been seen in the totalizer of document, are invariably or manage how to reduce that carry generates and the time-delay of carry transmission, or be generation and the transmission of managing to avoid carry.But net result can not allow the people satisfied fully.Along with the increase of number of bits, or hardware requirement presses index law and rises, or the time-delay expense press the index law rising, be difficult to reach a kind of equilibrium of satisfaction between the two, and circuit power consumption is bigger.
The 3rd class is for adopting the direct subtraction design based on the subtraction rule of integrated circuit.It is different from top two class subtractions design.At first it is to adopt the integrated electronic original paper, and secondly it is that utilization subtraction rule is carried out theoretical analysis and algorithm instructs, and it is the subtraction circuit design of adopting the substantivity that does not contain the adding circuit vestige at last.Consider that addition also can adopt subtracter to realize, and division circuit is if adopt the 3rd class subtraction circuit to realize improving travelling speed greatly.So more existing now researchists further investigate the 3rd class subtraction circuit.As: Y.G.Chen and J.B.Kuo are at A 1.5V BiCMOS dynamic subtracter Circuit for low-voltage BiCMOSCPU VLSI.Circuits and Systems, 1994.Proceedings of the 37th MidwestSymposium on.1944, the chain type subtraction circuit that proposes among the vol.2.pp.1149-1151; C.Senthilpari and K.Diwakar etc. have proposed to adopt the chain type subtracter of complementary transmission logic at Power deduction in digital signal processing circuit usinginventive CPL subtracter circuit.Semiconductor Electronics 2006 IEEEinternational Conference on.2006 in pp.820～824.In all visible domestic and foreign literatures, all more shallow about the design of the 3rd class subtracter.These subtracters also be otherwise hardware cost too high, power consumption is bigger, or it is excessive to delay time, promptly travelling speed is slower, can't provide gratifying scheme.
Summary of the invention:
Consider the problem that above-mentioned three types of achievements in research exist, proposed the present invention.Target of the present invention is to propose a kind of two digital subtractors that the multidigit binary number subtracts each other, it is the built-up circuit that subtracts each other about two multidigit binary numbers, form by computing circuit at each power and position, this subtracter subtracts each other the binary number characteristics according to coordination, having designed borrow produces and transmission selection circuit, again according to the character of metal-oxide-semiconductor, implemented each unit of the present invention, described binary digit subtracter, be the realization circuit that subtracts each other about two multidigit binary numbers, form by computing circuit at each power and position.The computing circuit of all power and positions all is identical, all be by a data computing and signature analysis circuit unit, a net result arithmetic element, and a borrow produces and transmission selected cell composition, data operation and signature analysis circuit unit are by an XOR gate, same or a door and a rejection gate composition.XOR gate is used to produce the intermediate result of subtracting each other of this power and position binary number.Same or Men Ze is used to produce the radix-minus-one complement of intermediate result, and produces and transmit the borrow transmission of control signals of selected cell as borrow.The output of rejection gate is then as when the borrow generation of this power and position minuend during less than subtrahend and the borrow generation control signal of transmission unit, the net result arithmetic element is by a NMOS pipe and the selection circuit that the PMOS pipe constitutes, wherein the source electrode of the drain electrode of NMOS pipe and PMOS pipe is imported the intermediate operations result from data operation and signature analysis circuit unit respectively, the drain electrode short circuit of the source electrode of NMOS pipe and PMOS pipe is also exported the final subtraction result of this power and position, the grid of NMOS pipe and PMOS pipe is connected to the borrow output terminal of low power and position jointly, as control signal, and the substrate of this two pipe is connected to source electrode separately with this.Borrow produces and the transmission selected cell is made up of 2 NMOS pipes and the resistance up to mega-ohms.The grid control signal of 2 NMOS pipes comes from data operation and signature analysis circuit unit respectively, substrate is received power supply ground jointly, source electrode is received the borrow output terminal jointly, and by receiving power supply ground up to the resistance of mega-ohms, in addition, positive power end is received in the drain electrode of a NMOS pipe, and the borrow input end of low power and position is received in the drain electrode of another NMOS pipe.
The present invention subtracts each other and the embodiment that designs at two multidigit binary numbers.When two binary numbers subtract each other,, make that low power and position will be to the high-order borrow that is close to, and this high position also may be to more high-order borrow because the minuend of low power and position may be less than subtrahend.Like this, because possible borrow, subtraction is implemented generally must be calculated by turn to high power and position by low power and position, causes the subtraction time-delay to increase.Especially for figure place more subtract a device, the people that may allow slowly of its travelling speed is difficult to accept.Under the integrated travelling speed of existing high speed required, this situation had become the problem of having to solve.The present invention has reasonably utilized the characteristics of binary number and the performance of integrated crystal to implement the present invention in order to overcome the bitwise operation that borrow produces and transmission is brought.When two multidigit binary numbers subtract each other, wherein two of any identical power and position binary numbers are followed such operation rule, adopt positive logic to describe below: when being subtracted the position and subtracting when equating, this power and position is the high power and position transmission of the possible borrow of low power and position, the final subtraction result of this power and position then is to subtract each other the result by this power and position two numbers, promptly binary " 0 " determines jointly with the borrow of low power and position; When subtracting the position is 1 to subtract the position when being 0, and no matter whether low power and position has borrow, and this power and position can be to a high power and position borrow.Because adopted positive logic, so also can say so, this power and position has borrowed 0 to a high power and position.In this case, this final subtraction result also is to subtract each other the result by this numerical digit two number, and promptly binary " 1 " determines jointly with the borrow of low power and position; When subtracting the position is 0 to subtract the position when being 1, and this power and position produces the borrow to a high power and position, and it is 1 that one's own department or unit two numbers subtract each other the result.Just because this " 1 " makes the borrow of this power and position generation is not subjected to low power and position whether to produce the influence of borrow.The low issuable borrow of power and position can only influence the final subtraction result of this power and position, and promptly these power and position two numbers subtract each other the result, and promptly binary " 1 " has determined the net result of this power and position jointly with the possible borrow of low power and position.If low power and position has borrow, this power and position net result is " 0 "; If low power and position does not have borrow, then this power and position net result is constant.Sum up above-mentioned operation rule, can draw such conclusion: when equating with subtrahend with the minuend of power and position, this power and position the possible borrow of low power and position to a high power and position transmission, and when with the minuend of power and position and subtrahend when unequal, this power and position is no longer transmitted the possible borrow of low level, but self produces possible borrow, and the logical value of this borrow is determined by the magnitude relationship of minuend and subtrahend.Based on this reason, the present invention has taked selector switch that possible borrow passage is selected.Like this, when scale-of-two minuend and subtrahend were added to circuit input end, the number on all power and positions carried out computing simultaneously, and opens selector switch simultaneously, selects corresponding borrow passage.The borrow of this moment will be propagated to a high position from low level along selector switch with the velocity of propagation that approaches on lead.Consider the characteristics of this selector switch, the present invention adopts metal-oxide-semiconductor.Because metal-oxide-semiconductor is the break-make by grid control drain-source two interpolars, its control input resistance is big especially, and the drain-source conducting resistance can drop in new technology and be no more than 10 Ω, and off resistance is big especially.So, adopt metal-oxide-semiconductor not only can reduce power consumption, and can shorten the channels spread time-delay, improve arithmetical operation speed.Thereby metal-oxide-semiconductor is a kind of more satisfactory switch.
Based on above-mentioned analysis, this subtracter can concurrent operation, and synchro control parallelly draws final operation result, and possible borrow is transmitted and taken working time hardly.Thereby the present invention not only reduces the computing time-delay, improves travelling speed, reduces hardware cost, reduces power consumption, and simple in structure, and cost is low, expands very high computing position easily to, as 64, or 128 etc., and the only linear increase of its hardware cost and computing figure place.
Can clearer understanding be arranged by reading to above-mentioned content relevant and target of the present invention below in conjunction with innovation pointed in the description of the drawings and the claims with other.
Description of drawings:
In order to understand employed accompanying drawing in detailed description of the present invention all sidedly, will carry out simple explanation to every figure, in the accompanying drawings:
Fig. 1 is a functional-block diagram of the present invention;
Fig. 2 is the calculation specification figure that the present invention is directed to arbitrary power and position number;
Fig. 3 is the embodiment of two 64 bit subtractions of the present invention.
Embodiment:
Hereinafter, will be described in detail the preferred embodiments of the present invention with reference to the accompanying drawings.Note that hereinafter described is representative embodiment of the present invention, and understands and should not be limited to following description when of the present invention.
Fig. 1 is a functional-block diagram of the present invention.Embodiments of the invention are, each power and position all is made up of one 100 unit, Unit 110, Unit 120, by the borrow incoming line of Unit 110 and the borrow output line of Unit 120, the embodiment of all power and positions is coupled together again, constituted the multidigit binary subtracter.
For this inventive embodiment, because the entitlement bit data is concurrent operation in Unit 100, the selector switch of all Unit 120 is parallel opening, all possible borrow along the passage that approaches lead to approach the transmission of wire spread speed.Then, the operation result of possible borrow and Unit 100 is parallel in Unit 110 to carry out computing, exports operation result at last.
Fig. 2 be by the i power and position of two multidigit binary numbers (i=0,1 ..., minuend Ai n-1) and subtrahend Bi, and the common subtraction embodiment that forms of the borrow of low power and position.At first, Ai, Bi again through the two-stage Sheffer stroke gate, export intermediate result Xi and Yi through the one-level not gate at last.The relation of Xi and Ai, Bi is
, this relation shows: when Ai was equal with Bi, Yi=0 met the subtraction rule, and Xi=1 belongs to the negate of Yi; When Ai and Bi were unequal, Yi=1 also met the binary subtraction rule, and Xi=0 also belongs to the negate of Yi.Intermediate result Xi and Yi and low power and position borrow Cin are input to unit 110, Yi receives the source electrode of P type metal-oxide-semiconductor Qi1, Xi receives the drain electrode of N type metal-oxide-semiconductor Qi2, the drain electrode of Qi1 and the source shorted of Qi2 and as the final subtraction result output terminal Si of this i power and position, the grid of two pipes is all received borrow Cin, and the source electrode of receiving at the bottom of the benefit of two pipes separately.Like this,,, when promptly low power and position does not have borrow, do not change the result of Ai-Bi, will choose intermediate result Yi exactly when the borrow of hanging down power and position is a low level 0 according to the subtraction rule.So, the Qi1 conducting, Qi2 ends, S
i=Yi; When the borrow of low power and position was high level 1, promptly low power and position had produced borrow, then will change the result of Ai-Bi, just will choose intermediate result Xi, so the Qi2 conducting, Qi1 ends, S
i=Xi.
Described arbitrary power and position above at the embodiment that has or not the subtraction result under the borrow, describing arbitrary power and position below again is how to implement to produce borrow and transmit borrow.Rejection gate Ui7 realizes function
Promptly work as Ai=0, Bi=1, or say, minuend is during less than subtrahend, and then Zi is a high level 1.Signal Zi receives N type metal-oxide-semiconductor Qi3, and positive supply Vcc is received in the drain electrode of Qi3, and source electrode is received borrow output terminal Cout, mends the end and then receives power supply ground.When Zi is high level, the Qi3 conducting, Cout=Vcc is high level.For another N type metal-oxide-semiconductor Qi4, its grid is received Xi, and the borrow signal wire Cin of low power and position is received in drain electrode, and source electrode is received borrow output line Cout, mends the end and receives power supply ground.When Xi is high level, the Qi4 conducting, Cout=Cin, promptly this power and position the borrow of low power and position to high power and position transmission.Adopt the course of work of the method for exhaustion below to the different value analytic units 120 of Ai and Bi.1. when Ai and Bi are all low level 0 or high level 1, Zi=0, Xi=1, then Qi3 ends, the Qi4 conducting, Cout=Cin, promptly the borrow of low power and position to high power and position transmission.Cin=0, then Cout=0; Cin=1, then Cout=1; 2. work as Ai=0, during Bi=1, Zi=1, Xi=0, then Qi3 conducting, Qi4 ends, and Cout is a high level, represents that this power and position will be to high power and position borrow; 3. work as Ai=1, during Bi=0, Zi=0, Xi=0, then Qi3 and Qi4 end.Considering that in such cases this power and position in no case can produce borrow, is the 110 unit operate as normal that low level could guarantee high one-level power and position but must make Cout.So, Cout is received ground with a resistance R i1 up to mega-ohms.When Qi3 and Qi4 ended, resistance R i1 pulled down to low level to Cout by force.
In an embodiment of the present invention, consider the worst situation, the minuend and the subtrahend of all power and positions all equate, in this case, the Qi4 conducting of all power and positions, Qi3 ends, and promptly unit 120 is in the borrow state that transmits.Because there is certain resistance in Qi4 in conducting state, will produce certain potential difference (PD).So if C-1 is a high level, must adopt power supply directly to drive.The reason that this drain electrode of the Qi3 of each power and position just directly connects power Vcc rather than directly meets the subtrahend Bi of this power and position.
Utilize Fig. 2 embodiment of the present invention.As long as can accomplish that the drain-source conducting resistance of metal-oxide-semiconductor is infinitely few, promptly reach the conductivity of general lead commonly used such as aluminium, two binary numbers that the subtracter of being implemented just can expand to suitable seniority subtract each other, as 128,256 etc.Fig. 3 has described two embodiment that binary number subtracts each other of one 64.This circuit has clearly reflected subtraction implementation process and the generation of borrow or the process of transmission of arbitrary power and position.
Subtraction circuit of the present invention can be implemented additive operation equally, as long as when doing addition, being input to several negates that subtrahend Bi holds, and to make the received borrow C-1 of minimum power and position be high level, and this circuit just can be implemented additive operation.
Although introduced the present invention, should be understood that the people who is proficient in this area still can carry out various modifications on pro forma and the details to the present invention, and does not break away from the spirit and scope of the present invention by describing specific embodiment of the present invention.
Claims (8)
1. binary digit subtracter, it is characterized in that: described binary digit subtracter, it is the built-up circuit that subtracts each other about two multidigit binary numbers, form by computing circuit at each power and position, the computing circuit of each power and position all is identical, all be by a data computing and signature analysis circuit unit, a net result arithmetic element, and a borrow produces and transmission selected cell composition;
Described data operation and signature analysis circuit unit are by an XOR gate, same or a door and a rejection gate composition, XOR gate is used to produce the intermediate result of subtracting each other of this power and position binary number, same or Men Ze is used to produce the radix-minus-one complement of intermediate result, and produce and the borrow transmission of control signals of transmission selected cell as borrow, the output of rejection gate is then as producing when the borrow of this power and position minuend during less than subtrahend and the borrow generation control signal of transmission selected cell;
Described net result arithmetic element is by a NMOS pipe and the selection circuit that the PMOS pipe constitutes, wherein the source electrode of the drain electrode of NMOS pipe and PMOS pipe is imported the intermediate operations result from data operation and signature analysis circuit unit respectively, the drain electrode short circuit of the source electrode of NMOS pipe and PMOS pipe is also exported the final subtraction result of this power and position, the grid of NMOS pipe and PMOS pipe is connected to the borrow output terminal of low power and position jointly, as control signal, and the substrate of this two pipe is connected to source electrode separately with this;
Described borrow produces and the transmission selected cell is made up of 2 NMOS pipes and the resistance up to mega-ohms, the grid control signal of 2 NMOS pipes comes from data operation and signature analysis circuit unit respectively, substrate is received power supply ground jointly, source electrode is received the borrow output terminal jointly, and by receiving power supply ground up to the resistance of mega-ohms, in addition, positive power end is received in the drain electrode of a NMOS pipe, and the borrow input end of low power and position is received in the drain electrode of another NMOS pipe;
When implementing binary digit subtracter, described binary digit subtracter has been followed such algorithmic rule: when two multidigit binary numbers subtract each other, two binary numbers for any identical power and position, when being subtracted figure place and subtracting figure place and equate, this power and position is transmitted the possible borrow of low power and position to a high power and position; When subtracting figure place is 1, and subtracting figure place is 0 o'clock, and no matter whether low power and position has borrow, and this power and position can when adopting positive logic to describe, can not said so to a high power and position borrow yet, and this power and position has been borrowed " 0 " to a high power and position; When subtracting figure place is 0, subtracting figure place is 1 o'clock, this power and position produces the borrow 1 to a high power and position, the borrow that makes this power and position produce is not subjected to low power and position whether to produce the influence of borrow, under any circumstance, the low issuable borrow of power and position affects the final subtraction result of this power and position, and it and these power and position two numbers subtract each other the net result that the result has determined this power and position jointly, if low power and position transmission borrow 1, this power and position net result are to choose these power and position two numbers to subtract each other the anti-of result; If low power and position transmission borrow 0, the then result of this power and position net result for selecting these power and position two numbers to subtract each other.
2. binary digit subtracter as claimed in claim 1 is characterized in that: the subtraction of two multidigit binary numbers walks abreast, and final subtraction result is parallel to be drawn.
3. binary digit subtracter as claimed in claim 1 is characterized in that: the borrow of any power and position produces and the transmission selected cell is parallel controlled, synchronous working, and the borrow transmission channel is to approach conductor line.
4. binary digit subtracter as claimed in claim 1 is characterized in that: the intermediate operations result of each power and position of binary load and borrow produce and the control signal of transmission selected cell is concurrent operation, produce synchronously.
5. binary digit subtracter as claimed in claim 1 is characterized in that: which kind of intermediate result the net result of this power and position selects by the borrow decision of low power and position, and this circuit computing of all power and positions is parallel carrying out, and obtains a result synchronously.
6. binary digit subtracter as claimed in claim 1 is characterized in that: the high value pull down resistor that the borrow output terminal inserts guaranteed this power and position minuend during greater than subtrahend this power and position to the borrow of high one-level power and position input low level.
7. binary digit subtracter as claimed in claim 1 is characterized in that: this subtracter has been followed the algorithmic rule that binary number subtracts each other, and has implemented the synchronous generation and the transmission of borrow.
8. binary digit subtracter as claimed in claim 1 is characterized in that: this subtracter uses metal-oxide-semiconductor to make.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101939252A CN101201731B (en) | 2008-02-15 | 2008-02-15 | Binary digit subtracter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007101939252A CN101201731B (en) | 2008-02-15 | 2008-02-15 | Binary digit subtracter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101201731A CN101201731A (en) | 2008-06-18 |
| CN101201731B true CN101201731B (en) | 2010-08-18 |
Family
ID=39516907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2007101939252A Expired - Fee Related CN101201731B (en) | 2008-02-15 | 2008-02-15 | Binary digit subtracter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101201731B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2629453C1 (en) * | 2016-04-19 | 2017-08-29 | Федеральное государственное бюджетное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" | Binary subtractor |
| RU2709653C1 (en) * | 2019-03-11 | 2019-12-19 | федеральное государственное бюджетное образовательное учреждение высшего образования "Ульяновский государственный технический университет" | Binary subtractor |
| CN110209375B (en) * | 2019-05-30 | 2021-03-26 | 浙江大学 | Multiply-accumulate circuit based on radix-4 coding and differential weight storage |
| CN110262772B (en) * | 2019-06-18 | 2023-01-03 | 北京大学深圳研究生院 | Two-bit and three-bit approximate adder and approximate adder |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4172288A (en) * | 1976-03-08 | 1979-10-23 | Motorola, Inc. | Binary or BCD adder with precorrected result |
| US4783757A (en) * | 1985-12-24 | 1988-11-08 | Intel Corporation | Three input binary adder |
| CN1232561A (en) * | 1996-10-02 | 1999-10-20 | Arm有限公司 | Digital adder circuit |
| CN1164988C (en) * | 2002-01-17 | 2004-09-01 | 北京大学 | Structure and circuit of logarithmic skip adder |
| CN1570844A (en) * | 2003-07-21 | 2005-01-26 | 中国科学院微电子中心 | Plus-minus compressor for three inputs |
-
2008
- 2008-02-15 CN CN2007101939252A patent/CN101201731B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4172288A (en) * | 1976-03-08 | 1979-10-23 | Motorola, Inc. | Binary or BCD adder with precorrected result |
| US4783757A (en) * | 1985-12-24 | 1988-11-08 | Intel Corporation | Three input binary adder |
| CN1232561A (en) * | 1996-10-02 | 1999-10-20 | Arm有限公司 | Digital adder circuit |
| CN1164988C (en) * | 2002-01-17 | 2004-09-01 | 北京大学 | Structure and circuit of logarithmic skip adder |
| CN1570844A (en) * | 2003-07-21 | 2005-01-26 | 中国科学院微电子中心 | Plus-minus compressor for three inputs |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101201731A (en) | 2008-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Navi et al. | A novel low-power full-adder cell for low voltage | |
| CN101201731B (en) | Binary digit subtracter | |
| Hussain et al. | Performance comparison of 1-bit conventional and hybrid full adder circuits | |
| Yadav et al. | Design and implementation of 4-bit arithmetic and logic unit chip with the constraint of power consumption | |
| Sadani et al. | Power and Delay Efficient Three-Input XOR/XNOR With Systematic Cell Design Methodology | |
| US7508233B2 (en) | Full-adder of complementary carry logic voltage compensation | |
| Ko et al. | An optimal design methodology of ternary logic in ISO-device ternary CMOS | |
| Kumar et al. | Study of threshold gate and CMOS logic style based full adders circuits | |
| CN111313890B (en) | High-performance approximate full adder gate-level unit | |
| Khan et al. | Design a 4-bit carry look-ahead adder using pass transistor for less power consumption and maximization of speed | |
| Yadav et al. | A study and comparative analysis of low power hybrid-CMOS 1-bit full adders in deep-submicron technology | |
| Gope et al. | Modelling of single electron ternary flip-flop using SIMON | |
| Ghabri et al. | Performance optimization of 1-bit full adder cell based on cntfet transistor | |
| Sarkar et al. | 9T and 8T Full Subtractor Design Using Modified GDI and 3T XOR Technique | |
| Sugandha et al. | Low Power 14T Hybrid Full Adder Cell | |
| Haribabu et al. | Design and Implementation of Ripple Carry Adder using Various CMOS Full Adder Circuits in 180nm and 130nm Technology | |
| Karunakaran et al. | Power Optimized Multiplier Using Shannon Based Multiplexing Logic | |
| Hussain et al. | An energy efficient and fast hybrid full adder circuit | |
| Kattepogu et al. | Low Power High Speed Modified GDI Full Adder Implemented by NCFET Technologies | |
| Roy et al. | Low Power Adder Circuit Based on Coupling Technique | |
| Priyadarshini et al. | Comparative analysis of a low power and high speed hybrid 1-bit full adder for ULSI circuits | |
| Sai Vamsi et al. | Design and Implementation of Power-Efficient and Fast Full Adders Using Hybrid Logics | |
| Nageswara Reddy et al. | Design of a Low Power Full Adder with a Two Transistor EX-OR Gate Using Gate Diffusion Input of 90 nm | |
| Murthy et al. | A novel design of multiplexer based full-adder cell for power and propagation delay optimizations | |
| Murthy | Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100818 Termination date: 20130215 |