CN101192550A - Semiconductor packaging member and method for fabricating the same - Google Patents
Semiconductor packaging member and method for fabricating the same Download PDFInfo
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- CN101192550A CN101192550A CNA2006101633454A CN200610163345A CN101192550A CN 101192550 A CN101192550 A CN 101192550A CN A2006101633454 A CNA2006101633454 A CN A2006101633454A CN 200610163345 A CN200610163345 A CN 200610163345A CN 101192550 A CN101192550 A CN 101192550A
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- package part
- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Lead Frames For Integrated Circuits (AREA)
Abstract
The invention relates to an encapsulation piece of a semiconductor and a manufacturing method thereof. The method essentially includes the following steps: a sacrificial layer is laid between a metallic carrier tool and an insulating layer, and preconcerted parts of the sacrificial layer and the insulating layer are opened with a plurality of perforative openings, so that a conductive metal layer can be generated in the openings subsequently and a patterned line layer can be generated on the insulating layer subsequently, and the patterned line layer is electrically connected with the conductive metal layer; then at least one chip is electrically connected with the patterned line layer and an encapsulated colloid which wraps the chip and the patterned line layer, in other words, the metallic carrier tool and the sacrificial layer are removed, so that the conductive metal layer generated formerly to prong the sacrificial layer and the opening of the insulating layer is relatively protruded when compared with the insulating layer; in this way, when the completed encapsulation piece of the semiconductor is electrically connected with outer devices, a distance between the encapsulation piece of the semiconductor and the outer devices can be increased, as a result, thermal stress generated by difference of thermal expansion coefficient between the encapsulation piece of the semiconductor and the outer devices can be reduced, and the reliability is improved.
Description
Technical field
The present invention relates to a kind of semiconductor package part and method for making thereof, refer to a kind of semiconductor package part and method for making thereof that does not need bearing part especially.
Background technology
The conventional semiconductors chip forms semiconductor package part with lead frame (Lead Frame) as chip bearing member.This lead frame comprises chip carrier and is formed on this chip carrier a plurality of lead foots on every side, after treating that the semiconductor chip gluing electrically connects this chip and lead foot to chip carrier and with bonding wire, coat the inner segment of this chip, chip carrier, bonding wire and lead foot via potting resin and form the semiconductor package part of this tool lead frame.
With lead frame as the kenel of the semiconductor sealing of chip bearing member and of a great variety, there is not pin (Quad Flat Non-leaded with regard to the quad flat formula, QFN) semiconductor package part, it is characterized in that not being provided with outer lead foot, promptly be not formed with as existing quad flat formula encapsulation (QuadFlat package, QFP) be used in the semiconductor package part and the extraneous outer lead foot that electrically connects, so, will be dwindled the size of semiconductor package part.As shown in Figure 1, lead frame chip carrier 11 bottom surfaces and lead foot 12 bottom surfaces of this QFN semiconductor package part 1 all expose outside packing colloid 15, make to connect to put on this chip carrier 11 and to be electrically connected to the semiconductor chip 13 of lead foot 12, and this QFN semiconductor package part must directly be electrically connected with weld pad 100 on external device such as the printed circuit board (PCB) (printed circuit board) 10 by soldering tin material 16 mutually by these lead foot 12 exposed surfaces by bonding wire 14.
In addition, be accompanied by becoming more and more important of the compact development trend of semiconductor product, the traditional welding framework often can't further dwindle the whole height of packaging part because of the restriction of its thickness, therefore, so developing, industry a kind of semiconductor package part that does not have bearing part, wish by lowering existing lead frame thickness, so that its integral thickness is able to is more more frivolous than traditional welding frame-type packaging part.
See also shown in Figure 2, it is a United States Patent (USP) the 5th, 830, the semiconductor package part of No. 800 no bearing parts that case disclosed, this semiconductor package part is main to form a plurality of plating weld pads (Pad) 21 according to configuration earlier on copper bearing part (not shown), the coating of this plating weld pad 21 comprises gold/palladium/nickel/palladium (Au/Pd/Ni/Pd) layer, and its thickness is approximately 6 μ m; Then, chip 22 is set on this bearing part again and carries out bonding wire 23 and connect operation, also encapsulate molding to form packing colloid 24, and then remove this copper bearing part so that its plating weld pad 21 is emerging in the external world, finish need not to prepare chip bearing member and connect the packaging part of putting use thus, and make this packaging part be able to directly form scolding tin contact (solder joint) 26 and electrically connect mutually with weld pad 200 on external device such as the printed circuit board (PCB) (printed circuit board) 20 by soldering tin material by these plating weld pad 21 exposed surfaces for chip.
But aforesaid QFN semiconductor package part and not having in the semiconductor package part of bearing part, when the chip that uses Highgrade integration (Highly Integrated), be that the electronic building brick density laid of chip is when improving, the laying quantity that relatively also need improve the corresponding lead foot that electrically connects or electroplate weld pad, and make lead foot or electroplate the distance of weld pad and chip chamber and the arc length increase of bonding wire, the degree of difficulty of bonding wire operation is promoted, even problems such as bonding wire skew and short circuit easily take place, have a strong impact on the electric connection quality.
In view of aforesaid drawbacks, United States Patent (USP) the 6th, 884, No. 652 a kind of semiconductor package parts that can effectively shorten the bonding wire arc length of announcement.As shown in Figure 3, this semiconductor package part includes dielectric materials layer 30, offers a plurality of openings 300 that run through dielectric materials layer 30 at its predetermined position; Scolder (Solder) 31 is in the opening 300 of this dielectric materials layer 30 respectively of being laid in; First thin copper layer 32 is formed on dielectric materials layer 30 and the scolder 31; The second bronze medal layer 33 on first thin copper layer 32 that is laid in, and makes first thin copper layer 32 and the second bronze medal layer 33 be formed with a plurality of conductive traces (Conductive Trace) 330, and each conductive trace 330 has terminal (Terminal) 331; Metal level 34 is on the terminal 331 of each conductive trace 330 that is laid in; At least one chip 35 is put on the predetermined position of conductive trace 330 by adhesive is glutinous; A plurality of bonding wires 36 are used to electrically connect chip 35 to the terminal 331 that is laid with metal level 34; And packing colloid (Encapsulant) 37, be used for coating chip 35, bonding wire 36 and conductive trace 330, and make dielectric materials layer 30 and scolder 31 expose outside packing colloid 37.
The advantage of above-mentioned semiconductor package part is to need not to use as prefabricated lead frame, substrate etc. as chip bearing member, and conductive trace must be laid and the laying zone of the bonding wire that can deep be connected with chip in response to the integrated degree of elasticity ground of chip, be used to electrically connect the bonding wire arc length of chip with effective shortening to the conductive trace terminal, and shorten electrical connection path between chip and conductive trace, thereby can improve the circuit layout of semiconductor package part and electrically connect quality.
Yet, no matter also or do not have for the halfbody packaging part of bearing part for the aforementioned QFN of being semiconductor package part, when electrically connecting mutually to form the scolding tin contact by surface mount technology (SMT) between this semiconductor package part and printed circuit board (PCB) by the soldering tin material reflow, can produce thermal stress because of the different of material between this semiconductor package part and printed circuit board (PCB), wherein this thermal stress and semiconductor package part are directly proportional with thermal expansion coefficient difference between printed circuit board (PCB), and be inversely proportional to the height of this scolding tin contact, therefore, to be electrically connected to the semiconductor package part of printed circuit board (PCB) at aforementioned existing employing surface mount technology (SMT), it only connects by soldering tin material and places on the printed circuit board (PCB), and because this semiconductor package part is different with the thermal coefficient of expansion between printed circuit board (PCB), therefore will produce tangible thermal stress on the scolding tin contact that provides it to follow mutually, this thermal stress is proportional to ((α
2-α
1) Δ T δ
1)/h wherein should (α
2-α
1) be the coefficient of thermal expansion differences between semiconductor package part and printed circuit board (PCB), this Δ T is the maximum temperature difference between semiconductor package part and printed circuit board (PCB), this δ
1Be the distance of semiconductor package part center to farthest scolding tin contact, this h is a scolding tin contact height.So, in aforementioned existing semiconductor package part, because the height of this scolding tin contact is extremely low, to cause on the scolding tin contact between this semiconductor package part and printed circuit board (PCB), producing great thermal stress, so not only cause reduction scolding tin contact fatigue life (fatigue life) between this semiconductor package part and printed circuit board (PCB), very will cause this scolding tin contact that crack (crack) problem takes place, have a strong impact on the confidence level of electronic product; Relatively, if increase the setting and the height of soldering tin amount, also can be too much, or connecing between this packaging part and printed circuit board (PCB) put distance control when bad because of soldering tin amount, cause adjacent soldering tin material contact and the problem that is short-circuited causes the puzzlement on the manufacture method.
Therefore, how to address the above problem and a kind of semiconductor package part and method for making thereof of not having bearing part can be provided, and can avoid the scolding tin contact that crack and the not good problem of confidence level take place, and flexibly laid circuit and can effectively be shortened the bonding wire arc length, thereby improve circuit layout and electrically connect quality, real is very urgent.
Summary of the invention
Mirror is arranged in aforementioned and other problem, main purpose of the present invention is to provide a kind of not to be needed bearing part and is formed with semiconductor package part and method for making thereof for the salient point that electrically connects with the external world.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof that does not need bearing part, can reduce the thermal stress that on the scolding tin contact between semiconductor package part and printed circuit board (PCB), produces, to increase confidence level.
Another purpose of the present invention is to provide a kind of semiconductor package part and method for making thereof that does not need bearing part, avoid connecing between this semiconductor package part and printed circuit board (PCB) to put distance control when bad, cause the contact of adjacent soldering tin material and the problem that is short-circuited causes the puzzlement on the manufacture method.
Another object of the present invention is to provide a kind of semiconductor package part and method for making thereof, effectively improved the circuit layout of semiconductor package part and electrically connect quality.
For reaching above-mentioned and other purpose, the present invention discloses a kind of semiconductor package part, comprising: insulating barrier offers a plurality of openings that run through in this insulating barrier; Conductive metal layer, it is formed in this opening, and protrudes from a surface of this insulating barrier; Patterned line layer is formed at another surface of this insulating barrier and goes up and be electrically connected to this conductive metal layer; Chip, it connects puts on the predetermined position of this insulating barrier, and is electrically connected to this patterned line layer; And packing colloid, it coats this chip and patterned line layer.
The method for making of this semiconductor package part comprises the following steps: to lay sacrifice layer (sacrificial layer) on a surface of metal carrier, and on this sacrificial layer surface, lay insulating barrier, and offer a plurality of openings that run through at the predetermined position of this sacrifice layer and insulating barrier, to expose outside this metal carrier; In this opening, form conductive metal layer; On this insulating barrier, form patterned line layer, and make this patterned line layer be electrically connected to this conductive metal layer; On the precalculated position of this insulating barrier, connect and put at least one chip, and make this chip be electrically connected to this patterned line layer; Form packing colloid to coat this chip and patterned line layer; And remove this metal carrier and sacrifice layer, expose outside this insulating barrier and conductive metal layer thus, and make this conductive metal layer evagination in this insulating barrier.
Therefore semiconductor package part of the present invention and method for making thereof mainly are when this semiconductor package part of manufacture method, between metal carrier and insulating barrier, additionally lay sacrifice layer, and offer a plurality of openings that run through at the predetermined position of this sacrifice layer and insulating barrier, in this opening, form conductive metal layer and on this insulating barrier, form patterned line layer for follow-up, and make this patterned line layer be electrically connected to this conductive metal layer, so that being connect, at least one chip puts and is electrically connected to this patterned line layer, and after forming the packing colloid that coats this chip and patterned line layer, remove this metal carrier and sacrifice layer, protruded from this insulating barrier relatively for before being formed on the conductive metal layer that runs through this sacrifice layer and insulating barrier opening, so when the semiconductor package part that will be finished is electrically connected to as external device (ED)s such as printed circuit board (PCB)s by this conductive metal layer with soldering tin material, can increase the distance between this semiconductor package part and printed circuit board (PCB), the thermal stress that attenuating is produced because of the thermal coefficient of expansion between semiconductor package part and printed circuit board (PCB) (CTE) difference, and then lifting confidence level, avoid increasing the soldering tin amount of electric connection simultaneously, cause the contact of adjacent soldering tin material and the problem that is short-circuited causes the puzzlement on the manufacture method.
Moreover, semiconductor package part of the present invention need not to use chip bearing member (as prefabricated lead frame, substrate etc.), to reduce manufacturing cost, and meet the compact development trend of electronic product, formed patterned line layer is able to because the integrated degree of elasticity of chip ground is laid and can be deeply and the zone of chip do electric connection in this semiconductor package part simultaneously, effectively shorten and electrically connect the bonding wire arc length of chip to patterned line layer, and shorten electrical connection path, improve the circuit layout of semiconductor package part and electrically connect quality.
Description of drawings
Fig. 1 shows that having the quad flat formula now does not have pin (Quad Flat Non-leaded, QFN) cutaway view of semiconductor package part;
Fig. 2 is the cutaway view of semiconductor package part that shows the no bearing part of No. the 5th, 830,800, United States Patent (USP);
Fig. 3 is the cutaway view of semiconductor package part that shows the no bearing part of No. the 6th, 884,652, United States Patent (USP);
Fig. 4 A to 4G is the schematic diagram that shows semiconductor package part of the present invention and method for making first embodiment thereof;
Fig. 4 D ' shows among the present invention to form tectal schematic diagram on patterned line layer because of demand; And
Fig. 5 A and 5B are the cutaway views that shows semiconductor package part second embodiment of the present invention.
[primary clustering symbol description]
10 printed circuit board (PCB)s
100 weld pads
11 chip carriers
12 lead foots
13 semiconductor chips
14 bonding wires
15 packing colloids
16 soldering tin materials
21 electroplate weld pad
22 chips
23 bonding wires
24 packing colloids
26 scolding tin contacts
20 printed circuit board (PCB)s
200 weld pads
30 dielectric materials layers
300 openings
31 scolders
32 first thin copper layers
33 second bronze medal layers
330 conductive traces
331 terminals
34 metal levels
35 chips
36 bonding wires
37 packing colloids
40 metal carrier
41 sacrifice layers
410 openings
42 insulating barriers
43 conductive metal layers
44 bonding wires
45 patterned line layer
450 terminals
46 metal levels
47 cover layers
48 chips
49 packing colloids
54 welding blocks
55 conductive metal layers
550 terminals
58 chips
56 metal levels
59 packing colloids
Embodiment
Below be that those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed by particular specific embodiment explanation embodiments of the present invention.
First embodiment
Seeing also Fig. 4 A to 4G, is the generalized section that semiconductor package part of the present invention and method for making first thereof are implemented.
Shown in Fig. 4 A, at first, preparation is as the metal carrier (Carrier) 40 of copper coin (Cu Plate), and on a surface of this metal carrier 40, lay sacrifice layer 41, this sacrifice layer 41 is for example made for the material of polymer (polymer), as epoxides (epoxy), photoresist (photo-resist) etc., its thickness is about 10 to 30 μ m.This sacrifice layer 41 with as traditional coating, exposure, development and etched mode, or form in screen printing mode (stencilprinting) and to have a plurality of sacrifice layers 41 that run through opening 410.
Shown in Fig. 4 B, on these sacrifice layer 41 surfaces, lay insulating barrier 42, this insulating barrier 42 for example is soldering-resistance layer (Solder Mask), and with as traditional coating, exposure, development and etched mode make this insulating barrier 42 appear the opening 410 of this sacrifice layer 41, and then expose this metal carrier 40.Certainly also can be after laying sacrifice layer and insulating barrier, more directly to form the opening that runs through this sacrifice layer 41 and insulating barrier 42, to expose outside this metal carrier 40 as laser perforate mode.
Shown in Fig. 4 C, then, form conductive metal layer 43 with plating mode at this opening 410 by this metal carrier 40, this conductive metal layer 43 for example is nickel/gold (Ni/Au) layer.This conductive metal layer 43 is and supplies follow-up semiconductor package part of finishing and external device (ED) to make the electricity connection end of electrical couplings.
Shown in Fig. 4 D, on this insulating barrier 42, form patterned line layer 45, and make this patterned line layer 45 be electrically connected to this conductive metal layer 43; This patterned line layer 45 can be by forming thin copper layer with electroless plating (Electroless Plating) or sputter modes such as (Sputtering) on this insulating barrier 42, utilize plating mode on this thin copper layer, to form thick copper layer again, also through overexposure (Exposing), develop (Developing) and etching (Etching) mode and the patterned line layer 45 that forms, wherein this patterned line layer 45 has terminal 450, and this terminal 450 electrically connects with semiconductor chip for follow-up.Can also form metal level 46 by plating mode in addition on the terminal 450 of this patterned line layer 45, this metal level 46 is silver (Ag) layer or nickel/gold (Ni/Au) layer.
Perhaps, see also Fig. 4 D ', can on this patterned line layer 45, form cover layer 47, and make respectively that the terminal 450 or the metal level 46 of this patterned line layer 45 expose outside this cover layer 47, the material of this cover layer 47 for example is soldering-resistance layer (Solder Mask) or ABF (Ajinomoto Build-up Film) layer.
Shown in Fig. 4 E, on the predetermined position of this insulating barrier 42, connect and put at least one chip 48, the line lead bonding method operation of going forward side by side electrically connects the metal level 46 of this chip 48 to this patterned line layer terminal to utilize bonding wire 44.
Shown in Fig. 4 F, then, carry out mold pressing (Molding) manufacture method, to form the packing colloid 49 that coats this chip 48, bonding wire 44 and patterned line layer 45, the assembly that packing colloid 49 is coated is exempted from extraneous aqueous vapor or pollutant sources infringement.
Shown in Fig. 4 G, at last, carry out cutting operation by the predetermined semiconductor package part planar dimension that forms, and remove this metal carrier 40 and sacrifice layer 41 with etching mode, expose outside this insulating barrier 42 and conductive metal layer 43 thus, wherein this conductive metal layer 43 protrudes this insulating barrier 42, and its protrusion height is about 10 to 30 μ m (also being previous sacrifice layer 41 thickness), to make the semiconductor package part that the present invention need not bearing part, so can be by conductive metal layer 43 these semiconductor package parts of increase of protrusion and the distance between external device (ED) (for example printed circuit board (PCB)), the thermal stress of attenuating because of being produced because of thermal coefficient of expansion (CTE) difference between semiconductor package part and external device (ED), and then promote confidence level.In addition, also or can carry out etching earlier and remove this metal carrier 40 and sacrifice layer 41, carry out cutting operation again, to make the semiconductor package part that the present invention need not bearing part.
By aforesaid method for making, the present invention also discloses a kind of semiconductor package part, comprising: insulating barrier 42 offers a plurality of openings that run through in this insulating barrier 42; Conductive metal layer 43, it is formed in this opening, and protrudes from a surface of this insulating barrier 42; Patterned line layer 45 is formed on these insulating barrier 42 another surfaces and goes up and be electrically connected to this conductive metal layer 43; Chip 48, it connects puts on the predetermined position of this insulating barrier 42, and is electrically connected to this patterned line layer 45; And packing colloid 49, it coats this chip 48 and patterned line layer 45.
Second embodiment
See also Fig. 5 A and 5B, be the cutaway view of semiconductor package part second embodiment of the present invention.Shown in Fig. 5 A, the semiconductor package part of present embodiment is roughly roughly the same with previous embodiment, and main difference is that the chip 58 of this embodiment is to connect in upside-down method of hull-section construction (Flip-Chip) mode to be located on the patterned line layer 55; Know clearly it, when sticking brilliant operation, the action face of chip 58 is towards patterned line layer 55 and be electrically connected to the terminal 550 of patterned line layer 55 or the metal level 56 on the terminal 550 by a plurality of welding blocks (Solder Bump) 54, forms the packing colloid 59 that coats this chip 58 again.Than connect chip and patterned line layer with bonding wire, utilize the upside-down method of hull-section construction technology of welding block further to be shortened the electrical connection path of chip and patterned circuit interlayer, more can guarantee the electric connection quality of chip and patterned circuit interlayer.
In addition, shown in Fig. 5 B, also can make the non-action face of this chip 58 expose outside the packing colloid 59 of coating chip 58,, and then improve the radiating efficiency of chip 58 so that the heat that chip 58 runnings produce is able to effectively dissipate to the external world by this non-action face that exposes.
Therefore semiconductor package part of the present invention and method for making thereof mainly are when making this semiconductor package part, between metal carrier and insulating barrier, additionally lay sacrifice layer, and offer a plurality of openings that run through at the predetermined position of this sacrifice layer and insulating barrier, in this opening, form conductive metal layer and on this insulating barrier, form patterned line layer for follow-up, and make this patterned line layer be electrically connected to this conductive metal layer, so that being connect, at least one chip puts and is electrically connected to this patterned line layer, and after forming the packing colloid that coats this chip and patterned line layer, remove this metal carrier and sacrifice layer, protruded from this insulating barrier relatively for before being formed on the conductive metal layer that runs through this sacrifice layer and insulating barrier opening, so when the semiconductor package part that will be finished is electrically connected to as external device (ED)s such as printed circuit board (PCB)s by this conductive metal layer with soldering tin material, can increase the distance between this semiconductor package part and printed circuit board (PCB), the thermal stress that attenuating is produced because of the thermal coefficient of expansion between semiconductor package part and printed circuit board (PCB) (CTE) difference, and then lifting confidence level, avoid increasing the soldering tin amount of electric connection simultaneously, cause the contact of adjacent soldering tin material and the problem that is short-circuited causes the puzzlement on the manufacture method.
Moreover, semiconductor package part of the present invention need not to use chip bearing member (as prefabricated lead frame, substrate etc.), can reduce manufacturing cost, and meet the compact development trend of electronic product, formed patterned line layer is able to lay and can be deeply and the zone of chip do electric connection because of the integrated degree of elasticity ground of chip in this semiconductor package part simultaneously, effectively shorten and electrically connect the bonding wire arc length of chip to patterned line layer, and shorten electrical connection path, improve the circuit layout of semiconductor package part and electrically connect quality.
The foregoing description is illustrative principle of the present invention and effect thereof only, but not is used to limit the present invention, and any those skilled in the art all can be under spirit of the present invention and category, and the foregoing description is modified and changed.Therefore, the scope of the present invention should be as described in claims.
Claims (19)
1. the method for making of a semiconductor package part, it comprises:
On a surface of carrier, lay sacrifice layer, and on this sacrifice layer, lay insulating barrier, and offer the opening that majority runs through, to expose outside this carrier in the predetermined position of this sacrifice layer and insulating barrier;
In this opening, form conductive metal layer;
On this insulating barrier, form patterned line layer, and make this patterned line layer be electrically connected to this conductive metal layer;
On the precalculated position of this insulating barrier, connect and put at least one chip, and make this chip be electrically connected to this patterned line layer;
Form packing colloid to coat this chip and patterned line layer; And
Remove this carrier and sacrifice layer, expose outside this insulating barrier and conductive metal layer thus, and make this conductive metal layer protrude from this insulating barrier.
2. the method for making of semiconductor package part according to claim 1, wherein, this sacrifice layer is that polymeric material is made.
3. the method for making of semiconductor package part according to claim 2, wherein, this sacrifice layer is one of them of epoxides and photoresist, its thickness is about 10～30 μ m.
4. the method for making of semiconductor package part according to claim 1, wherein, this insulating barrier is a soldering-resistance layer.
5. the method for making of semiconductor package part according to claim 1, wherein, this conductive metal layer is nickel/gold layer, to make the electricity connection end of electrical couplings as semiconductor package part and external device (ED).
6. the method for making of semiconductor package part according to claim 1, wherein, this patterned line layer forms thin copper layer by the wherein a kind of mode with electroless plating and sputter on this insulating barrier, utilize plating mode on this thin copper layer, to form thick copper layer again, form through overexposure, development and etching mode again.
7. the method for making of semiconductor package part according to claim 1 wherein, after laying sacrifice layer and insulating barrier, directly forms the opening that runs through this sacrifice layer and insulating barrier in laser perforate mode, to expose outside this carrier.
8. the method for making of semiconductor package part according to claim 1, wherein, this sacrifice layer forms the sacrifice layer with a plurality of openings by wherein a kind of mode of coating, exposure, development and etching and screen printing.
9. the method for making of semiconductor package part according to claim 8, wherein, this insulating barrier makes this insulating barrier appear the opening of this sacrifice layer by coating, exposure, development and etched mode, and then exposes this carrier.
10. semiconductor package part, it comprises:
Insulating barrier offers a plurality of openings that run through in this insulating barrier;
Conductive metal layer, it is formed in this opening, and protrudes from a surface of this insulating barrier;
Patterned line layer, it is formed at another surface of this insulating barrier and goes up and be electrically connected to this conductive metal layer;
Chip, it connects puts on the predetermined position of this insulating barrier, and is electrically connected to this patterned line layer; And
Packing colloid, it coats this chip and patterned line layer.
11. semiconductor package part according to claim 10, wherein, this insulating barrier is a soldering-resistance layer.
12. semiconductor package part according to claim 10, wherein, this conductive metal layer is a nickel/gold layer, to make the electricity connection end of electrical couplings as semiconductor package part and external device (ED).
13. semiconductor package part according to claim 10, wherein, this patterned line layer has terminal, and this terminal offers semiconductor chip and electrically connects.
14. semiconductor package part according to claim 13 wherein, also is formed with metal level on the terminal of this patterned line layer.
15. semiconductor package part according to claim 14, wherein, this metal level is one of them of silver layer and nickel/gold layer.
16. according to claim 13 or 14 described semiconductor package parts, wherein, be formed with cover layer on this patterned line layer, and make the terminal of this patterned line layer or metal level expose outside this cover layer, this cover layer is one of them of soldering-resistance layer and ABF layer.
17. semiconductor package part according to claim 10, wherein, this chip is electrically connected to this patterned line layer in wherein a kind of mode of terminal conjunction method and flip-chip method.
18. semiconductor package part according to claim 10, wherein, this chip has action face and non-action face, and the action face of this chip is electrically connected to patterned line layer in the upside-down method of hull-section construction mode, and makes the non-action face of this chip expose outside packing colloid.
19. semiconductor package part according to claim 10, wherein, this conductive metal layer protrudes this insulating barrier height and is about 10～30 μ m.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101633454A CN101192550A (en) | 2006-12-01 | 2006-12-01 | Semiconductor packaging member and method for fabricating the same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2006101633454A CN101192550A (en) | 2006-12-01 | 2006-12-01 | Semiconductor packaging member and method for fabricating the same |
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| CN101192550A true CN101192550A (en) | 2008-06-04 |
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| CNA2006101633454A Pending CN101192550A (en) | 2006-12-01 | 2006-12-01 | Semiconductor packaging member and method for fabricating the same |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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