CN101110584B - Driving circuit - Google Patents
Driving circuit Download PDFInfo
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- CN101110584B CN101110584B CN2007100258032A CN200710025803A CN101110584B CN 101110584 B CN101110584 B CN 101110584B CN 2007100258032 A CN2007100258032 A CN 2007100258032A CN 200710025803 A CN200710025803 A CN 200710025803A CN 101110584 B CN101110584 B CN 101110584B
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Abstract
The present invention discloses a drive circuit, which comprises a voltage shift circuit and a drive voltage output circuit and is characterized in that the drive voltage output circuit is composed of a first input line connected with an input terminal of the voltage shift circuit, a second input line connected with an output terminal of the voltage shift circuit and a power voltage input line. Wherein, a P type first MOS tube and an N type second MOS tube are arranged between the first input line and the second input line in sequence. A source electrode of the first MOS tube is connected with the second input line. A source electrode of the second MOS tube is connected with the first input line. A grid of the first MOS tube and the second MOS tube is jointly connected with the power voltage input line. A drain electrode of the first MOS tube and the MOS tube is connected as an output terminal of a drive voltage. The first MOS tube is connected with a first current compensating circuit in parallel. The second MOS tube is connected with a second current compensating circuit in parallel. The present invention realizes drive voltage linear output in a range of 0-2VDD. Voltage resistance of each tube will not exceed a power voltage VDD.
Description
Technical field
The present invention relates to a kind of design of CMOS integrated circuit, being specifically related to a kind of driving voltage is the circuit structure of the drive circuit output stage of 0 to 2 times of supply voltage, can realize the linear relationship of input and output.
Background technology
In the prior art, common CMOS drive circuit is mainly used in the ability that drives load that improves, and improves drive current or the like.Wherein, for the driving of voltage, drive voltage range can realize that the circuit of raising of driving voltage is comparatively rare usually within 0-VDD.Charge pump construction is a kind of structure that can reach 2 times of supply voltages, and it has multiplication of voltage type and 2 kinds of basic circuits of back-pressure type, but it for 2 kinds of states, i.e. its output be high-low level, can not export the driving voltage between the high-low level.
In order to obtain higher output voltage, require the metal-oxide-semiconductor in the drive circuit to have higher puncture voltage usually, and then cause the difficulty in the cmos circuit design.
Chinese invention patent application CN1440124A discloses a kind of drive circuit, comprise level translation circuit (or claiming voltage translation circuit) and amplitude amplifying circuit, by the voltage translation, under the control of control circuit, can realize 2 times driving voltage output, and metal-oxide-semiconductor wherein can adopt the element than low breakdown voltage.Yet, this drive circuit that is used for PWM, its output be that voltage magnitude is 2 times a pulse signal, can not realize the continuous output of the driving voltage of 0-2VDD.
Therefore, can think that the circuit that will realize exporting continuously the driving voltage of 0-2VDD is very difficult, particularly for the design of the above-mentioned drive circuit that can be applied to the CMOS integrated circuit (IC) design, is the difficult point that this area faces.
Summary of the invention
The object of the invention provides a kind of drive circuit that can realize exporting continuously the driving voltage in the 0-2VDD scope, and wherein the operating voltage of the power switch component of Cai Yonging all is no more than supply voltage VDD.
For achieving the above object, the technical solution used in the present invention is: a kind of drive circuit, comprise voltage translation circuit and driving voltage output circuit, described driving voltage output circuit comprises, first incoming line that is connected with the input of voltage translation circuit, with second incoming line that the output of voltage translation circuit is connected, supply voltage incoming line; Between described first incoming line and second incoming line, be connected with first metal-oxide-semiconductor of P type and second metal-oxide-semiconductor of N type in turn, the source electrode of first metal-oxide-semiconductor connects second incoming line, the source electrode of second metal-oxide-semiconductor connects first incoming line, the grid of first metal-oxide-semiconductor and second metal-oxide-semiconductor is connected the supply voltage incoming line jointly, drain electrode is common to be connected, and as the driving voltage lead-out terminal; On described first metal-oxide-semiconductor, be parallel with first current compensation circuit, on described second metal-oxide-semiconductor, be parallel with second current compensation circuit.Described voltage translation circuit comprises the translation circuit power line that is equivalent to 2 times of supply voltages, five, the metal-oxide-semiconductor of the 6th, the 7th, the 84 P type, the source electrode of described the 5th metal-oxide-semiconductor connects translation circuit power line, drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor, the drain electrode of the 6th metal-oxide-semiconductor is connected with the source electrode of the 7th metal-oxide-semiconductor, the drain electrode of the 7th metal-oxide-semiconductor is connected with the source electrode of the 8th metal-oxide-semiconductor, the grounded drain of the 8th metal-oxide-semiconductor; Five, the grid of the 6th, the 73 metal-oxide-semiconductor is connected with drain electrode, constitutes the diode mode, and the grid of the 8th metal-oxide-semiconductor connects first incoming line; The source electrode of the drain electrode of the 5th metal-oxide-semiconductor and the 6th metal-oxide-semiconductor is connected second incoming line jointly, constitutes the output of translation circuit.
In the technique scheme, utilize the operating state of N type field effect transistor and P type field effect transistor conducting simultaneously, traditional reverser structure is improved, the grid input changes the source electrode input into, 2 source electrodes of N pipe and P pipe connect first input and second input respectively, the grid of 2 pipes meets supply voltage VDD, like this at the V that guarantees each pipe
DS, V
GSAll be no more than under the situation of supply voltage the driving voltage in the output 0-2VDD scope.Current compensation circuit can guarantee the linearity of outputting drive voltage.
In the technique scheme, described first current compensation circuit is the 3rd metal-oxide-semiconductor of P type, and the source electrode of the 3rd metal-oxide-semiconductor connects first incoming line, and grid and drain electrode are connected to lead-out terminal jointly; Described second current compensation circuit is the 4th metal-oxide-semiconductor of N type, and the source electrode of the 4th metal-oxide-semiconductor connects second incoming line, and grid and drain electrode are connected to lead-out terminal jointly.
In the technique scheme, the output voltage of described voltage translation circuit is suitable with described supply voltage with the difference of input voltage.
In the technique scheme, the purpose of described voltage translation circuit is to obtain second input voltage by the translation to first input voltage, can be called bootstrap circuit boost again.
Because the technique scheme utilization, the present invention compared with prior art has following advantage:
1. the present invention passes through the design to the syndeton of a pair of P type and N type metal-oxide-semiconductor, and with the cooperating of voltage translation circuit, realized the output of the driving voltage in the 0-2VDD scope, and the withstand voltage supply voltage VDD that is no more than of each pipe, thereby when being used for the cmos circuit design, can effectively improve area efficiency;
2. the driving voltage of the present invention's output can be followed input voltage, changes between 0 to 2VDD, by regulating the parameter of driving stage metal-oxide-semiconductor, can adjust the amplitude of oscillation and the slope of driving voltage arbitrarily.
3. owing to be provided with first and second current compensation circuits, guaranteed that driving voltage realizes that 0-2VDD scope in linearity exports.
Description of drawings
Accompanying drawing 1 is the circuit block diagram that the present invention executes example one;
Accompanying drawing 2 is structure principle charts of voltage translation circuit among the embodiment one;
Accompanying drawing 3 is structure principle charts of driving voltage output circuit among the embodiment one;
Accompanying drawing 4 is equivalent circuit diagrams of a kind of operating state among Fig. 3;
Accompanying drawing 5 is equivalent circuit diagrams of another kind of operating state among Fig. 3;
Accompanying drawing 6 is input, output situation schematic diagrames of the voltage translation circuit of embodiment one;
Accompanying drawing 7 is output resolution charts as a result of drive circuit among the embodiment one.
Embodiment
Below in conjunction with drawings and Examples the present invention is further described:
Embodiment one: shown in accompanying drawing 1, a kind of drive circuit is made of voltage translation circuit and driving voltage output circuit, and the input of entire circuit is the first incoming line Vin_L, and output is Vout.
As shown in Figure 2, the voltage translation circuit of present embodiment comprises the translation circuit power line VDDH that is equivalent to 2 times of supply voltage VDD, five, the metal-oxide-semiconductor of the 6th, the 7th, the 84 P type, the source electrode of described the 5th metal-oxide-semiconductor M5 connects translation circuit power line VDDH, drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor M6, the drain electrode of the 6th metal-oxide-semiconductor M6 is connected with the source electrode of the 7th metal-oxide-semiconductor M7, and the drain electrode of the 7th metal-oxide-semiconductor M7 is connected with the source electrode of the 8th metal-oxide-semiconductor M8, the grounded drain of the 8th metal-oxide-semiconductor M8; Five, the grid of the 6th, the 73 metal-oxide-semiconductor M5, M6, M7 is connected with drain electrode, formation diode mode, and the grid of the 8th metal-oxide-semiconductor M8 connects the first incoming line Vin_L; The drain electrode of the 5th MOS pipe M5 and the source electrode of the 6th metal-oxide-semiconductor M6 are connected the second incoming line Vin_H jointly, constitute the output of translation circuit.
This voltage translation circuit also can be described as bootstrap circuit boost, is used to produce the needed input value Vin_H of Fig. 3.
By adjusting the breadth length ratio of 4 pipes, can obtain suitable translation input voltage; The breadth length ratio of adjusting M5 and M8 can guarantee that translational movement equates under different situations.The value of VDDH is 2VDD, Figure 6 shows that the output voltage after input voltage and the lifting.
As shown in Figure 3, the driving voltage output circuit of present embodiment comprises, the first incoming line Vin_L that is connected with the input of voltage translation circuit is with the second incoming line Vin_H that the output of voltage translation circuit is connected, supply voltage incoming line VDD; Between described first incoming line and second incoming line, be connected with first metal-oxide-semiconductor M1 of P type and the second metal-oxide-semiconductor M2 of N type in turn, the source electrode of the first metal-oxide-semiconductor M1 connects the second incoming line Vin_H, the source electrode of the second metal-oxide-semiconductor M2 connects the first incoming line Vin_L, the grid of the first metal-oxide-semiconductor M1 and the second metal-oxide-semiconductor M2 is connected supply voltage incoming line VDD jointly, drain electrode is common to be connected, and as the driving voltage output terminal Vout; On the described first metal-oxide-semiconductor M1, be parallel with first current compensation circuit, on the described second metal-oxide-semiconductor M2, be parallel with second current compensation circuit.
In the present embodiment, described first current compensation circuit is the 3rd metal-oxide-semiconductor M3 of P type, and the source electrode of the 3rd metal-oxide-semiconductor M3 connects the second incoming line Vin_H, and grid and drain electrode are connected to output terminal Vout jointly, constitutes the diode mode and connects; Described second current compensation circuit is the 4th metal-oxide-semiconductor M4 of N type, and the source electrode of the 4th metal-oxide-semiconductor connects the first incoming line Vin_L, and grid is connected to output terminal Vout formation diode mode jointly with drain electrode and is connected.
Above-mentioned driving voltage output circuit, not only output voltage swing can reach 0-2VDD, and input and output are linear.
The foregoing circuit structure has guaranteed to have path between Vin_L and the Vin_H all the time, and passage current is constant, thereby makes Vout linear change with the change of Vin_L and Vin_H.Wherein, since the effect of voltage translation circuit, Vin_H=Vin_L+VDD.If two threshold voltages of metal-oxide-semiconductor are respectively VL and VH, the course of work of foregoing circuit is explained as follows:
1, when input 0≤Vin_L≤VL, effect through voltage translation circuit, VDD≤Vin_H≤VL+VDD, at this moment, M1 turn-offs, the M2 conducting, M3 and M2 form path, have constituted the amplifying circuit of linear zone, because the pressure drop on the M2 is very little, do not reach the unlatching threshold value of M4, its equivalent circuit diagram as shown in Figure 4.Along with the increase of Vin_L, output voltage V out increases, and the VGS of M2 reduces, and electric current reduces.
2, when input VL≤Vin_L≤VH, through the voltage translation, VDD+VL≤Vin_H≤VH+VDD, at this moment, and M1, M2 conducting simultaneously, M3, M4 guarantee passage current by way of compensation, because the compensating action of M3, M4, the linearity of output is guaranteed.
3, when input VH≤Vin_L≤VDD, through the voltage translation, VDD+VH≤Vin_H≤2VDD, at this moment, and the M1 conducting, M2 turn-offs, and M1 and M4 form path, and electric current is equal.Its equivalent circuit diagram as shown in Figure 5.
Figure 7 shows that the output result of this drive circuit.Here, the scope of Vin_L is 0-3.3v, and the scope of Vin_H is 3.3v-6.6v.
As can be seen from Figure 7, the circuit of present embodiment has obtained the linearity output in 0 to the 2VDD scope.
Claims (3)
1. drive circuit, comprise voltage translation circuit and driving voltage output circuit, it is characterized in that: described driving voltage output circuit comprises, first incoming line that is connected with the input of voltage translation circuit, second incoming line and the supply voltage incoming line that are connected with the output of voltage translation circuit; Between described first incoming line and second incoming line, connect first metal-oxide-semiconductor of P type and second metal-oxide-semiconductor of N type successively; The source electrode of described first metal-oxide-semiconductor connects described second incoming line, the source electrode of described second metal-oxide-semiconductor connects described first incoming line, the grid of described first metal-oxide-semiconductor and second metal-oxide-semiconductor is connected the supply voltage incoming line jointly, and the drain electrode of described first metal-oxide-semiconductor and second metal-oxide-semiconductor jointly is connected and as the driving voltage lead-out terminal; On described first metal-oxide-semiconductor, be parallel with first current compensation circuit, on described second metal-oxide-semiconductor, be parallel with second current compensation circuit;
Voltage translation circuit comprises the translation circuit power line VDDH that is equivalent to 2 times of supply voltage VDD, five, the metal-oxide-semiconductor of the 6th, the 7th, the 84 P type, the source electrode of described the 5th metal-oxide-semiconductor M5 connects translation circuit power line VDDH, drain electrode is connected with the source electrode of the 6th metal-oxide-semiconductor M6, the drain electrode of the 6th metal-oxide-semiconductor M6 is connected with the source electrode of the 7th metal-oxide-semiconductor M7, the drain electrode of the 7th metal-oxide-semiconductor M7 is connected with the source electrode of the 8th metal-oxide-semiconductor M8, the grounded drain of the 8th metal-oxide-semiconductor M8; The grid of metal-oxide-semiconductor is connected with drain electrode, the grid of the 6th metal-oxide-semiconductor is connected with drain electrode, the grid of the 7th metal-oxide-semiconductor is connected with drain electrode, constitutes the diode mode, and the grid of the 8th metal-oxide-semiconductor M8 connects the first incoming line Vin_L; The source electrode of the drain electrode of the 5th metal-oxide-semiconductor M5 and the 6th metal-oxide-semiconductor M6 is connected the second incoming line Vin_H jointly, constitutes the output of translation circuit.
2. drive circuit according to claim 1 is characterized in that: described first current compensation circuit is the 3rd metal-oxide-semiconductor of P type, and the source electrode of the 3rd metal-oxide-semiconductor connects second incoming line, and grid and drain electrode are connected to lead-out terminal jointly; Described second current compensation circuit is the 4th metal-oxide-semiconductor of N type, and the source electrode of the 4th metal-oxide-semiconductor connects first incoming line, and grid and drain electrode are connected to lead-out terminal jointly.
3. drive circuit according to claim 1 is characterized in that: the output voltage of described voltage translation circuit is suitable with described supply voltage with the difference of input voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100258032A CN101110584B (en) | 2007-08-01 | 2007-08-01 | Driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2007100258032A CN101110584B (en) | 2007-08-01 | 2007-08-01 | Driving circuit |
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| CN101110584A CN101110584A (en) | 2008-01-23 |
| CN101110584B true CN101110584B (en) | 2011-05-25 |
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| CN2007100258032A Expired - Fee Related CN101110584B (en) | 2007-08-01 | 2007-08-01 | Driving circuit |
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| CN103368383B (en) * | 2013-07-24 | 2015-09-02 | 苏州加古尔微电子科技有限公司 | For the ON-OFF control circuit of DC-DC boost converter |
| CN104579303B (en) * | 2013-10-12 | 2018-10-23 | 成都信息工程大学 | A kind of data driver with over-voltage protecting function |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208208B1 (en) * | 1998-04-20 | 2001-03-27 | Nec Corporation | Operationally amplifying method and operational amplifier |
| CN1440124A (en) * | 2002-02-20 | 2003-09-03 | 松下电器产业株式会社 | Driving circuit |
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- 2007-08-01 CN CN2007100258032A patent/CN101110584B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6208208B1 (en) * | 1998-04-20 | 2001-03-27 | Nec Corporation | Operationally amplifying method and operational amplifier |
| CN1440124A (en) * | 2002-02-20 | 2003-09-03 | 松下电器产业株式会社 | Driving circuit |
Non-Patent Citations (2)
| Title |
|---|
| 潘华兵,来新泉, 贾立刚.一种低电压高频率采用自举电路的BiCMOS驱动电路.世界电子元器件 3.2004,(3),65-67. |
| 潘华兵,来新泉, 贾立刚.一种低电压高频率采用自举电路的BiCMOS驱动电路.世界电子元器件 3.2004,(3),65-67. * |
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