CN101032084B - Method and apparatus used for receiver - Google Patents

Abstract

A satellite receiver comprises a front-end, demodulator and an LDPC decoder. The front-end receives a DVB-S2 LDPC coded signal and provides a down-converted signal to the demodulator. The latter demodulates the down-converted signal and provides a demodulated signal to the LDPC decoder. The LDPC decoder has a partially parallel architecture and partitions the bit node messages into N/360 groups and the check node messages into q groups, where q = M/360. Each group is processed by 360 bit node processors or 360 check node processors, respectively. Illustratively, the LDPC decoder includes a memory that is partitioned such that messages associated with bit node groups are consecutively addressed. Alternatively, the LDPC decoder includes a memory that is partitioned such that messages associated with check node groups are consecutively addressed.

Description

The method and apparatus that is used for receiver

Technical field

The present invention relates generally to communication system, and relate in particular to the receiver of a kind of processing low-density checksum (LDPC) coded data.

Background technology

In the last few years, the LDPC sign indicating number was because it had obtained near Shannon (Shannon) limit error correcting capability popularizing.For example, second generation digital video-frequency broadcast standard (DVB-S2) has adopted the LDPC sign indicating number as main error correcting code, replaces convolution code used in the first generation DVB standard (for example, to see the draft EN of ETSI (ETSI) 302307, v.1.1.1, (in June, 2004)).

Usually, (N, K) the LDPC sign indicating number is a parity check code, and wherein K is a figure place to be encoded, and N is the size (length) of gained encoding block, (N-K) is the additional error correction bits by this yard interpolation.Can be with matrix form will (N, K) the LDPC code table be shown following matrix equation Hx ^T=0 ^TThe set of separating x.This equation is also referred to as " parity check equation ", and wherein subscript T refers to the transposition of incidence matrices, and H is called as " parity matrix " of M * N dimension, and wherein as mentioned above, N is corresponding to the size of gained encoding block, and M=N-K.Modifier " low-density " is passed on following true: the part of the nonzero element in the parity check matrix H is very little, and particularly, linear with code block length N, and (opposite, " at random " linear block code is that 1 expection number is with N ²The sign indicating number that relation increases).

As this technical field known, also available two-dimensional plot is represented the LDPC sign indicating number, two-dimensional plot is used to understand the LDPC decode procedure.Under the environment of the parity check matrix H that M * N ties up, corresponding two-dimensional plot comprises N the node (be also referred to as variable node or information node) corresponding with the N row of parity matrix, and comprises the capable corresponding M check-node of M with this parity matrix.Each check-node all is connected to one or more nodes.Specifically, and if only if H _{M, n}=1, limit (or branch) is connected to variable node n with check-node m, wherein 0≤n＜N and 0≤m＜M.For two-dimensional plot, term " position node degree " is meant a number of the check-node that node was connected to.Similar, term " check-node degree " is meant the number of the position node that check-node is connected to.Also should observe, check-node degree and position node degree are also corresponding to 1 number in each row of parity check matrix H and each row.Forward Fig. 1 for the time being to, it shows illustrative parity matrix 5 and corresponding two-dimensional plot 6, wherein N=7 and M=3.Illustrative ground, position node x ₇A position node degree be 1, and check-node c ₃The check-node degree be 4.

As mentioned above, two-dimensional plot is used to understand the LDPC decode procedure. under this environment, in the LDPC decoder, check-node is associated with check node processor, and a node is associated with the position modal processor. unfortunately, though the decoding algorithm of LDPC decoder is conceptive simple, but for big code block or near at random parity matrix, the structure of LDPC decoder has caused a great enforcement difficult problem. for the enforcement of LDPC decoder, three kinds of known structures are arranged. first kind of structure is full parallel organization, all check-nodes wherein, yet position node and their connection all are mapped as hardware. this structure has produced the ultrahigh speed decoder., because high hardware complexity, this structure is unpractical for the decoding of the LDPC sign indicating number of long block length. second kind of structure is serial structure, wherein only implement a code check node processing unit (CPU) and node processing unit, a position (BPU), and they are repeatedly reused finish all decode operations. unfortunately, because all processing are all handled with serial mode, so serial structure has produced the Ultra-Low Speed decoder. last, the third structure is the part parallel structure, it is the compromise of first kind and second kind structure. at this, implement and reuse a plurality of BPU and a plurality of CPU, be actually in the LDPC hardware decoders complexity of expecting with between the decoding stand-by period and trade off. unfortunately, also there is not a kind of method for designing of unanimity of efficient realization part parallel LDPC decoder.

Summary of the invention

We observe, may reduce the complexity of LDPC decoder by some characteristic of utilizing the LDPC parity matrix, thereby design a kind of more efficient LDPC decoder with part parallel structure.Therefore, according to principle of the present invention, a kind of receiver is carried out the LDPC coding/decoding method that may further comprise the steps: receive the LDPC coded data; And the LDPC coded data of handling this reception, so that the data of decoding to be provided; Wherein this treatment step is divided into the Y group with the position node messages, and the verification node messages is divided into q group, wherein q changing with code check.

In an embodiment of the present invention, satellite receiver comprises front end, demodulator and LDPC decoder.This front end receives the DVB-S2LDPC encoded signals, and provides down signals to demodulator.This demodulator carries out demodulation to this down signals, and the signal that demodulation is provided is to the LDPC decoder.This LDPC decoder has the part parallel structure, and the position node messages is divided into the N/360 group, and the verification node messages is divided into q group, wherein q=M/360.Handle each group with 360 position modal processors or 360 check node processor respectively.Illustrative ground, this LDPC decoder comprises the memory of such division, so that the message related with the position groups of nodes is by addressing continuously.

In an embodiment of the present invention, satellite receiver comprises front end, demodulator and LDPC decoder.This front end receives the DVB-S2LDPC encoded signals, and provides down signals to demodulator.This demodulator carries out demodulation to this down signals, and the signal that demodulation is provided is to the LDPC decoder.This LDPC decoder has the part parallel structure, and the position node messages is divided into the N/360 group, and the verification node messages is divided into q group, wherein q=M/360.Handle each group with 360 position modal processors or 360 check node processor respectively.Illustrative ground, this LDPC decoder comprises the memory of such division, so that the message related with the check-node group is by addressing continuously.

Description of drawings

Fig. 1 shows parity matrix and the two-dimensional plot about the LDPC coding;

Fig. 2 shows table 1, and this table 1 shows some DVB-S2LDPC coding parameters;

Fig. 3-5 shows some the known observations about the DVB-S2LDPC parity matrix;

Fig. 6 shows table 2, and this table 2 further shows some observations about the DVB-S2LDPC coding;

Fig. 7-12 shows the reorganization of parity matrix in accordance with the principles of the present invention;

Figure 13 shows the part of the illustrative communication system of the concrete enforcement principle of the invention;

Figure 14 shows the illustrative embodiment of receiver in accordance with the principles of the present invention;

Figure 15 shows the illustrative embodiment of LDPC decoder in accordance with the principles of the present invention;

Figure 16 and 17 shows a kind of confession illustrative memory construction of the usefulness of LDPC decoder in accordance with the principles of the present invention;

Figure 18 shows in accordance with the principles of the present invention, the illustrative flow of the usefulness of the LDPC decoder of confession Figure 15;

Figure 19 shows about message transmission embodiment illustrated in fig. 15;

Figure 20 shows a kind of confession illustrative memory construction of the usefulness of LDPC decoder in accordance with the principles of the present invention;

Figure 21 shows the operation of the cyclic shifter of Figure 15;

Figure 22 shows a kind of illustrative code check node processing unit of usefulness of the LDPC decoder for Figure 15;

Figure 23 and 24 shows a kind of node processing unit, illustrative position of usefulness of the LDPC decoder for Figure 15;

Figure 25-28 shows another illustrative embodiment in accordance with the principles of the present invention; And

Figure 29 shows another illustrative embodiment in accordance with the principles of the present invention.

Embodiment

Except that notion of the present invention, the element shown in the figure all is well-known, and will not be described in detail.For example, except that notion of the present invention, satellite repeater, down link signal, symbol constellation, carrier wave recovery, interpolation, phase-locked loop (PLL), radio frequency (rf) front end or receiver part are as low-noise frequency transformer, be used to produce the format and the coding method (as Motion Picture Experts Group (MPEG)-2 system standard (ISO/IEC 13818-1), LDPC coding etc.) of transmission bit stream, and coding/decoding method such as log-likelihood ratio, soft inputting and soft output (SISO) decoder, Viterbi (Viterbi) decoder, all be well-known, not in this description.In addition, can utilize the conventional programming technology to implement notion of the present invention, thereby not in this description.And, suppose that the reader is familiar with satellite-based system (for example DVB-S2) and above-mentioned ETSI draft EN 302307, v.1.1.1, (in June, 2004), and not in this detailed description.At last, identical Reference numeral is represented similar element among the figure.

Before continuing to describe notion of the present invention, the prior art decoding algorithm of first brief review LDPC decoder.Should be noted that as this technical field known, the decoding algorithm of LDPC decoder is called as message pass-algorithm or belief propagation algorithm sometimes.Message pass-algorithm itself is as quite simple.Particularly, define one group of check-node M _n={ m:H _{M, n}=1} and one group of position node N _m={ n:H _{M, n}=1}.Make u _{M, n} ^(l)Be during the 1st iteration from put in place the message of node n of check-node m, make v _{N, m} ^(l)Be the message from position node n to check-node m during the 1st iteration, and make λ _n ^(l)Represent the estimation of the posteriority log-likelihood ratio (LLR) of n position after 1 iteration.If the channel observation of LDPC code block is expressed as vector r, then the message pass-algorithm is as follows.During initialization, below the calculating:

${\mathrm{\λ}}_n^{\left(0\right)}=\log \frac{\mathrm{Pr}\left(r\right|b_n=0)}{\mathrm{Pr}\left(r\right|b_n=1)}---\left(1\right)$

And, order

For all n ∈ 0 ..., N-1} and m ∈ M _n(2)

After the initialization, promptly for iteration l=1,2 ..., l _Max, following calculating is all carried out in an each check-node renewal and a position node updates.Upgrade for each check-node:

For m ∈ 0,1 ..., M-1} and n ∈ N _m, calculate

$u_{m,n}^{\left(l\right)}=\left(\underset{i\∈N_m-\left\{n\right\}}{\mathrm{\Π}}\mathrm{sign}\right\{v_{i,m}^{(l-1)}\left\}\right)f\left(\underset{i\∈N_m-\left\{n\right\}}{\mathrm{\Σ}}f\right(\left|v_{i,m}^{(l-1)}\right|)---\left(3\right)$

Wherein $f\left(x\right)=\log \frac{e^x+1}{e^x-1}$

And, for each position node updates:

For n ∈ 0,1 ..., N-1} and m ∈ M _n, calculate

${\mathrm{\λ}}_n^{\left(l\right)}={\mathrm{\λ}}_n^{\left(0\right)}+\underset{m\∈M_n}{\mathrm{\Σ}}{u}_{m,n}^{\left(l\right)}---\left(4\right)$

$v_{n,m}^{\left(l\right)}={\mathrm{\λ}}_n^{\left(l\right)}-u_{m,n}^{\left(l\right)}$

The hard decision of decoding algorithm is as follows with the termination criterion:

If

B then _n=0, otherwise b _n=1 (5)

Check bit sequence b wherein ₀, b ₁..., b _N-1Whether satisfy all parity check equations by the parity check matrix H definition.If satisfy, then iteration stops, otherwise makes l ← (l+1), and continues iteration, till reaching maximum iteration time.

As mentioned above, yet message pass-algorithm itself is quite simple., since between hardware constraints, LDPC code length and position node and the check-node near being connected at random, make that used LDPC sign indicating number has especially illustrated this point in the not necessarily simple .DVB-S2 satellite system of actual enforcement of LDPC decoder, yet will utilize this DVB-S2 satellite system that notion of the present invention is described., notion of the present invention is not therefore and limited, but can be applicable to the LDPC decoder of any kind, and no matter whether it is the part of satellite system.

In DVB-S2, four kinds of possible modulation schemes are arranged: quarternary phase-shift keying (QPSK) (QPSK), eight phase phase shift keyings (8-PSK), 16 amplitude phase shift keyings (16-APSK) and 32 amplitude phase shift keyings (32-APSK).Before modulation, utilize the serially concatenated code plan that data are encoded, wherein the LDPC sign indicating number is an ISN, and BCH (Bose-Chaudhuri-Hochquenghem) sign indicating number is outer sign indicating number.Except that the QPSK modulation, before modulation, also the LDPC codeword bit is interweaved.About cataloged procedure, BCH code is very weak sign indicating number, and it is used in LDPC decode procedure post-equalization residual error, so that realize 10 ^-7Packet-error-rate.About the LDPC coding, two types LDPC sign indicating number is arranged.First type is referred to herein as " normal LDPC sign indicating number ", and it has 64800 code block length.Second type is short LDPC sign indicating number, and it has 16200 code block length.Because this sign indicating number of two types has analog structure, so will describe normal LDPC sign indicating number at this.Only for simplicity and except as otherwise noted, subsequently any quoting of term " LDPC sign indicating number " all represented normal LDPC sign indicating number.Yet, in claims to the use of term " LDPC sign indicating number " not therefore and limited.

For DVB-S2 system (for example, see above-mentioned ETSI draft EN 302307, v.1.1.1, (in June, 2004)), multiple different available LDPC code check is arranged, shown in the table 1 of Fig. 2.What be labeled as " rate " in the table 1 first has listed these different LDPC code checks.Next column " K " has been listed under the sort of specific LDPC code check coded data amount in the LDPC encoding block.In the environment of DVB-S2 system, these data comprise the data of aforementioned Bose-Chaudhuri-Hocquenghem Code.For example, for 1/4 code check, uncoded data block has 16008 size (not shown in the table 1).Then, this uncoded data block being carried out Bose-Chaudhuri-Hocquenghem Code is 16200 the Bose-Chaudhuri-Hocquenghem Code piece corresponding K value of LDPC 1/4 code check (in the table 1 corresponding to).Then, under this specific code check, this Bose-Chaudhuri-Hocquenghem Code piece is carried out the LDPC coding.Because the LDPC code check is 1/4 in this example, so the size of gained LDPC encoding block is 68400 (not shown in the table 1).Should be noted that the data that comprised in the predefine part of corresponding receiver according to the DVB-S2 signal format that receives, determine code check.

As can be observed from table 1,11 kinds of possible code checks are arranged, in 1/4 to 9/10 scope, change.Yet as defined among the DVB-S2, the sign indicating number of different code checks has different parity matrixs.Thereby, can not obtain high rate codewords by puncturing (puncture) low rate codewords.Thereby big code block length and various code rate make the LDPC hardware decoders implement to become very complicated.

As previously mentioned, for the enforcement of LDPC decoder, three kinds of primary structures are arranged.Under the environment of DVB-S2, the LDPC code block length is 64800, and this is sizable.In addition, the DVB-S2 decoder requires the short stand-by period.Therefore, parallel entirely or serial structure is unsuitable for implementing decoder, and needs design part parallel structure.Yet, also do not have consistent method for designing to implement part parallel LDPC decoder efficiently.

For overcoming this difficulty, and, might reduce the complexity of LDPC decoder by some characteristic of utilizing the DVB-S2 parity matrix according to principle of the present invention.For abnormal LDPC code, the rule of an expectation is check-node degree (D _C) distribution even as far as possible.About the DVB-S2LDPC sign indicating number, can determine that for each related parity matrix first check-node that removes parity matrix has (D _C-1) beyond the check-node degree, each check-node all has identical check-node degree (D _C).Thereby the LDPC sign indicating number among the DVB-S2 is deferred to above-mentioned rule.

In addition, known all DVB-S2 parity matrixs all have [A/T] form, as shown in Figure 3.Matrix A is the rectangular matrix of M * K dimension, wherein M=N-K.Further show matrix A among Fig. 4.Should be noted that and matrix A itself can be regarded as by two sub-matrix A ₁And A ₂The parity matrix of forming, wherein A ₁Be the matrix of M * L dimension, A ₂It is the matrix of the dimension of M * (K-L).Matrix A ₁In the position node have identical position node degree, be expressed as DV ₁, same, matrix A ₂In the position node degree of position node also identical, and be fixed as DV ₂=3.Forward matrix T now to, this matrix is the lower triangular matrix that special M * M ties up, as shown in Figure 5.Such structure is sometimes referred to as hierarchic structure, for given degree distribute, a node degree is provided is 2 position node, i.e. DV for it ₃=2.In addition, should be noted that this lower triangular matrix enables quick LDPC coding (for example, see ETSI draft EN 302307, v.1.1.1, (in June, 2004)).

Forward Fig. 6 now to, table 2 shows above-mentioned L, the DV for different DVB-S2 code checks ₁, q and D _CValue.Two row that are marked as " rate " and " K " in the table 2 are identical with those row shown in the table 1 of Fig. 2.

According to principle of the present invention, the enforcement of LDPC decoder is shown clearlyer to the further analysis of matrix A structure.Particularly, for 360 position nodes of each group 360 * k ..., 360 * k+359} can be that (check-node of first of 360 * k) node is specified this group related check-node of node by index.For example, if first node in this group position node relates to one group of check-node { C ₁, C ₂..., C _DV, wherein DV is a node degree, then index for (360 * k+m) the position node relate to the following one group of check-node that provides:

Wherein $q=\frac{\mathrm{<figure-callout\; id="360"\; label="M"\; filenames="H2005800328231E00071.png,H2005800328231E00161.png"\; state="\{\{state\}\}">M</figure-callout>}}{360}.$

According to above-mentioned observation, and according to principle of the present invention, position node and every kind of node of check-node all are organized as many groups, so that execute bit node updates or check-node renewal operation simultaneously.About this special case, and shown in equation (6), per 360 position nodes 360 * k ..., and 360 * k+359} can be treated to one group, and promptly the contraposition node divides into groups continuously, as

For n ∈ 0,1 ..., (K/360)-1}, n position groups of nodes will comprise a node 360n, 360n+1 ..., 360n+358,360n+359}.

These nodes are also referred to as the system bits node at this.

About check-node, check-node by following be rearranged for q group (wherein, as mentioned above,

Be that q changes with code check):

Group 0:{0, q, 2 * q, 3 * q ..., 359 * q};

Group 1:{1,1+q, 1+2 * q, 1+3 * q ..., 1+359 * q}

…

Group q-2:{q-2, q-2+q ..., q-2+359 * q}; And

Group q-1:{q-1, q-1+q ..., q-1+359 * q}.

Because the size of LDPC encoding block is N=64,800, thus the following A matrix that will describe smaller szie, to further specify notion of the present invention.Fig. 7 shows the matrix 10 (matrix of A form) that reorganizes according to the principle of the invention.Matrix 10 is used to have the LDPC sign indicating number of following parameter:

N＝10X360＝3600；

M＝5X360＝1800；

q＝5；

DV ₁=4; And

L＝360。

Each square 11 is all represented 360 * 360 dimension submatrixs.Except that notion of the present invention, should note, symbol shown in Figure 7 in technical field be about similar code structure known (for example, see David J.C.Mackay, " the Comparison of Constructionsof Irregular Gallager Codes " of Simon T.Wilson and Matthew C.Davey, ieee communication journal (Transactions onCommunications), 47 volumes, the 1449-1454 page or leaf, in October, 1999; And D.Sridhara, T.Fuja and R.M.Tanner's " Low density parity check codes from permutationmatrices; " information, science and system of IMS conference (Conf.On Info.Sciences and Sys.), TheJohn Hopkins University, March calendar year 2001).Particularly, blank square is represented full null matrix, and the integer representative in the circle overlaps the quantity of circulating unit (identity) matrix on the square on every side in the square.The single circulating unit matrix that several 1 representatives have particular offset, and several 2 represent two circulating unit combinations of matrices.Further illustrate this point among Fig. 8 and 9.At first forward Fig. 8 to, the figure shows the different side-play amounts under the environment of circulating unit matrix that shifts left.Matrix 21 shows unit matrix.At this, this is also referred to as the nothing skew, is the circulating unit matrix of zero offset.In Fig. 8,, matrix 21 is shifted left once, produced matrix 22 from moving left to the right side.If the position of the element in the matrix 22 24 and it were before compared the position in matrix 21, then can observe, element 24 appears at same delegation, but to the row (in fact, making column wrap) that shifted left.Thereby matrix 22 is that side-play amount is 1 circulating unit matrix.Matrix 22 is shifted left once, produced matrix 23 now.Again, can observe from Fig. 8, element 24 from it before the position matrix 22 to the row that shifted left.Because matrix 23 is twice result that shift left, be 2 circulating unit matrix so matrix 23 is side-play amounts.Can obtain other side-play amount with similar mode, though and do not illustrate among Fig. 8, also can on other direction, equivalence carry out the dextroposition operation.For simplicity, be matrix I in this circulating unit matrix notation of will shifting left ^(y), wherein go up scale value and represent offset value.

With reference now to Fig. 9,, it shows the notion of combination circulating unit matrix.Combination circulating unit matrix is two or more circulating unit combinations of matrices.About Fig. 9, the figure shows two circulating unit combinations of matrices.Particularly, matrix 26 is the matrix 21 of Fig. 8 and 22 combination, and matrix 27 is the matrix 22 of Fig. 8 and 23 combination, and matrix 28 is the matrix 21 of Fig. 8 and 23 combination.Can obtain other combination with similar fashion.

According to more than, Figure 10 shows the matrix 10 (matrix of A form) of Fig. 7 once more, it shows the pattern of specific shift left circulating unit matrix and combination circulating unit matrix.If wired in the submatrix, then this corresponding submatrix element of representing line to cross has " 1 " value, and other submatrix element has " 0 " value.There is not the submatrix of line for the inside, complete zero submatrix of this representative.

As a result, can be observed by Fig. 7 and 10, for all LDPC sign indicating numbers, the A matrix of parity matrix comprises three types 360 * 360 dimension submatrixs:

-null matrix;

-circulating unit matrix I ^(y), for 0≤y≤359; And

-combination circulating unit matrix I ^(x)+ I ^(y), for x ≠ y and 0≤x, y≤359.

Now, there is another kind of mode to describe the LDPC parity matrix.Particularly, make H (m, n) the A matrix of the expression parity matrix corresponding, and only show non-zero submatrices with check-node group m and groups of nodes n.Capable (except that notion of the present invention for the n in the address of parity check bit accumulator table, at ETSI draft EN 302307, v.1.1.1, the address of parity check bit accumulator was described in (in June, 2004)), obtain the one group submatrix corresponding with n position groups of nodes.Give fixed number x for this table the n in capable, the corresponding check groups of nodes is m=x mould q, and the value of left cyclic shift number is And corresponding submatrix be H (m, n)=I ^(y)For example, by Fig. 6, for 1/2 code check, the q value equals 90, and by ETSI draft EN 302307, v.1.1.1, the appendix B in (in June, 2004), the 0th row (n=0) of the address of parity check bit accumulator table is:

54，9318，14392，27561，26909，10219，2534，8597。

(according to the nomenclature in the ETSI draft, the 0th row of the parity check bit accumulator table of 1/2 code check is corresponding to the row of the parity matrix of the zero bits node that " 1 " is arranged in row).

Therefore, the corresponding submatrix of A matrix is:

54：H(54，0)＝I ⁽⁰⁾；

9318：H(48，0)＝I ⁽¹⁰³⁾；

14392：H(82，0)＝I ⁽¹⁵⁹⁾；

27561：H(21，0)＝I ⁽³⁰⁶⁾；

26909：H(89，0)＝I ⁽²⁹⁸⁾；

10219：H(49，0)＝I ⁽¹¹³⁾；

2534:H (14,0)=I ⁽²⁸⁾And

9597：H(47，0)＝I ⁽⁹⁵⁾。

Equally, consider first row (n=1) (once more according to ETSI draft EN 302307, v.1.1.1, the appendix B in (in June, 2004)) of identical parity check bit accumulator table:

55，7263，4635，2530，28130，3033，23830，3651。

Therefore, the corresponding submatrix of A matrix is:

55：H(55，1)＝I ⁽⁰⁾；

3033，7263：H(63，1)＝I ⁽³³⁾+I ⁽⁸⁰⁾；

4635：H(45，1)＝I ⁽⁵¹⁾；

2530：H(10，1)＝I ⁽²⁸⁾；

28130：H(50，1)＝I ⁽³¹²⁾；

23830:H (70,1)=I ⁽²⁶⁴⁾And

3651：H(51，1)＝I ⁽⁴⁰⁾。

Should be noted that about 3033 of first row all to have produced identical submatrix H (63,1), but have different circulating unit matrix I respectively with 7263 calculating ⁽³³⁾And I ⁽⁸⁰⁾Therefore, submatrix H (63,1) is these two circulating unit matrix sums as implied above.

As previously mentioned, all DVB-S2 parity matrixs all have [A/T] form.According to principle of the present invention,, the position node in the matrix T is divided into groups to be different from the mode of matrix A meta node.For n ∈ (K/360) ..., (N/360)-1}, n position groups of nodes comprises with the next node:

K+(n-K/360)+{0，q，2×q，3×q，…，359×q}

The discontinuity of the parity check bit node in position groups of nodes is that the rearrangement by parity check equation causes.Figure 11 shows the example of gained T matrix.Can observe by Figure 11, three kinds of 360 * 360 possible dimension squares are arranged in the matrix T:

-null matrix;

-unit matrix I ⁽⁰⁾And

-comprise the square H (0, (N/360)-1) of the specific submatrix of 360 * 360 dimensions shown in Figure 12.

Now, utilize rearranging of above-mentioned parity matrix, implementing LDPC decoder in accordance with the principles of the present invention. Figure 13 shows the illustrative part of communication system in accordance with the principles of the present invention. as can be observed from Figure 13, signal 104 is received device 105 and receives. and signal 104 transmits representative control signaling, the information of content (for example video) etc. under the environment of this example, DVB-S2 down link satellite-signal after putative signal 104 representatives are received by the antenna (not shown). receiver 105 comes processing signals 104 according to principle of the present invention (following), and signal 106 is provided, show with the multimedia terminal that certain content is sent to as television set (TV) 90 representatives.

Forward Figure 14 now to, it shows the illustrative part of receiver 105 in accordance with the principles of the present invention.Receiver 105 comprises front end filter 110, modulus (A/D) transducer 115, demodulator 120, LDPC decoder 125 and BCH decoder 135.The signal 104 of 110 pairs of receptions of front end filter is carried out down-conversion (for example from the satellite transmits band) and filtering, to provide near baseband signal to A/D converter 115,115 pairs of these down signals of A/D converter are sampled, so that to numeric field, and provide signal 116 as sample sequence this conversion of signals to demodulator 120.120 pairs of signals of demodulator 116 are carried out demodulation (comprising that carrier wave recovers), and the signal 121 that demodulation is provided is to LDPC decoder 125, LDPC decoder 125 principle according to the present invention is decoded to the stream of signal points 121 of this demodulation, so that the signal 126 of representing Bose-Chaudhuri-Hocquenghem Code signal or data flow to be provided.Signal 126 is applied to BCH decoder 135, to recover the transmission data represented as signal 136.At least some data of signal 136 finally are provided (not shown among Figure 14) by signal 106 and give TV 90.(in this, receiver 105 can be before data be applied to TV90 deal with data in addition, and/or directly provide data to TV 90).

According to principle of the present invention, Figure 15 shows the illustrative embodiment of LDPC decoder 125.LDPC decoder 125 comprises: log-likelihood ratio (LLR) computing element 205, LLR buffer 210, multiplexer (mux) 215, limit (edge) memory 220, cyclic shifter 225 and 235, a plurality of code check node processing unit (group CPU handles) 230, a plurality of node processing unit (group BPU handles) 240, iteration stop decision element 245 and controller 290.The controlled processors (for example microprocessor and associative storage) of program or state machine etc. have been stored in controller 290 representative.

The stream of signal points signal 121 of LLR computing element 205 receiving demodulations, and calculate LLR as this technical field is known is to provide the signal 206 of the LLR value that representative calculated, the LDPC encoding block that the LLR value of being calculated representative receives.Particularly, LLR computing element 205 comes the LLR of compute codeword position to be based on the signal to noise ratio of modulation scheme and received signal

For for simplicity, utilize the look-up table (not shown) to realize this function.In addition, before the LLR value being sent to LLR buffer 210 via signal 206, LLR computing element 205 also to the LLR value carry out deinterleaving (as previously mentioned, unless use the QPSK modulation, otherwise before modulation, the LDPC coding stream is interweaved).LLR buffer 210 is memory elements, and comprises for example double buffering structure, so that alternately store the data of representing the LDPC encoding block that is received.Thereby, when a buffer is full of, handle via the data of signal 211, so that LDPC decode encoded blocks to before having received from another buffer.Figure 16 shows a kind of illustrative memory construction 315 of usefulness of LLR buffer of the system bits node for matrix A; And Figure 17 shows a kind of illustrative memory construction 320 of usefulness of LLR buffer of the position node for matrix T.By Figure 16 and 17, required storage number of words is N/360=64800/360=180, if suppose that wherein needing 6 comes storing initial channel information (λ _n ⁽⁰⁾), then the bit wide of a memory word is 360 * 6=2160 position.Thereby LLR buffer 210 provides the LDPC encoding block to multiplexer 215 via signal 211.Multiplexer 215 is subjected to the control as the represented processor of controller 290, and each element of these controller 290 control LDPC decoders 125 is for representing with empty arrow for simplicity.Multiplexer 215 provide following three types of data via signal 216 any to limit memory 220; The LDPC encoding block to be decoded (via signal 211) that receives; Position node processing data (via signal 241); Or code check node processing data (via signal 236).

Now should be with reference to Figure 18, the figure shows illustrative flow in the LDPC decoder 125 employed overall processes that are used for carrying out the LDPC decoding. in step 405, provide the LDPC encoding block to limit memory 220 from LLR buffer 210, to be stored in the limit memory 220. in step 410 and 415, carry out the LDPC decoding. particularly, the data of storage are carried out check-node renewal (step 410) and position node updates (step 415) (following) in the opposite side memory 220. in step 420, for example whether should stop decode procedure if check by above equation (5). process is terminated, then carry out and turn back to step 405, begin next LDPC decode encoded blocks, otherwise continuing to carry out the decoding that another takes turns check-node and position node updates by step 410 and 415. should note, for for simplicity, error condition is not shown in the flow chart of Figure 18.

As mentioned above, limit memory 220 storage LDPC coded datas, and in check-node renewal shown in Figure 180 and position node updates step, all visit limit memory 220.Limit memory 220 is represented memory element.Allow the register of fast access (though having higher design complexity) to realize limit memory 220 though can utilize, the length of given LDPC encoding block, preferably memory bank is the realization that is more suitable for.In the LDPC decode procedure, message is by transmitting between the limit of two-dimensional plot node on the throne and the check-node.Figure 19 in conceptual illustration this point, the figure shows the part of illustrative two-dimensional plot.For example, position node n is connected to check-node m by limit 40, and the message transmission between limit 40 enable bit node n and the check-node m is represented as position node messages 41 and check-node message 42.Because the frontier juncture connection between memory that uses in the LDPC decode procedure and check-node and the position node is so this memory is referred to herein as the limit memory.Thereby, limit memory 220 storage via signal 236 from put in place the message { u of node of check-node _{M, n} ^(l), or via the message { v of signal 241 from the position node to check-node _{N, m} ^(l).Particularly, and as can be observed from the flow chart of Figure 18, LDPC decoder 125 has at least two stages; Check-node update stage (for example step 410 of Figure 18) and position node updates stage (for example step 415 of Figure 18).Begin { v in the check-node update stage _{N, m} ^(l-1)Be stored in the memory location of limit memory 220; And at the ending of check-node update stage, { u _{M, n} ^(l)Calculated and be stored in identical memory location.Equally, in the node updates stage on the throne, read { u _{M, n} ^(l)And calculate { v _{N, m} ^(l), and be stored to identical memory location.Thereby, in the part parallel structure, depend on the stage of LDPC decoder, utilize identical memory location to store { v _{N, m} ^(l)Or { u _{M, n} ^(l).

According to principle of the present invention, can organize limit memory 220 according to position node or check-node according to the reorganization of above-mentioned parity matrix.Should be noted that required total storage capacity is identical for both of these case, because for specific parity matrix, the limit number is fixed.

In one embodiment, organize limit memory 220 according to the position node with coming illustrative.In this case, utilize a memory word to store all message corresponding with cyclic shift unit matrix (above-mentioned).The memory word related with the position groups of nodes is stored in the continuation address position, and this makes a node updates become simple.Figure 20 shows a kind of illustrative memory construction 325 that supplies the usefulness of limit memory 220.Because the memory of limit memory 220 is according to the position node organization, this memory also can be described as a node storage.

Turn back to Figure 15, the data of storage are provided for a node processing path or code check node processing path via signal 221 in the limit memory 220.About the code check node processing path, this path is in check-node update stage work (step 410 of Figure 18).Particularly, data (no matter being initial LDPC coded data or message data subsequently) { v _{N, m} ^(l-1)Be provided for group CPU processing 230 via cyclic shifter 225.Because limit memory 220 is according to the position node organization, thus the data in the cyclic shifter 225 cyclic shift memory words, so that the data of a check-node group are aligned.This point has been described among Figure 21, has the figure shows the cyclic shift amount of 0/ groups of nodes 0 of check-node group.Group CPU handles 230 and comprises 360 code check node processing unit (below further describe), is used for calculating { u _{M, n} ^(l)And { u is provided _{M, n} ^(l)Give cyclic shifter 235, cyclic shifter 235 is redirected the data in the memory word once more, so that the data of a position groups of nodes are aligned.Cyclic shifter 235 provides { u by signal 236 via multiplexer 215 and signal 216 _{M, n} ^(l)To limit memory 220.Should be noted that can be multiplexing by in time domain the operation of cyclic shifter being carried out, and uses a cyclic shifter to replace two.Forward a node processing path now to, this path node updates stage on the throne work (step 415 of Figure 18).Particularly, data { u _{M, n} ^(l)Be provided for and organize BPU processing 240.Group BPU handles 240 illustratives ground and comprises node processing unit, 360 positions (below further describe), is used for calculating { v _{N, m} ^(l), and by signal 241, provide { v via multiplexer 215 and signal 216 _{N, m} ^(l)To limit memory 220.

As mentioned above, group CPU processing 230 comprises 360 code check node processing unit.Figure 22 shows illustrative code check node processing unit (CPU) 230-J, wherein 0＜J≤360.CPU 230-J handles one group of input message

So that the output message of one group of correspondence to be provided

As previously mentioned, in the LDPC decoding, utilize equation (3) to produce this group output message.Yet if the accurate formula in the realization equation (3), the complexity of each code check node processing unit will increase.Really, because the check-node degree of maximum possible is 30, so even can realize function f () by simple lookup, the realization of adder array and all function f () also will become very complicated.In order to reduce the complexity of code check node processing unit, CPU 230-J implements following method.Particularly, suppose Be one group of input message of code check node processing unit (CPU).Then calculate

s _k＝sign(e _k) (7)

$S=\underset{k=0}{\overset{D_C-1}{\mathrm{\&Pi;}}}{s}_k---\left(8\right)$

Now, select this group input message

In 3 minimum values, and to make their manipulative indexing be m ₀, m ₁, m ₂After this, calculate following four values:

${\mathrm{\&lambda;}}_0=g\left(\right|e_{m_1}|,|e_{m_2}\left|\right),---\left(9\right)$

${\mathrm{\&lambda;}}_1=g\left(\right|e_{m_0}|,|e_{m_2}\left|\right),---\left(10\right)$

${\mathrm{\&lambda;}}_2=g\left(\right|e_{m_0}|,|e_{m_1}\left|\right),---\left(11\right)$

${\mathrm{\&lambda;}}_3=g(g\left(\right|e_{m_0}|,|e_{m_1}\left|\right),|e_{m_2}\left|\right)---\left(12\right)$

Wherein

$g(x,y)\&cong;\mathrm{sign}\left(x\right)\mathrm{sign}\left(y\right)\{\min \left(\right|x|,|y\left|\right)-h\left(\right|\left|x\right|-\left|y\right|\left|\right)\}---\left(13\right)$

h(x)＝1n(1+e ^-x) (14)

Then, one group of output message of following calculating

$e_k^{\&prime;}=s_k\&times;S\&times;\left\{\begin{array}{c}{\mathrm{\&lambda;}}_0,\mathrm{fork}={\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="H2005800328231E00011.png,H2005800328231E00121.png"\; state="\{\{state\}\}">m</figure-callout>}}_0\\ {\mathrm{\&lambda;}}_1,\mathrm{fork}={\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="H2005800328231E00011.png,H2005800328231E00051.png"\; state="\{\{state\}\}">m</figure-callout>}}_1\\ {\mathrm{\&lambda;}}_2,\mathrm{fork}={\mathrm{<figure-callout\; id="2"\; label="m"\; filenames="H2005800328231E00071.png,H2005800328231E00161.png"\; state="\{\{state\}\}">m</figure-callout>}}_2\\ {\mathrm{\&lambda;}}_3,\mathrm{fork}\&NotEqual;{\mathrm{<figure-callout\; id="0"\; label="m"\; filenames="H2005800328231E00011.png,H2005800328231E00121.png"\; state="\{\{state\}\}">m</figure-callout>}}_0,{\mathrm{<figure-callout\; id="1"\; label="m"\; filenames="H2005800328231E00011.png,H2005800328231E00051.png"\; state="\{\{state\}\}">m</figure-callout>}}_1,m_2\end{array}\right.---\left(15\right)$

0＜k≤D wherein _C-1.In said method, only utilize three minimum values importing in the message to calculate the output message of CPU.Simulation demonstrates, because the performance loss that should approximate cause can be ignored for all the LDPC sign indicating numbers among the DVB-S2.

Forward a node processing now to, group BPU handles 240 and comprises node processing unit, 360 positions.Figure 23 shows node processing unit, illustrative position (BPU) 240-I, wherein 0＜I≤360.BPU 240-I handles one group of input message { e ₀, e ₁..., e _DV-1, with output message that one group of correspondence is provided e ' ₀, e ' ₁..., e ' _DV-1.Position node processing operation is quite simple, and in Figure 24 it is further specified.In Figure 24, term LLR is provided by the log-likelihood ratio of the position node of the association that provides from LLR buffer 210 by signal 211.

The last element of LDPC decoder 125 is that the iteration of implementing the above-mentioned steps 420 of Figure 18 stops decision element 245. as can be from Figure 15 and 23 observed, signal 242 is provided for iteration and stops decision element 245 from node processing path, position, for its use. if the LDPC decoding is terminated, and then the data of the LDPC of gained decoding are provided for above-mentioned BCH decoder 135. iteration termination decision element 245 via signal 126 provides about continuing the LDPC decode procedure or beginning new to controller 290, the signaling (not shown) of the LDPC decode procedure of for example next LDPC encoding block.

As previously mentioned, DVB-S2 supports multiple code check with predefine parity matrix, and the data that comprised in the predefine part of receiver according to the DVB-S2 signal format of receiving, determines code check.Under this environment, controller 290 utilizes the modulation type of determining, selects different look-up table (not shown) for aforementioned LLR calculates, and selects different interleaving scheme (as defined among the DVB-S2).Controller 290 principle also according to the present invention disposes LDPC decoder 125, so that according to the parity matrix according to the aforementioned principles tissue, handles the LDPC encoded signals that is received with different code checks.For example, can above-mentioned submatrix be calculated (H (m, n)) is stored in the memory (for example config memory 295 of Figure 15), so that be used for subsequently for the different parameters shown in the table 2 of Fig. 6, and the LDPC coded data that processing receives. in advance

Figure 25 shows another illustrative embodiment of LDPC decoder 125.Except limit memory 220 according to check-node tissue (and also can be described as the check-node memory bank), this configuration is similar to configuration shown in Figure 15, and work in a similar fashion (for example seeing Figure 18,22,23 and 24).Thereby, two cyclic shifter 225 and 235 be positioned at now group BPU handle 240 before and afterwards.Should be noted that by the operation of cyclic shifter being carried out simply multiplexingly again, can use a cyclic shifter to replace two in time domain.

About organize limit memory 220 according to check-node, be brought together with a check-node group corresponding check node memory, and use for example memory word of a memory location, store all message corresponding with the particular cycle unit matrix.In other words, all message that the memory word storage sends by the limit related with the particular cycle unit matrix.As the observed, and shown in the table 2 of Fig. 6, for the LDPC sign indicating number, remove the 0th check-node and have check-node degree (D _C-1) the degree D of all check-nodes in addition, _cAll identical.The following example that uses 1/2 code rate LDPC code is considered on illustrative ground, wherein by the table 2 of Fig. 6, and D _C=7, and the 63rd check-node group is corresponding to following square formation as submatrix in the parity matrix (calculating as previously mentioned):

H(63，1)＝I ⁽³³⁾+I ⁽⁸⁰⁾；

H(63，9)＝I ⁽⁰⁾；

H(63，29)＝I ⁽³²⁴⁾；

H(63，34)＝I ⁽¹³²⁾；

H (63,62)=I ⁽⁰⁾And

H(63，63)＝I ⁽⁰⁾。

Figure 26 shows the illustrative memory bank 305 in the limit memory corresponding with the 63rd check-node group 220.If regard each provisional capital of memory bank 305 as single memory word, then as shown in the figure, the check-node group only needs D _C=7 memory words.Really, all memory banks of all check-nodes all can be put together then, and with the linear mode addressing.Figure 27 shows this illustrative memory construction 310 of limit memory 220.The address space of the limit memory 220 of memory construction 310 be 0,1,2 ..., qD _C-1}.In other words, the size of this address space is (qxD _C).The table 3 of Figure 28 shows for the required memory space of Different L DPC code check.As can be observed from table 3, required maximum storage number of words be 792.If supposing each node messages or check-node message once more is 6 bit wides, then the bit wide of memory word is 360 * 6=2160 position.

Figure 29 shows another illustrative embodiment of notion of the present invention.In this illustrative embodiment, supply the integrated circuit (IC) 705 of the usefulness of receiver (not shown) to comprise LDPC decoder 720 and at least one register 710, this register 710 is connected to bus 751.Illustrative ground, however IC 705 is integrated demodulator/decoder., only show those parts with the IC 705 of conceptual dependency of the present invention.For example, for for simplicity, analog to digital converter, filter, decoder etc. are not shown.Bus 751 provides and as the dealing communication between other parts of the represented receiver of processor 750.Register 710 is represented one or more registers of IC 705, and wherein each register all comprises as represented one or more in position 709, is used for the operation of control IC 705.The register of IC 705 or portions of registers can be read-only, only write or read/writable.LDPC decoder 720 is connected to register 710 via internal bus 711, and this internal bus 711 is represented other signal path and/or the parts of IC 705, be used for LDPC decoder 720 is docked with register 710, as this technical field known.According to principle of the present invention, LDPC decoder 720 comprises above-mentioned group of CPU and group BPU.Under the environment of Figure 14, IC 705 receives IF signal 701 (for example signals 116 of Figure 14) so that handle via input pin or the lead-in wire of IC 705.The derivative 702 of this signal is applied to LDPC decoder 720, so that according to aforesaid principle of the present invention (for example Figure 15 and 24) it is carried out the LDPC decoding.LDPC decoder 720 provides the signal 721 as the bit stream of LDPC decoding.IC705 provides the one or more restored signals represented as signal 706.For example, signal 706 representatives are from the signal 136 of the BCH decoder (not shown) of IC 705.In the another kind of modification of IC 705, signal 706 is represented the signal 106 of Figure 13.

As mentioned above, and according to principle of the present invention, describe and shown a kind of LDPC decoder that can handle multiple different code checks.And, should be noted that and the equivalence of above-mentioned cyclic shift unit matrix can be generalized to permutation matrix.In this case, replace above-mentioned cyclic shifter with permutation network.

In view of more than, though should be noted that described notion of the present invention under the environment of satellite communication system, notion of the present invention is not therefore and limited.For example, the element of Figure 13 can be represented the multimedia terminal of system He other form of other type, for example satelline radio, terrestrial broadcasting, cable TV etc.And, though under this environment, be described at single demodulator, but should be realized that notion of the present invention can be applicable to wherein can transmit at the unlike signal layer many modulator receivers of information, for example hierarchical modulation receiver, hierarchical modulation receiver or their combination etc.Certainly, the present invention can be applicable to wherein to carry out the receiver of any kind of LDPC decoding.Thereby notion of the present invention is not limited to the decoding of DVB-S2LDPC sign indicating number.

Thereby foregoing description has only illustrated principle of the present invention, thereby should be appreciated that, though those skilled in the art can design many clearly the description at this, and concrete enforcement principle of the present invention, and the configuration of the replacement in spirit and scope of the invention.For example, though under the environment of the function element of separating, be illustrated, can go up concrete these function element of implementing at one or more integrated circuits (IC).Similar, though be shown as the element of separation, but can be in the controlled processors that has program stored therein, as for example carry out with the digital signal processor (DSP) of the corresponding associated software of one or more elements of element shown in Figure 14,15 and/or 24 or microprocessor etc. in, implement any or all element.In addition, though be shown as the element of separation, element wherein can be distributed in the different units with any compound mode.For example, receiver 105 can be the part of TV 90, and perhaps receiver 105 can be positioned at the more upstream of compartment system, for example is positioned at head end, so content can be retransmitted other node and/or receiver to network.Therefore, should be appreciated that, under situation about not breaking away from, can carry out many modifications to illustrative embodiment, and can design other configuration as the defined spirit and scope of the invention of claims.

Claims (12)

1. method that is used for receiver, described method comprises:

Receive low-density checksum (LDPC) coded data; And

Utilize check-node message and position node messages to handle the data of the low-density checksum coding of described reception, so that the data of decoding to be provided;

Data represented (N, K) low density parity check code, the wherein M=N-K of the low-density checksum coding of wherein said reception with M * N dimension parity matrix; And

It is characterized in that described treatment step reorganizes parity matrix and makes that forming Y organizes position node and q group check-node, wherein q=Y (N-K)/N, and its feature also is the treating step comprises:

Handle each group check-node message with J processor; And

Handle each group position node messages with J processor;

J=N/Y wherein; And

Described check-node message and institute's rheme node messages are stored in the memory of limit.

2. method according to claim 1, the data of the low-density checksum coding of wherein said reception are to obtain from digital video broadcast system-2 signal that receives.

3. method according to claim 1, wherein Y=N/360.

4. method according to claim 1, the step of wherein said processing check-node message may further comprise the steps:

Each group check-node message is carried out cyclic shift;

Handle the check-node message that each organizes cyclic shift with J processor, so that one group of new information to be provided; And

Each group new information is carried out cyclic shift, to form one group of position node messages.

5. method according to claim 1, the step of wherein said processing position node messages may further comprise the steps:

Each group position node messages is carried out cyclic shift;

Handle the position node messages that each organizes cyclic shift with J processor, so that one group of new information to be provided; And

Each group new information is carried out cyclic shift, to form one group of check-node message.

6. equipment that is used for receiver, described equipment comprises:

Demodulator provides the data of low-density checksum coding;

Low-density parity-check decoder is decoded to the data of described low-density checksum coding, so that the data of decoding to be provided;

Data represented (N, K) low density parity check code, the wherein M=N-K of described low-density checksum coding with M * N dimension parity matrix;

Wherein said low-density parity-check decoder is handled the data of described low-density checksum coding, wherein q=Y (N-K)/N by the position node messages being divided into the Y group and the verification node messages being divided into the q group; And described low-density parity-check decoder also comprises:

Be used to handle J processor of each group position node messages; And

Be used to handle J processor of each group check-node message;

J=N/Y wherein;

The limit memory, wherein, the described check-node message of described limit memory stores and institute's rheme node messages; And

Be used to dispose the config memory of described low-density parity-check decoder, be used for handling the data of the low-density checksum coding that is received with different code checks.

7. equipment according to claim 6, the data of wherein said low-density checksum coding are to obtain from digital video broadcast system-2 signal that receives.

8. equipment according to claim 6, wherein Y=N/360.

9. equipment according to claim 6, wherein said low-density parity-check decoder comprises:

Be used for cyclic shifter that described check-node message is shifted;

One group of position modal processor is handled the check-node message of described cyclic shift, so that new information to be provided;

Be used for described new information is shifted, to form the cyclic shifter of new position node messages; And

One group of check node processor is handled institute's rheme node messages new check-node message is provided, so that be stored in the memory of described limit;

The formation of wherein said limit memory makes that described new position node messages is stored continuously.

10. equipment according to claim 6, wherein said low-density parity-check decoder comprises:

One group of position modal processor is handled described check-node message new position node messages is provided, so that be stored in the memory of described limit;

Be used for cyclic shifter that institute's rheme node messages is shifted;

One group of check node processor is handled the position node messages of described cyclic shift, so that new information to be provided; And

Be used for described new information is shifted, to form the cyclic shifter of new check-node message;

The formation of wherein said limit memory makes that described new check-node message is stored continuously.

11. equipment according to claim 6, the formation of wherein said limit memory make that many groups position node messages is stored continuously.

12. equipment according to claim 6, the formation of wherein said limit memory make that many group check-node message are stored continuously.

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