CN101010796A - Semiconductor device and method of manufacturing such a semiconductor device - Google Patents
Semiconductor device and method of manufacturing such a semiconductor device Download PDFInfo
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- CN101010796A CN101010796A CN 200580028224 CN200580028224A CN101010796A CN 101010796 A CN101010796 A CN 101010796A CN 200580028224 CN200580028224 CN 200580028224 CN 200580028224 A CN200580028224 A CN 200580028224A CN 101010796 A CN101010796 A CN 101010796A
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Abstract
The invention relates to a CMOS device (10) with an NMOST 1 and PMOST 2 having gate regions (1D,2D) comprising respectively first and second conducting materials of a compound containing both a metal and a further element. According to the invention the first and second conducting material both comprise a compound containing as the metal a metal selected from the group comprising molybdenum and tungsten and the first conducting material comprises oxygen as the further element and the second conducting material comprise a chalcogenide as the further element. The invention also provides an attractive method of manufacturing such a device.
Description
Technical field
The present invention relates to a kind of semiconductor device with substrate and semiconductor body, described semiconductor body comprises first field-effect transistor and second field-effect transistor, and described first field-effect transistor has: first source area; First drain region; First raceway groove of the first electric conductivity type; And by first dielectric region and first raceway groove first grid polar region isolated, that comprise first electric conducting material, and described second field-effect transistor has: second source area; Second drain region; Second raceway groove of the second electric conductivity type opposite with the first electric conductivity type; And by second dielectric region and second raceway groove second grid district isolated, that comprise second electric conducting material different with first electric conducting material, wherein, described first and second electric conducting materials comprise the compound that contains metal and another element.In advanced CMOS (complementary metal oxide semiconductors (CMOS)) device that is lower than inferior 0.1 micron zone, expect to utilize metal gates or its alloy to replace polysilicon gate for a variety of reasons.The invention still further relates to the manufacture method of this device.
Background technology
Learn the device of in the introductory song paragraph, mentioning from October 10th, 2000 in the laid-open U.S. Patents 6,130,123.Wherein, described multiple electric conducting material, they are applicable among the NMOST (N type MOS transistor) and PMOST in the cmos device.The example that is suitable for being used in the metal or metal alloy among the NMOST is Ru, Zr, Nb, Ta, MoSi and TaSi, and their work function is 4.2eV.For PMOST, suitable material is Ni, RuO2, MoN and TaN, and they have the work function of about 5.2eV.
The shortcoming of known electric conducting material is: they are always not compatible well with existing IC technology.Compatibility comprises following requirement: this material should with the material compatibility of gate stack, wherein, the material of gate stack comprises the material of gate dielectric layer, cover layer and wall.
Summary of the invention
Therefore, the objective of the invention is to avoid above-mentioned shortcoming and the device that a kind of and IC technical compatibility are good and be easy to make is provided.
In order to realize purpose of the present invention, a kind of device of the type of mentioning in the introductory song paragraph has been proposed, it is characterized in that: first and second electric conducting materials include the compound that contains metal, and described metal is selected from the group that comprises molybdenum and tungsten; And second electric conducting material comprise oxygen as another element, and first electric conducting material comprises the chalcogen as another element.Described chalcogen comprises element S, Se and Te.On the one hand, described material comprises very common metal in the current I C technology, for example is used for conductive path and is used in particular for connection between the conductive path on the different brackets.On the other hand, some advantages are provided according to another element in the device of the present invention.At first, described another element allows two relevant work functions in the cmos device (that is, being respectively 5.2eV and 4.1eV) are carried out good covering.In addition, on the one hand the molybdenum in tungsten and the oxygen on the other hand similar with chalcogen (elements of all VI row) behavior, and all these elements can both be compatible well with current IC technology.Especially, if use the method according to this invention to make described compound, will keep a back advantage.
In a preferred embodiment, select molybdenum as metal and select tellurium as chalcogen.Use these elements to obtain good result.When Te was injected molybdenum film, therefore the work function of the material that is generated was very suitable for being used among the NMOST very near 4.1eV.Be designated as down 2 or the work function of the littler material that molybdenum oxide generated very near 5.2, therefore be very suitable for being used among the PMOST.Therefore, preferred metallic element is a molybdenum.
Preferably, first and second gate regions are included in the zone that is formed by another material on first and second electric conducting materials, and conduct electricity in this zone, and with the barrier of doing silicon.Preferably, described another material comprises the metal nitride that is similar to titanium nitride.Also can use other metal nitride that is similar to tantalum nitride.This has improved the manufacturing efficient of described device.
A kind of manufacture method of semiconductor device according to the invention, described semiconductor device has substrate and semiconductor body, described semiconductor body comprises first field-effect transistor and second field-effect transistor, and described first field-effect transistor has: first source area; First drain region; First raceway groove of the first electric conductivity type; And by first dielectric region and first raceway groove first grid polar region isolated, that comprise first electric conducting material; Described second field-effect transistor has: second source area; Second drain region; Second raceway groove of the second electric conductivity type opposite with the first electric conductivity type; And by second dielectric region and second raceway groove second grid district isolated, that comprise second electric conducting material different with first electric conducting material, wherein, selection comprises that the compound that contains metal and another element is used for first and second electric conducting materials, described method is characterised in that: the material of selecting to include the compound that contains metal is used for first and second electric conducting materials, and described metal is selected from the group that comprises molybdenum and tungsten; And selection oxygen is as another element of second electric conducting material; And for selecting chalcogen another element as first electric conducting material.By this way, obtained semiconductor device according to the invention.
In the preferred embodiment of the method according to this invention, the selection molybdenum is as metal and select tellurium as chalcogen.
First modification is characterised in that: form metal level on described first and second dielectric regions; to be positioned at the ion that the locational described metal level of first dielectric region injects chalcogen; simultaneously, protect the locational described metal level of second dielectric region to avoid being injected into by mask.
Another modification is characterised in that: form metal level on described first and second dielectric regions; make and be positioned at the locational described metal level of second dielectric region and oxygen reacts; simultaneously, protect the locational described metal level of first dielectric region to avoid reacting by another mask with oxygen.
These two modifications all allow easily to form two kinds of electric conducting materials.Preferably, before oxidizing process, finish injection process.Like this, oxidation unit can be used for two kinds of materials are annealed under the minimum delay.Only needing to make the gas in the described device is inert gas, and arranges another desired temperature cycles.Can be easily with these feature combinations.Can use the mask that is similar to silicon nitride easily to carry out selective oxidation.
Description of drawings
Read the description that hereinafter with reference embodiment carries out in conjunction with the drawings, these and other aspect of the present invention will become obviously, wherein:
Fig. 1 to Fig. 4 is the sectional view in each stage of making semiconductor device according to the invention by the embodiment according to the inventive method.
Embodiment
Accompanying drawing is schematically, does not proportionally draw, and for clearer, has amplified the size on the thickness direction especially.In each accompanying drawing, be generally corresponding parts and give identical reference number and identical shade.
Fig. 1 to Fig. 4 is the sectional view in each stage of making semiconductor device according to the invention by the embodiment according to the inventive method.
(almost) device of finishing 10 (referring to Fig. 4) comprises semiconductor body 12, here is the semiconductor body 12 of the p type silicon that formed by substrate 11, and wherein, the first transistor 1 is formed as NMOST.In N well region 33, transistor seconds 2 is formed as PMOST.Transistor 1,2 comprises: have source area that n type and p type electricity lead and drain region 1A, 1B, 2A, 2B respectively, and dielectric region 1C, the 2C and gate regions 1D, the 2D that comprise silicon dioxide.Formed isolated area 25 on the surface of semiconductor body 12, here isolated area 25 is with silica-filled ditch (or use other gate-dielectric to fill, for example, metal oxide).
In this example, the gate regions 1D of NMOST1 comprises compound, and described compound comprises that work function is approximately Mo and the Te of 4.1eV, and their work function is in close proximity to the optimum value that is approximately 4.2eV.In this example, the gate regions 2D of PMOST2 comprises compound, and described compound comprises Mo, O and MoO
xComposition (x≤2, for example MoO here
2), can be easily their work function be adjusted into the optimum value that is approximately 5.2eV.In addition, these two gate regions include TiN district and the multi-crystal silicon area on the work function material.
Make device 10 according to following process.Starting point (referring to Fig. 1) is a p type substrate 11, in substrate 11, has formed n trap 33 and STI (shallow isolating trough) district 25.Next formed dielectric layer 21, and by vapor deposition, depositing metal layers 22 on dielectric layer 21 (here preferably, metal level 22 comprises porous Mo), and have thickness in 5 to the 20nm scopes.
(referring to Fig. 2) subsequently forms mask 15 on the position of PMOST2 and NMOST1.The position of PMOST is provided with additional mask 15A.Here, mask 15 comprises that TiN and the deposition by the TiN layer form, and mask 15A comprises for example photoresist layer.Mask 15 has 5 to 20nm thickness, and mask 15A is that 0.5 to 2 μ m is thick.Then, tellurium ion 30 is injected the locational metal level of NMOST1.1-4 * 10 in addition of following the tellurium ion together to inject
15Cm
-2Scaling powder in the scope and the injection energy in 10 to the 20keV scopes.Under given condition, only at the tellurium ion 30 of NMOST1 position or the most of at least Mo layer 22 that arrives in the tellurium ion 30.The thickness of TiN mask 15 can be adjusted in the above-mentioned scope, thereby avoid the Te ion is injected the gate dielectric regions 1C of NMOST1 position, be positioned at the substrate of forming by for example Si below this gate isolation district 1C.In addition, can be optimized, thereby mask 15 is dispensable, and can after Te injects, deposits condition.Exist the attendant advantages of mask 15 to be in the commitment after forming Mo layer 22: mask 15 has protected Mo layer 22 (for example, at memory period) under intermediate conditions to be exposed in the oxygen controllably.
Hereinafter, PMOST2 is carried out similarly processing (referring to Fig. 3).Now, the device 10 that still is coated with TiN layer 15 is subjected to the protection of mask 16.After this mask layer 16 has been carried out uniform deposition, removed the part mask layer 16 of PMOST2 position by photoetching and etching.In this example, mask 16 comprises silicon nitride.Utilize superincumbent mask 16, also removed the part TiN layer 15 of PMOST2 position.Now, the Mo layer 22 of PMOST2 position is exposed in the gaseous compound 40 that comprises O, and here, O2 is heated to T＞250 degree centigrade.Under this condition, Mo layer 22 is converted into MoO partly
2(perhaps being converted into the compound with the composition in the above-mentioned scope), this will form the gate regions 2D of PMOST2.Because oxygen can not see through mask 16, can not be affected so the NMOST1 position comprises the metal level 22 of Te atom.
In this stage, device 10 experience thermal annealing steps are for example carried out spike annealing with the temperature in 700 to 1050 degrees centigrade of scopes in nitrogen.This annealing steps can form MoO
2Device in carry out.Owing to inject in the first step, so device was in the suitable annealing device in this stage.Therefore, the method in this example is quite effective.Next, remove mask 16 by etching.If desired, can remove remaining mask 15.Yet this removal is optional.
In this example, subsequently the cover layer (not shown) of the electric conducting material that is similar to metal nitride (for example titanium nitride) is deposited on the device 10 equably.This material will use subsequently the silicon of deposition to stop the reaction of work function material, and because this material is an electric conducting material, so allow it to be present in the gate stack.In addition, this material can protection device be avoided other exposure under intermediate conditions.
Afterwards, proceed this manufacture process, form gate stack by amorphous or polysilicon deposition, photoetching and etching in common mode.Behind the dash area that has formed source area and drain region 1A, 1B, 2A, 2B, form wall 44 and deep layer source electrode and drain electrode injection.Other step that pattern forms, contact metal deposits and the pattern of contact metal deposition forms of inter metal dielectric deposition before being similar to, preceding inter metal dielectric deposition is not shown among the figure.
What can obviously find out is, the invention is not restricted to example described herein, and those skilled in the art can carry out multiple change and modification within the scope of the invention.For example, the trace (trace) of another element can be introduced electric conducting material in order accurately to adjust work function.In addition, can use the mixing that is similar to Se and Te element to be used for this purpose.
Claims (10)
1. semiconductor device (10) with substrate (11) and semiconductor body (12), described semiconductor body (12) comprises first field-effect transistor (1) and second field-effect transistor (2), described first field-effect transistor (1) has: and first source area and first drain region (1A, 1B); First raceway groove of the first electric conductivity type; And by first dielectric region (1C) and described first raceway groove first grid polar region (1D) isolated, that comprise first electric conducting material, described second field-effect transistor (2) has: and second source area and second drain region (2A, 2B); Second raceway groove of the second electric conductivity type opposite with the described first electric conductivity type; And by second dielectric region (2C) and described second raceway groove second grid district (2D) isolated, that comprise second electric conducting material different with described first electric conducting material, wherein, described first and second electric conducting materials comprise the compound that contains metal and another element, it is characterized in that: described first and second electric conducting materials include the compound that contains metal, described metal is selected from the group that comprises molybdenum and tungsten, and described second electric conducting material comprises the oxygen as another element, and described first electric conducting material comprises the chalcogen as another element.
2. semiconductor device according to claim 1 (10) is characterized in that, the selection molybdenum is as metal and select tellurium as chalcogen.
3. semiconductor device according to claim 1 and 2 (10) is characterized in that, described first electric conducting material comprises the n type.
4. according to claim 1,2 or 3 described semiconductor device (10), it is characterized in that described first and second gate regions are included in another material sections on first and second electric conducting materials, described another material sections conduction, and formation is to the barrier of silicon.
5. semiconductor device according to claim 4 (10) is characterized in that, described another material comprises metal nitride.
6. the manufacture method of a semiconductor device (10), described semiconductor device (10) has the semiconductor device (10) of substrate (11) and semiconductor body (12), described semiconductor body (12) comprises first field-effect transistor (1) and second field-effect transistor (2), described first field-effect transistor (1) has: and first source area and first drain region (1A, 1B); First raceway groove of the first electric conductivity type; And by first dielectric region (1C) and described first raceway groove first grid polar region (1D) isolated, that comprise first electric conducting material, described second field-effect transistor (2) has: and second source area and second drain region (2A, 2B); Second raceway groove of the second electric conductivity type opposite with the described first electric conductivity type; And it is isolated by second dielectric region (2C) and described second raceway groove, the second grid district (2D) that comprises second electric conducting material different with described first electric conducting material, wherein, described first and second electric conducting materials comprise the compound that contains metal and another element, described method is characterised in that: described first and second electric conducting materials include the compound that contains metal, described metal is selected from the group that comprises molybdenum and tungsten, and described second electric conducting material comprises the oxygen as another element, and described first electric conducting material comprises the chalcogen as another element.
7. method according to claim 6 is characterized in that, the selection molybdenum is as metal and select tellurium as chalcogen.
8. according to claim 6 or 7 described methods; it is characterized in that; go up formation metal level (22) at described first and second dielectric regions (1C, 2C, 21); the locational described metal level (22) that will be positioned at first dielectric region (1C) injects the ion (30) of chalcogen; simultaneously, protect the locational described metal level of described second dielectric region (2C) (22) to avoid being injected into by mask (15,15A).
9. according to claim 6,7 or 8 described methods; it is characterized in that: go up at described first and second dielectric regions (1C, 2C, 21) and form metal level (22); locational described metal level of described second dielectric region (2C) (22) and oxygen (40) are reacted; simultaneously, protect the locational described metal level of described first dielectric region (1C) (22) to avoid reacting by another mask (16) with oxygen (40).
10. according to claim 6,7,8 or 9 described methods, it is characterized in that, after forming oxygen compound and/or chalcogen compound, described equipment (10) experience thermal annealing step.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP04104056.9 | 2004-08-24 | ||
| EP04104056 | 2004-08-24 | ||
| EP04104489.2 | 2004-09-16 | ||
| EP05105562.2 | 2005-06-22 |
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| Publication Number | Publication Date |
|---|---|
| CN101010796A true CN101010796A (en) | 2007-08-01 |
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| CN 200580028224 Pending CN101010796A (en) | 2004-08-24 | 2005-08-10 | Semiconductor device and method of manufacturing such a semiconductor device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293085A (en) * | 2020-02-07 | 2020-06-16 | 复旦大学 | Three-dimensional CMOS (complementary metal oxide semiconductor) based on two-dimensional transition metal chalcogenide and tellurium and preparation method thereof |
-
2005
- 2005-08-10 CN CN 200580028224 patent/CN101010796A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111293085A (en) * | 2020-02-07 | 2020-06-16 | 复旦大学 | Three-dimensional CMOS (complementary metal oxide semiconductor) based on two-dimensional transition metal chalcogenide and tellurium and preparation method thereof |
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