CN100595882C - SOI preparation method of bonding and wafer thinning - Google Patents
SOI preparation method of bonding and wafer thinning Download PDFInfo
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- CN100595882C CN100595882C CN200710173696A CN200710173696A CN100595882C CN 100595882 C CN100595882 C CN 100595882C CN 200710173696 A CN200710173696 A CN 200710173696A CN 200710173696 A CN200710173696 A CN 200710173696A CN 100595882 C CN100595882 C CN 100595882C
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Abstract
The invention relates to a production method of an SOI chip by bonding and thinning, when in epitaxy, a doping gas source is utilized for the in-situ generation of a back corrosion layer in an epitaxial furnace, and then an epitaxial single crystal is taken as an SOI layer on the back corrosion layer to form a device chip. Then, the device chip and a support chip are bonded, at least one chip of the using device chip and the support chip is done with the insulation processing before the bonding, the annealing reinforcement is carried out after the bonding, the grinding and corrosion method isadopted for corrosion till the in-site back corrosion layer of the device chip, after that, the back corrosion layer is removed by corrosion, the top layer of silicon is done with the fine grinding, and an SOI wafer is finally formed. Eventually, the thicknesses of the buried layer and the top layer of silicon are respectively decided by the thickness of an oxidation layer and the thickness of anepitaxial layer on the device chip. The buried layer of the SOI wafer which is produced by the process and the thickness of the SOI layer can be regulated in a big range according to the needs. As theusage of the back corrosion layer, the invention can also ensure the thickness uniformity of the top layer of silicon.
Description
Technical field
The invention belongs to the manufacturing process technology field of microelectronics and solid electronics, silica-based integrated-optic device material.
Background technology
Integrated circuit develops into the era of nanotechnology of present great scale, further improve the integrated level and the speed of service of chip, and existing body silicon materials and technology have run into stern challenge, and new important breakthrough must be arranged on material and technology.The SOI technology becomes one of solution of the existing single crystal silicon material of era of nanotechnology replacement, is the sharp weapon of keeping Moore law tendency, and the SOI material becomes the high-end backing material of nanoscale great scale integrated circuit.A large amount of power devices, high tension apparatus and MEMS need the SOI material of thick buried regions, and the raising that requires along with device performance, require also more and more stricter to the thickness evenness of thick buried regions and soi layer.
The SOI material preparation technology of main flow comprises SMART-in the world
, SIMOX, BESOI.SiO in the SIMOX material
2Insulating buried layer is to rely on oxonium ion to inject silicon to form through high annealing, because be subjected to the influence of oxonium ion implantation dosage and energy, so the SOI material SiO that forms
2Buried regions is generally less than 400nm, and upper strata Si thickness≤250nm in other words, injects the SOI technology with ion and can not obtain thick buried regions, the SOI material of thick upper strata silicon fiml.The SOI wafer that this technology forms can't satisfy the requirement of high tension apparatus, MEMS, optical communication uniform thickness buried oxide (as the 1-4 micron).
And the BESOI technology is reinforced the wafer after a slice thermal oxidation and another platelet wafer bonding earlier, and thinning back side forms soi structure to needed thickness again.Two kinds of basic thining methods are arranged: will use CMP (Chemical Mechanical Polishing) process directly to make soi layer meet the requirements of thickness behind the grinding back surface here.The cost of this method is low, but can only be fit to prepare very thick SOI material owing to do not carry on the back the erosion layer.And the top layer silicon thickness evenness is poor, generally greater than 0.5 micron, can not satisfy the requirement of microelectronic applications.In addition, pass through B in addition
+The ion injection mode forms back of the body erosion layer, because the needs of back of the body erosion layer corrosion rate ratio must have very high concentration, B
+Ion concentration is greatly about 10
20Atom/cm
3But there is a balance here,, then can't forms enough strong back of the body erosion layer if doping content is little.If but the too high crystal structure that can change wafer surface again of implantation concentration, because all need an annealing process to repair impaired lattice for any doping injection.
Summary of the invention
Specific demand at thick buried regions, thick film SOI material, the present invention proposes to utilize outer time-delay growth in situ back of the body erosion layer technology and bonding SOI technology to prepare the thick film SOI new technology, can prepare the top layer silicon good uniformity, the thickness that buried regions can be needed arbitrarily by the thermal oxidation or the chemical deposition of device sheet and support, soi layer thickness then can be gone up the thickness that the time of single crystal epitaxial growth is needed arbitrarily by being controlled at back of the body erosion layer, just can obtain the continuously adjustable SOI material of buried regions and soi layer in conjunction with both.
A kind of bonding and wafer thinning prepares the method for Silicon-On-Insulator wafer, step is as follows: the outer time-delay of (1) wafer utilizes dopant gas source middle original position in epitaxial furnace to generate back of the body erosion layer, and then back of the body erosion layer go up epitaxy single-crystal as soi layer to form the device sheet, described original position generates back of the body erosion layer and be meant to be to rely on the impurity gas of extension to decompose the back to form at described back of the body erosion layer in epitaxial furnace, then can continue epitaxial monocrystalline silicon thereon, do not need that disk is shifted out epitaxial device and do other processing, back of the body erosion layer growth and single crystal epitaxial are finished in same equipment simultaneously; (2) device sheet and the support chip bonding that step (1) is prepared, have at least a slice to handle before the bonding in described device sheet and the support chip through insulating, annealing reinforcing again behind the bonding, (3) adopting grinding to add corroding method corrodes to device sheet original position back of the body erosion layer, (4) remove back of the body erosion layer, (5) top layer silicon is carried out the fine gtinding polishing, form final SOI wafer.
As optional technical scheme, growth in situ back of the body erosion layer before step (1) epitaxial monocrystalline silicon or in the epitaxial monocrystalline silicon process, it feeds reacting gas is AsH
3Or PH
3Or B
2H
6In any; The concentration volume ratio of reacting gas is between 0.5～100%, and protective atmosphere is H
2Or N
2Or any among the Ar, between 300-1400 ℃ of its reaction temperature, reaction pressure is between 0.01-10Torr; Perhaps reaction pressure is between 700-770Torr.
As optional technical scheme, in the step (1),, on the device sheet, adopt the monocrystalline silicon layer of extension as soi layer according to the requirement of final products to top layer silicon thickness, promptly the back of the body of growth loses layer growing epitaxial layers in position, and extension is homoepitaxy or heteroepitaxy; Epitaxial loayer is P type or N type, boron-doping, phosphorus or arsenic.
As optional technical scheme, according to the requirement to insulating buried layer thickness, the stratification of insulating is handled to device sheet or support chip in the step (2), and method comprises thermal oxide growth or chemical gaseous phase depositing process; Wherein the thermal oxide growth treatment temperature is between 300～1400 ℃; The insulating barrier of chemical vapour deposition (CVD) comprises: the SiO of deposition
2Film or Si
3N
4Film, the insulating barrier of deposition carries out 500～1200 ℃ annealing in process.
As optional technical scheme, in the step (2) above-mentioned device sheet and support chip are carried out bonding, and annealing is reinforced; Annealing temperature is at 100-1000 ℃, time 0.5-15 hour; Atmosphere is selected from a kind of in dried oxygen, wet oxygen, oxygen containing nitrogen and the oxygen containing argon gas.
As optional technical scheme, from grinding back surface device sheet, attenuate device sheet makes back of the body erosion layer go up the thickness of residue film within 1-100 μ m in the step (3).
As optional technical scheme, the method for employing chemical corrosion, high-temp chlorination hydrogen HCl etching or thermal oxidation is removed the original position back of the body erosion layer on the device sheet in the step (4), exposes the soi layer that extension obtains.
As optional technical scheme, step (2) is Direct Bonding or the auxiliary room temperature bonding of using plasma at room temperature.
As optional technical scheme, device sheet attenuate adopts Grinding or Lapping milling apparatus or Polishing polissoir in the step (3); The thickness thinning of device sheet is greater than 50 μ m.
As optional technical scheme, the corrosion rate that described caustic solution makes material and the original position back of the body erosion layer that is corroded is than greater than 50, thereby is implemented in corrosion on the original position back of the body erosion layer from stopping; Corrosive liquid is organic corrosive agent of monocrystalline silicon or alkali corrosion liquid; The weight proportion of its corrosive liquid is that the ratio of chemical agent and deionized water was at 1: 1～1: 1000; The corrosion reaction temperature is between 10-200 ℃.
As optional technical scheme, chemical corrosion method is removed original position back of the body erosion layer, and the chemical corrosion liquid HNA volume proportion of described original position back of the body erosion layer is HF: HNO
3: CH
3COOH=1: (1～5): (3～15).
The main preparation process of SOI material is as follows among the present invention, as shown in Figure 1, choose a slice semiconductor crystal wafer wafer A, at first do preceding cleaning, can adopt RCA cleaning method commonly used that wafer surface is cleaned, before clean after, handle (comprising the mode of thermal oxidation or the method for chemical deposition) by insulating and grow certain thickness insulating barrier (comprise silicon dioxide, or silicon nitride or the like) at wafer this sheet wafer is as support chip for future use then.
Get a slice wafer B in addition, can carry out wafer surface with the RCA cleaning method earlier equally cleans, after the cleaning this sheet wafer B is carried out the epitaxial growth of original position back of the body erosion layer, the step of its growth is as follows: at high temperature, pressure is under normal pressure or the low pressure situation, at first feeds B
2H
6, AsH
3, PH
3, wherein any one reacting gas at the back of the body erosion layer of Si surface coverage growth one deck B atom or As or P atomic layer, and then feeds SiH
4, TCS, DCS, SiCl
4Homepitaxy gas carries out extension, the certain thickness epitaxial loayer of growing as required, and described epitaxy technique preferentially adopts with SiH
4Epitaxy technique for source of the gas.Epitaxial loayer can be P type or N type.The extension soi layer adopts the common process [2] that generally adopts in the semi-conductor industry.
Select than the foreign atom of high principle selective epitaxy layer according to corrosion with back of the body erosion layer.Also can the non-doped epitaxial monocrystalline silicon layer of epitaxial growth, the doping source of the gas of back of the body erosion layer can be selected arbitrarily like this.Delay outward and can handle, comprise that meticulous polishing or insulation stratification handle, improve wafer B surface quality or satisfy the requirement of post-order process epitaxial surface.
The preferential employing of described insulation stratification processing low-temperature plasma oxidation generation insulation film or low-temp low-pressure chemical vapour deposition (CVD), low-temperature plasma assistant depositing technology generate insulation film.WaferB after treatment is as the device sheet.
Use bonding technology that wafer A and two of B are bonded together, can adopt room temperature bonding technology or low-temperature plasma to assist bonding technology, bonding post-reinforcing during bonding.Preferential auxiliary bonding technology of employing low-temperature plasma and the follow-up medium annealing reinforcement process recommended.Utilize Ginding process that the silicon fiml at the device sheet wafer B back side is removed up to distance back of the body erosion layer 1～100 μ m after two platelet wafer bondings are good earlier, herein behind the attenuate on the device sheet remaining thickness be greater than and grind mechanical damage layer in the rear film, usually thickness is about 10 μ m under the technology, chemical liquids wet etching then, perhaps high temperature HCl lithographic method erodes to original position extension back of the body erosion layer, because the effect of back of the body erosion layer, first step corrosion stops, and then will carry on the back the corrosion of erosion layer with the chemical liquids wet etching.For the surface quality that further improves soi layer can adopt methods such as comprising polishing that the surface is processed.So just can obtain the SOI wafer that appropriate size requires.
The invention has the advantages that owing to using back of the body erosion layer, the uniformity of soi layer is well improved, and the uniformity of while soi layer also no longer is subjected to the influence of support chip planarization, can reduce the support chip cost.In addition, owing to do not adopt ion implantation technology, can well guarantee the quality of soi layer, as perfection of lattice, distribution of resistance uniformity.Because the defective that ion injects can cause the decline of final soi layer quality.Because other monocrystalline such as GaAs have and similar extension of monocrystalline silicon and bonding technology character, so the present invention can be embodied in other single crystal wafers such as GaAs equally.
Description of drawings
Fig. 1 is the preparation flow schematic diagram of the embodiment of the invention.
Embodiment
Following specific embodiment helps to understand the features and advantages of the present invention, but enforcement of the present invention is not limited thereto embodiment.
Embodiment 1:
Step 1: choose a slice monocrystalline silicon buffing disk waferA, adopt the SC1 solution of RCA that wafer surface is carried out preceding cleaning then, after preceding the cleaning, mode by thermal oxidation is at waferA growth 1000nm thick silicon dioxide layer, Sheng Chang silicon dioxide thickness can be as required herein, according to the empirical equation [1] that the Deal-grove oxidated layer thickness calculates, make the continuously adjustable purpose thereby change technological parameters arrival such as growth time or temperature.This sheet wafer A as support chip for future use.
Step 2: other gets a slice monocrystalline silicon buffing disk wafer B, adopts the SC1 solution of RCA to clean equally, cleans back this sheet wafer B and sends in the epitaxial furnace, and the step of its growth is as follows: at 600 ℃, under the 0.4Torr atmospheric pressure, feed 200cc PH
3, 30 minutes.
At Si surface coverage growth one deck P atom back of the body erosion layer, and then feed SiH
4Extension gas carries out the body silicon epitaxy, the single-crystal Si epitaxial layers of the 1 μ m that grows.Epitaxially grown here monocrystalline silicon thickness also can need be adjusted the extension time and epitaxy layer thickness is carried out arbitrarily adjustment continuously according to specification, and cleaned wafer B is as the device sheet behind the process SC1.
Step 3: use the auxiliary bonding technology of low-temperature plasma that wafer A and two of B are bonded together, adopt the auxiliary bonding technology of low-temperature plasma during bonding, low temperature annealing process is reinforced in adopting behind the bonding.Utilize Ginding process that the silicon fiml at the device sheet wafer B back side is removed up to about distance back of the body erosion layer 10 μ m after two platelet wafer bondings are good earlier, lose layer with the KOH solution corrosion to the original position extension back of the body then, because the effect of back of the body erosion layer, first step corrosion stops, and then is 1: 3: 8 HF with proportioning: HNO
3: CH
3The COOH mixed acid solution will be carried on the back the erosion layer and erode.
Step 4: adopt chemical mechanical polishing method that the SOI surface is processed a retrofit, obtain final products.
Embodiment 2:
Step 1: choose a slice monocrystalline silicon buffing disk wafer A, adopt the SC1 solution of RCA that wafer surface is carried out preceding cleaning then, after preceding the cleaning, mode by thermal oxidation is at wafer A growth 500nm thick silicon dioxide layer, Sheng Chang silicon dioxide thickness can be as required herein, according to the empirical equation [1] that the Deal-grove oxidated layer thickness calculates, make the continuously adjustable purpose thereby change technological parameters arrival such as growth time or temperature.This sheet wafer A as support chip for future use.
Step 2: other gets a slice monocrystalline silicon buffing disk wafer B, adopts the SC1 solution of RCA to clean equally, cleans back this sheet wafer B and sends in the epitaxial furnace, and the step of its growth is as follows: at 1000 ℃, under the 760 Torr pressure, feed 400sccm B
2H
6, B in the reative cell
2H
6Concentration is 100%, 20 minute.
At Si surface coverage growth one deck B atom back of the body erosion layer, and then feed SiH
4Extension gas carries out the body silicon epitaxy, the single-crystal Si epitaxial layers of the 1.5 μ m that grow.Through cleaned behind the SC1, the method by LPCVD deposits the thick silicon dioxide layer of 500nm again.This sheet wafer B is as the device sheet.
Step 3: use the auxiliary bonding technology of low-temperature plasma that wafer A and two of B are bonded together, adopt the auxiliary bonding technology of low-temperature plasma during bonding, low temperature annealing process is reinforced in adopting behind the bonding.Utilize Ginding process that the silicon fiml at the device sheet wafer B back side is removed up to about distance back of the body erosion layer 10 μ m after two platelet wafer bondings are good earlier, lose layer with the KOH solution corrosion to the original position extension back of the body then, because the effect of back of the body erosion layer, first step corrosion stops, and then is 1: 3: 8 HF with proportioning: HNO
3: CH
3The COOH mixed acid solution will be carried on the back the erosion layer and erode under 25 ℃ temperature.
Step 4: adopt chemical mechanical polishing method that the SOI surface is processed a retrofit, obtain final products.
Claims (11)
1, a kind of bonding and wafer thinning prepares the method for Silicon-On-Insulator wafer, it is characterized in that step is as follows:
(1) the outer time-delay of wafer utilizes dopant gas source middle original position in epitaxial furnace to generate back of the body erosion layer, and then back of the body erosion layer go up the epitaxy single-crystal silicon layer as the silicon layer on the insulator to form the device sheet, described original position generation back of the body erosion layer is to rely on the impurity gas decomposition back of extension to form in epitaxial furnace, and described impurity gas is selected from AsH
3Or PH
3Or B
2H
6In a kind of, then can continue epitaxial monocrystalline silicon thereon, do not need that wafer is shifted out epitaxial furnace and do other processing, back of the body erosion layer growth and single crystal epitaxial are finished in same equipment simultaneously;
(2) with the device sheet and the support chip bonding of step (1) preparation, have at least a slice to handle before the bonding in described device sheet and the support chip through insulating, anneal again behind the bonding and reinforce,
(3) adopt grinding to add corroding method and corrode to device sheet original position back of the body erosion layer,
(4) remove back of the body erosion layer,
(5) top layer silicon is carried out the fine gtinding polishing, form silicon wafer on the final insulation body.
2, the method for preparing Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1 is characterized in that the preceding growth in situ back of the body of step (1) epitaxial monocrystalline silicon erosion layer, and the concentration volume ratio of the impurity gas of its feeding is between 0.5%～100%, and protective atmosphere is H
2Or N
2Or any among the Ar, between 300-1400 ℃ of its reaction temperature, reaction pressure is between 0.01-10Torr; Perhaps reaction pressure is between 700-770Torr.
3, the method for preparing Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1, it is characterized in that: in the step (1), according to requirement to the top layer silicon thickness of final products, on the device sheet, adopt the monocrystalline silicon layer of extension as soi layer, promptly the back of the body of growth loses layer growing epitaxial layers in position, and extension is homoepitaxy or heteroepitaxy; Epitaxial loayer is P type or N type, boron-doping, phosphorus or arsenic.
4, the method for preparing Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1, it is characterized in that: basis is to the requirement of insulating buried layer thickness in the step (2), the stratification of insulating is handled to device sheet or support chip, and method comprises thermal oxide growth or chemical gaseous phase depositing process; Wherein the thermal oxide growth treatment temperature is between 300～1400 ℃; The insulating barrier of chemical vapour deposition (CVD) comprises: the SiO of deposition
2Film or Si
3N
4Film, the insulating barrier of deposition carries out 500～1200 ℃ annealing in process.
5, prepare the method for Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1, it is characterized in that: in the step (2) above-mentioned device sheet and support chip are carried out bonding, and annealing is reinforced; Annealing temperature is at 100-1000 ℃, time 0.5-15 hour; Atmosphere is selected from a kind of in dried oxygen, wet oxygen, oxygen containing nitrogen and the oxygen containing argon gas.
6, prepare the method for Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1, it is characterized in that: from grinding back surface device sheet, attenuate device sheet makes back of the body erosion layer go up the thickness of residue film within 1-100 μ m in the step (3).
7, the method for preparing Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1, it is characterized in that: the method for employing chemical corrosion, high-temp chlorination hydrogen HCl etching or thermal oxidation is removed the original position back of the body erosion layer on the device sheet in the step (4), exposes the soi layer that extension obtains.
8, prepare the method for Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1, it is characterized in that: step (2) is Direct Bonding or the auxiliary room temperature bonding of using plasma at room temperature.
9, the method for preparing Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1 is characterized in that device sheet attenuate adopts Grinding or Lapping milling apparatus or Polishing polissoir in the step (3); The thickness thinning of device sheet is greater than 50 μ m.
10, the method for preparing Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 1 is characterized in that corrosion rate that described caustic solution makes material and the original position back of the body erosion layer that is corroded than greater than 50, thereby is implemented in corrosion on the original position back of the body erosion layer from stopping; Corrosive liquid is organic corrosive agent of monocrystalline silicon or alkali corrosion liquid; The weight proportion of its corrosive liquid is that the ratio of chemical agent and deionized water was at 1: 1～1: 1000; The corrosion reaction temperature is between 10-200 ℃.
11, the method for preparing Silicon-On-Insulator wafer by the described bonding and wafer thinning of claim 7 is characterized in that chemical corrosion method removes in the technology of original position back of the body erosion layer, and the chemical corrosion liquid HNA volume proportion of described original position back of the body erosion layer is HF: HNO
3: CH
3COOH=1: (1～5): (3～15).
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|---|---|---|---|---|
| CN102479674B (en) * | 2010-11-22 | 2014-12-31 | 比亚迪股份有限公司 | Wafer manufacturing method |
| CN102820251A (en) * | 2011-06-08 | 2012-12-12 | 中国科学院上海微系统与信息技术研究所 | Method for preparing SOI (silicon on insulator) material with high-K dielectric buried layer on basis of bonding technology |
| CN102903607A (en) * | 2011-06-30 | 2013-01-30 | 上海新傲科技股份有限公司 | Method for preparing substrate with buried insulation layers by selective etching |
| CN107393812A (en) * | 2017-08-31 | 2017-11-24 | 长江存储科技有限责任公司 | A kind of wafer cleaning method |
| CN110459555A (en) * | 2019-08-29 | 2019-11-15 | 长春长光圆辰微电子技术有限公司 | Manufacturing process method of the back side illumination image sensor crystal round fringes without silicon fiml defect |
| FR3116940B1 (en) * | 2020-11-27 | 2023-06-09 | Commissariat Energie Atomique | Low temperature process for manufacturing a semiconductor substrate on insulator |
| CN114242647B (en) * | 2021-12-08 | 2022-11-18 | 中环领先半导体材料有限公司 | Method for improving thickness uniformity of device silicon layer of silicon wafer on insulator |
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