CN100583077C - Device and method for promoting system bus drive ability - Google Patents
Device and method for promoting system bus drive ability Download PDFInfo
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- CN100583077C CN100583077C CN200710178389A CN200710178389A CN100583077C CN 100583077 C CN100583077 C CN 100583077C CN 200710178389 A CN200710178389 A CN 200710178389A CN 200710178389 A CN200710178389 A CN 200710178389A CN 100583077 C CN100583077 C CN 100583077C
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Abstract
The invention provides a device for improving system bus drive capability and a method thereof, belonging to electrical and digital data processing field. The device comprises a processor, at least two tri-state buffers connected with the processor in series and a bus controller parallelly connected with the tri-state buffers, wherein, the pin opens a circuit by pole piece phase selection after buffering and controlling the OE emitter electrode of the tri-state buffer, the DIR direction pins of a control bus and an address bus of the tri-state buffer are grounded, and the DIR direction pin of a data bus is connected with a system bus. The invention drives the multistage tri-state buffer in stages, so as to improve the drive capability of the system bus. The invention can be widely used in hardware of an embedded system.
Description
Technical field
The present invention relates to the numerical data processing technology field, relate in particular to a kind of device and method that improves system bus drive ability.
Background technology
At present, flush bonding processor carries out control operation by system bus to bus controller spare, such as the operation to Flash (flash memory), SDRAM (synchronous DRAM) and other peripheral components.In order to satisfy the control operation of system bus, need to improve the driving force of system bus to a plurality of bus controllers.
The method of existing raising system bus drive ability has increases methods such as going up pull down resistor and increase three-state buffer, wherein, some are changed signal more slowly, such as at reset, signals such as sheet choosing and interruption, can adopt increases the method that goes up pull down resistor, to move power supply on the signal to, according to the KCL law of Kirchhoff's law, the drive current of signal has increase; But then need to improve by three-state buffer the driving force of system bus for bus signals, promptly three-state buffer mainly makes the input current of signal improve output current through behind the three-state buffer.Rule of thumb analyze, system bus can directly drive 4 to 5 bus controller spares, but, when the number of bus controller spare surpasses 5, the reliability of system bus may have problems, because the drive current of general processor bus interface output is a fixed value, external bus controller spare, electric current to input signal also has a thresholding, if external bus controller spare more for a long time, the output current of processor bus interface signal will be too little by what divide, and be not enough to drive certain bus controller spare, will cause the unreliable of system.
In realizing process of the present invention, find that there are the following problems at least in the prior art: when the processor periphery is connected with less bus controller spare, peripheral bus controller spare can be connected on by the mode of parallel connection on the bus interface of processor, but work as bus controller spare more for a long time, because the restriction of the driving force of system bus can't guarantee reliability of system operation.
Summary of the invention
The invention provides a kind of device and method that improves system bus drive ability, by three-state buffer system bus is carried out classification and drive, thereby improved the system bus driving capability.
To achieve these goals, the invention provides a kind of device that improves system bus drive ability, comprise processor and bus controller spare, wherein, also comprise: two-stage three-state buffer at least, the OE emitter of first order three-state buffer open circuit pin and each sheet that described processor sends select the CS signal with, be used to drive and described first order three-state buffer and the described bus controller spare that connects, the input of second level three-state buffer is connected with the output of described first order three-state buffer, be used to drive and described second level three-state buffer and the described bus controller spare that connects, wherein, the DIR direction pin of the data bus of every utmost point three-state buffer is connected with system bus, the DIR direction pin ground connection of the control bus of every utmost point three-state buffer and address bus.
Above-mentioned a kind of device that improves system bus drive ability, wherein, described device also comprise with the corresponding buffering of every grade of three-state buffer after the pole piece choosing with, be connected the OE emitter that is used to the to control every grade of three-state buffer pin of opening a way with every grade of three-state buffer.
In order better to realize above-mentioned purpose, the present invention also provides a kind of method that improves system bus drive ability, wherein, comprising:
With the OE emitter of first order three-state buffer open circuit pin and each sheet that described processor sends select the CS signal with, the input of second level three-state buffer is connected with the output of described first order three-state buffer, the DIR direction pin of the data bus of every utmost point three-state buffer is connected with system bus, the DIR direction pin ground connection of the control bus of every utmost point three-state buffer and address bus;
Determine the number of bus controller spare according to the drive current of processor;
Drive every grade of impact damper of the first order and with every grade of impact damper of the described first order and the described bus controller spare that connects;
According to the number that determines the bus controller spare that the every grade of impact damper in the second level will drive through the output current of every grade of impact damper of the described first order.
Above-mentioned a kind of method that improves system bus drive ability, wherein, described method further comprises:
The streams data direction of every grade of impact damper of the described first order of read operation signal controlling of described processor is with the streams data direction of the every grade of impact damper in the described second level of read operation signal controlling of every grade of impact damper of described first order output.
A technical scheme in the technique scheme has following beneficial effect: by three-state buffer system bus is carried out classification and drive, improved the driving force of system bus, thereby realize the operation of system bus to a plurality of bus controller spares, and the sequential of system bus does not change, and has guaranteed reliability of system operation.
Description of drawings
Fig. 1 is the apparatus structure synoptic diagram that improves system bus drive ability in the embodiments of the invention;
Fig. 2 for of the present invention be the structural representation of three-state buffer in the example;
Fig. 3 is the A mouth and the B mouth synoptic diagram of three-state buffer in the embodiments of the invention;
Fig. 4 is the method flow diagram that improves system bus drive ability in the embodiments of the invention.
Embodiment
Add a plurality of three-state buffers by back level in an embodiment of the present invention, then three-state buffer is carried out classification and drive at three-state buffer, thus the driving force of raising system bus.
The existing systems bus comprises: data bus, address bus and control bus.Wherein, control bus comprises: CS (sheet choosing), RD (read operation enables) and WE (write operation enables), when processor is operated bus controller spare, all be to carry out the sheet choosing by CS earlier, choose the bus controller spare that to visit, and then bus controller spare is carried out addressing operation, writes data manipulation or sense data operation.
By using a plurality of three-state buffers, improve the driving force of system bus in the embodiments of the invention, make processor can control a plurality of bus controller spares.Number according to bus device has been carried out classification to three-state buffer again, can pass through every grade of three-state buffer system bus by the direction of system bus and be divided into two parts, and wherein, a part is address bus and control bus, and another part is a data bus.
Control bus and address bus all are that folk prescription is to signal, signal all is to send to bus controller spare from processor, therefore the control bus and the address bus DIR direction pin of three-state buffer data bus only need directly drag down, just above-mentioned signal from the processor to the three-state buffer after, arrive bus controller spare again, the OE emitter of three-state buffer open circuit pin can select by each sheet that processor sends the CS signal with, control the duty or the high-impedance state of three-state buffer, and the direct ground connection of the DIR direction pin of the control bus of three-state buffer and address bus, the sense of passing through is delivered to the A mouth from the B mouth of three-state buffer.
Because data bus will be considered direction, the OE emitter of three-state buffer open circuit pin be still each sheet that sends by processor select the CS signal with, control the duty or the high-impedance state of three-state buffer, and the DIR direction pin of three-state buffer will be controlled by read signal RD, the direction that makes data bus signal when read operation is invalid from the B mouth to the A mouth, when read operation is effective the direction of data from the A mouth to the B mouth.Require simultaneously to select when effective at the back utmost point each sheet, three-state buffer will be in running order, and when the sheet choosing is all invalid, three-state buffer will be in high-impedance state, thereby can not influence the normal operation of other bus controller spare.
In order to make those skilled in the art understand the present invention program better, embodiments of the invention are described in further detail below in conjunction with drawings and embodiments.
By Fig. 1 and Fig. 2 as can be known, the structural representation that installs in the embodiments of the invention has only demonstrated the syndeton of the three-state buffer of preceding two-stage among the figure, and the quantity of SDRSM and FLASH and put in order and can specifically select according to the needs of system design.
In an embodiment of the present invention because system belongs to embedded system, therefore need be connected SDRAM close as far as possible with processor, therefore first order three-state buffer and two SDRAM are attempted by on the bus B US, only are equivalent to above the bus B US and have connect 3 devices.Be called B1 BUS through the bus behind the first order three-state buffer, SDRAM and processor that this bus connects FLASH and prime constitute embedded minimum system, as long as above-mentioned minimum system can move, just can debug one by one other peripheral bus control devices, therefore such arrangement has incremental effect to the later stage debugging.
Be called B2BUS through the bus behind the three-state buffer of the second level, the third level impact damper that the utmost point partly connects after this bus is identical with the catenation principle of preceding two-stage three-state buffer, therefore omits to illustrate in Fig. 1.
Because flush bonding processor carries out the operation of system bus is all asynchronous usually, the therefore operation that can not read or write simultaneously two devices in the same moment.For data bus through three-state buffer, because data direction is inconsistent when read operation and write operation, therefore need control the direction of three-state buffer DIR direction pin, here with read signal data bus direction is controlled, promptly reading when effective, data from the B mouth of three-state buffer to the A mouth, when read data when invalid then from the A mouth of three-state buffer to the B mouth, as shown in Figure 3.Three-state buffer is that two kinds of unidirectional buffering and bidirectional buffers are arranged, one-way damper does not have DIR direction pin, only need control and get final product the OE emitter open circuit pin of device, general is exactly when OE emitter open circuit pin is low level, signal can enter from the A mouth of device, from the output of B mouth, when OE emitter open circuit pin was high level, B mouth output level was a high-impedance state.Bidirectional buffer increases direction control signal, when OE emitter open circuit pin is low level, device is started working, the direction of the level decision signal of DIR direction pin, when DIR direction pin was high level, signal can only be imported from the A mouth, export from the B mouth, when DIR direction pin was high level, signal can only be exported from the A mouth from the input of B mouth.
Three-state buffer for the back one-level then needs the chip selection signal of back device and the signal that comes out, and controls the OE emitter open circuit pin of back level three-state buffer, and direction control signal is with controlling through the read signal behind the first order three-state buffer.Make like this and can guarantee that bus signals is not being changed through the sequential behind the first order three-state buffer.
When implementing embodiments of the invention, bus signals is after output, drive first order three-state buffer and several bus controller spare, to decide the number of direct control bus control device according to the drive current of processor bus signal, behind first order three-state buffer, originally the electric current on the bus signals is improved, can satisfy the input current thresholding of back level bus controller spare, drive second level three-state buffer and several bus controller spare, also will be according to bus signals output current through first order three-state buffer, decide the number of the bus controller spare that will drive, drive down so successively, just realized three-state buffer is carried out classification, improved the driving force of bus signals, increased the reliability of system design, can design the device of the raising system bus drive ability of using multistage three-state buffer according to above-mentioned steps.
As shown in Figure 4, for improving the method flow diagram of system bus drive ability in the embodiments of the invention, concrete steps are as follows:
Step 400, according to the number of bus controller spare, determine the progression of needed three-state buffer.
Step 401, according to the drive current of processor system bus interface, determine that the processor system bus interface directly drives the number of bus controller spare;
Step 402, drive first order impact damper and with described first order impact damper and the described bus controller spare that connects;
Step 403, according to the number of the bus controller spare that will drive through the output current of described first order impact damper decision second level impact damper.
Determine the number of all back level bus controller spares that three-state buffer at different levels drove according to step 402 and step 403.
As shown from the above technical solution, by multistage three-state buffer is carried out classification, improved the driving force of system bus, thereby realized the operation of system bus a plurality of bus controllers, and the sequential that guarantees bus does not change, and has guaranteed reliability of system operation.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (4)
1. device that improves system bus drive ability, comprise processor and bus controller spare, it is characterized in that, also comprise: two-stage three-state buffer at least, the OE emitter of first order three-state buffer open circuit pin and each sheet that described processor sends select the CS signal with, be used to drive and described first order three-state buffer and the described bus controller spare that connects, the input of second level three-state buffer is connected with the output of described first order three-state buffer, is used to drive and described second level three-state buffer and the described bus controller spare that connects;
Wherein, the DIR direction pin of the data bus of every utmost point three-state buffer is connected with system bus, the DIR direction pin ground connection of the control bus of every utmost point three-state buffer and address bus.
2. a kind of device that improves system bus drive ability according to claim 1, it is characterized in that, described device also comprise with the corresponding buffering of every grade of three-state buffer after the pole piece choosing with, be connected the OE emitter that is used to the to control every grade of three-state buffer pin of opening a way with every grade of three-state buffer.
3. a method that improves system bus drive ability is characterized in that, comprising:
With the OE emitter of first order three-state buffer open circuit pin and each sheet that described processor sends select the CS signal with, the input of second level three-state buffer is connected with the output of described first order three-state buffer, the DIR direction pin of the data bus of every utmost point three-state buffer is connected with system bus, the DIR direction pin ground connection of the control bus of every utmost point three-state buffer and address bus;
Determine the number of bus controller spare according to the drive current of processor;
Drive first order three-state buffer and with described first order three-state buffer and the described bus controller spare that connects;
According to the number that determines the bus controller spare that second level three-state buffer will drive through the output current of described first order three-state buffer.
4. a kind of method that improves system bus drive ability according to claim 3 is characterized in that described method further comprises:
The streams data direction of the described first order three-state buffer of read operation signal controlling of described processor is with the streams data direction of the described second level of the read operation signal controlling three-state buffer of described first order three-state buffer output.
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| CN200710178389A CN100583077C (en) | 2007-11-29 | 2007-11-29 | Device and method for promoting system bus drive ability |
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| CN200710178389A CN100583077C (en) | 2007-11-29 | 2007-11-29 | Device and method for promoting system bus drive ability |
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| CN105866610B (en) * | 2016-04-15 | 2019-11-22 | 中国海洋石油集团有限公司 | Connect the detection device and detection method of bus |
| CN107229589B (en) * | 2017-06-21 | 2024-03-12 | 上海景格信息科技有限公司 | TTL communication bus sub-module expansion circuit |
| CN107367697B (en) * | 2017-08-24 | 2020-09-01 | 武汉大学 | Double-detector lithium battery surface temperature detection device and method |
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Effective date of registration: 20201224 Address after: 224006 12th floor, yanchuang building, 1 Zhenxing Road, Yandu District, Yancheng City, Jiangsu Province (d) Patentee after: Yancheng Yongheng Asset Management Co.,Ltd. Address before: 518057 Ministry of justice, Zhongxing building, South Science and technology road, Nanshan District hi tech Industrial Park, Shenzhen, Guangdong Patentee before: ZTE Corp. |
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