CN100573456C - A kind of paralleling multi-processor virtual machine system - Google Patents
A kind of paralleling multi-processor virtual machine system Download PDFInfo
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Abstract
The invention discloses the paralleling multi-processor virtual machine system that a kind of CPU of support carries out simultaneously, comprise a virtual machine and the operating system that operates on the virtual machine.This dummy machine system can be simulated at least one virtual processor, and it comprises a processor Parallel Simulation module, a memory management module, interrupt control analog module and peripheral hardware analog module; The machine instruction of operating system passes to processor simulation module by the memory management module of virtual machine, processor simulation module can be simulated the operating system instruction that the translation module translation comes that is used to execute instruction of a plurality of virtual processors, and make it executed in parallel, go out the present invention proposes the synchronous and access control algorithm in the executed in parallel process simultaneously; The interrupt control analog module is responsible for coordinating peripheral hardware analog module and processor simulation module.The present invention is particularly suitable for the parallelization execution environment of a virtual complete analog hardware on a SMP server or multiple-core server.
Description
Technical field
The present invention relates to Computer Systems Organization, be specifically related to a kind of paralleling multi-processor virtual machine system, make virtual a plurality of processors can parallel running on modern multiprocessor servers platform.
Background technology
Operating system has played a very special effect in current PC and server, it has been connected the wide gap between user application and the hardware platform as a bridge block.In a very long time in the past, on a computing machine, have only an operating system in one given period, to move.Therefore, in order to make a plurality of operating systems, or the application program of different operating system runs on same the computing machine simultaneously, and scientists has been invented out many methods and technology.
Virtual machine as a kind of powerful and also easily technology obtained widely using.
System-level virtual machine is simulated all constituents of a computer system with higher precision.What operating system and the application program on it can be correct like this moves on this virtual machine.System-level virtual machine is to operate on the operating system as an application program.The service that system-level virtual machine can utilize operating system to provide; be subjected to simultaneously the restriction of operating system again; for example: if operating system provides protection to the visit of internal memory; do not allow the direct access memory physical address of application program; when virtual machine moves so, in memory management, just have great expense.Representative the having of this class virtual machine: Bochs, QEMU etc.System-level virtual machine generally is applied to the scientific research field of system architecture, with helping the performance that the researchist weighs multiprocessor or storage system, perhaps is used for the development field of operating system.
Along with hardware development with rapid changepl. never-ending changes and improvements, the particularly widespread use of SMP (symmetric multiprocessor) server and the progress of multi-core technology, some present virtual machine techniques or can not make full use of the multiprocessor resource, otherwise the CPU number that fictionalizes is subjected to the restriction of actual physics processor number.Above mentioned various virtual machine also all exists such or such deficiency.The traditional virtual machine (as: Bochs IA-32Emulator:
Http:// bochs.sourceforge.net/) when structure has user's execution environment of multiprocessing resource, in order to realize the synchronous of performance element, be actually being received within the execution of a plurality of processing units in the circulation, to carry out serial and carry out, its efficient is low-down.For under multi-processor environment, construct general and virtual execution environment, just must at first realize the parallelization of execution environment itself, simultaneously, because the quantity of the nuclear that multinuclear hardware is had constantly improves, itself must have extensibility this execution environment, and promptly system operates on the processor machine with any a plurality of nuclears with can not adding modification, and can make full use of the handling property of bottom main frame.And paralleling multi-processor virtual machine system of the present invention is with regard to effective this problem that solved.
Summary of the invention
The purpose of this invention is to provide a kind of paralleling multi-processor virtual machine system, a complete computer system can be simulated by this system, can simulate a plurality of CPU, and makes the interior at one time executed in parallel of virtual cpu.
Paralleling multi-processor virtual machine system provided by the invention is characterized in that: this system comprises virtual machine and virtual machine internal operating system;
The virtual machine internal operating system adopts the operating system of supporting symmetric multiprocessor, moves on virtual machine;
Virtual machine provides virtual platform for the user, and it comprises processor Parallel Simulation module, memory management module, interrupt control analog module and peripheral hardware analog module;
Processor Parallel Simulation module is used for the instruction that the sink virtual machine internal operating system is submitted to, is carried out after the translation; If instruction relates to memory read-write, the read-write operation signal will pass to memory management module; If processor Parallel Simulation module is wanted handling interrupt, then look-at-me is sent to the interrupt control analog module;
Memory management module is responsible for the read-write operation management of all internal memories, and memory management module sends the peripheral port address that receives to the peripheral hardware analog module, and the result of memory read-write operation is fed back to processor Parallel Simulation module;
The peripheral hardware analog module is responsible for simulating all peripheral hardware action and echo port access message, interrupts if cause, and then look-at-me is sent to the interrupt control analog module and handles;
The interrupt control analog module is responsible for the control and the management of the look-at-me in the virtual machine; It receives the external interrupt signal that transmits from the peripheral hardware analog module on the one hand, carries out interrupt operation with processor Parallel Simulation module cooperative on the other hand.
The present invention can be both complete a computer system view is provided, can make full use of the various processing resources of actual hardware again.Compare with existing technology, the present invention has following characteristics:
A. can simulate a complete computer system.The consideration on the performance or the restriction of implementation method a lot of traditional virtual machines arranged owing to can not provide a complete computer system view.They often only provide the execution environment of a software.Just because of this, the software that has only some to write for these traditional virtual machines specially could move on these virtual mechanism.Such restriction makes a lot of other widely used softwares just can be applied to so will certainly increase many workloads virtually on the virtual machine through rewriting.The present invention makes current various mainstream operation systems not change and directly moves owing to the simulation that provides for complete computer system.Like this, all application software can depend on operating system and need not to make any modification and directly use.
B. can adjust the number and the every hardware parameter of configuration of virtual cpu at any time.Because the present invention realizes that with the thread encapsulation number of virtual CPU is not subjected to the restriction of actual physics CPU number fully to each virtual CPU.In addition, because all peripheral hardwares of the present invention all are to be simulated and managed by the peripheral hardware analog module, peripheral hardware will not be subjected to the restriction of actual real equipment.The user can arbitrarily simulate various types of peripheral hardwares, only need provide unified read-write interface just can join among the dummy machine system very easily.
C. can efficiently utilize the multiprocessor computational resource of real server with parallel executing method.The present invention uses parallel fully mode to simulate a computer system.If virtual machine of the present invention operates in the hardware environment of a multiprocessor, it will make full use of the actual calculation resource.Even change has taken place the physical computing environment of bottom, all be transparent for operating system that runs on virtual machine of the present invention inside and application software thereof.
D. the present invention is when parallelization simulation multiprocessor, utilizes the method for synchronous of virtual cpu thread and the access control of critical resource has been guaranteed the logical correctness of virtual machine when carrying out.
Description of drawings
Fig. 1 is the hierarchical structure synoptic diagram of paralleling multi-processor virtual machine system provided by the invention;
Fig. 2 is the structural representation of processor Parallel Simulation module among Fig. 1;
Fig. 3 is the structural representation of memory management module among Fig. 1;
Fig. 4 be paralleling multi-processor virtual machine system provided by the invention when virtual CPU number during less than the actual processor number thread distribute synoptic diagram;
Fig. 5 be paralleling multi-processor virtual machine system provided by the invention when virtual CPU number during greater than the actual processor number thread distribute synoptic diagram;
Fig. 6 is the method for synchronous synoptic diagram of parallel virtual cpu thread in the paralleling multi-processor virtual machine system provided by the invention;
Fig. 7 is the service procedure figure of paralleling multi-processor virtual machine system provided by the invention.
Embodiment
The present invention will be further described in detail below in conjunction with accompanying drawing and example.
As shown in Figure 1, from the level of architecture, the applied computer system of the present invention comprises paralleling multi-processor virtual machine system 3, local operation system layer 4 and home server 5 from top to bottom.
Local operation system 4 can use any current main flow to support the operating system of SMP (as Windows, Linux).Home server 5 is physical basis of the present invention, it comprise p processor 51,52 ..., 5p, wherein 2≤p≤16.
Paralleling multi-processor virtual machine system 3 comprises virtual machine 1 and virtual machine internal operating system 2, and virtual machine internal operating system 2 operates on the virtual machine 1.Virtual machine internal operating system 2 is for supporting the operating system of SMP (symmetric multiprocessor), and it possesses the ability of supporting parallel processing.If use Windows, then Windows can directly support SMP.If use Linux, then need to recompilate the kernel of Linux, add its support option to SMP.
Virtual machine 1 is for the user provides virtual platform, and it comprises processor Parallel Simulation module 11, memory management module 12, interrupt control analog module 13 and peripheral hardware analog module 14.
Processor Parallel Simulation module 11 is used for the instruction that sink virtual machine internal operating system 2 is submitted to, is carried out after the translation.If instruction relates to memory read-write, the read-write operation signal will pass to memory management module 12.If processor Parallel Simulation module 11 is wanted handling interrupt, then look-at-me is sent to interrupt control analog module 13.
Interrupt control analog module 13 is responsible for the control and the management of the look-at-me in the virtual machine 1; It receives the external interrupt signal that transmits from peripheral hardware analog module 14 on the one hand, on the other hand with the 11 collaborative execution interrupt operations of processor Parallel Simulation module.
Peripheral hardware analog module 14 is responsible for simulation all peripheral hardware action and echo port access message, interrupts if cause, and then look-at-me is sent to interrupt control analog module 13 and handles.
Illustrate the concrete structure of processor Parallel Simulation module 11 and memory management module 12 below; persons skilled in the art can be according to content disclosed by the invention; implement technical scheme of the present invention with other multiple specific implementation method, protection scope of the present invention is not limited to the content of following example.
As shown in Figure 2, processor Parallel Simulation module 11 comprises query statement power function table 111, synchronization control module 112 and virtual cpu thread module 113.
Virtual cpu thread module 113 a dynamic construction n virtual cpu thread T
1, T
2..., T
n(3≤n≤17), the corresponding physical cpu of each virtual cpu thread.Virtual cpu thread T
1, T
2..., T
n(hereinafter to be referred as the virtual cpu thread) all is responsible for the behavior of a virtual cpu of simulation, and major function is the translation of instruction and the execution of command function.
All virtual cpu threads in the virtual cpu thread module 113 can obtain the binary code of the instruction that current virtual cpu will carry out by memory management module 12, and this binary code is translated into corresponding instruction number via the virtual cpu thread.After the virtual cpu thread was obtained translation instruction later number, query statement power function table 111 obtained the inlet of the power function of present instruction correspondence.Then, the corresponding power function of virtual cpu thread execution instruction is finished the present instruction specified action.
If present instruction relates to soft interruption or unusual, the virtual cpu thread will send to interrupt control analog module 13 to interrupt number.After interrupt control analog module 13 receives interrupt number, realize corresponding interrupt function, switch the context of the corresponding virtual cpu thread of this instruction simultaneously, it can be changed over to interrupting or abnormity processing according to interrupt number.
If the function of present instruction only is the oneself state that changes virtual cpu, corresponding actions is carried out the back is entered next bar instruction by same method above-mentioned implementation so.If the function of present instruction relates to the read-write to the physical address of internal memory, Du Xie operation will be delivered to memory management module 12 so.
Synchronization control module 112 collaborative virtual cpu thread modules 113 are coordinated the synchronous execution of all virtual cpu threads.
As shown in Figure 3, memory management module 12 comprises address judgment module 121 and accessing operation module 122.Behind the read-write operation that address judgment module 121 reception virtual cpu threads send, judge the related physical address of read-write operation.If the action that accessing operation module 122 is carried out memory access is so just directly given in the common memory address; If the port address of peripheral hardware mapping is then passed to peripheral hardware analog module 14 to the mapped port address, peripheral hardware analog module 14 retrieves the corresponding peripheral hardware of port and carries out read-write operation after obtaining corresponding port number.Accessing operation module 122 is handled the read-write requests of virtual cpu thread, guarantees the atomicity of twice access instruction.
If in the peripheral hardware of peripheral hardware analog module 14 simulations interrupt request is arranged, peripheral hardware analog module 14 will send to interrupt control analog module 13 to interrupt request.The IPQ that after the interrupt control analog module 13 execution respective handling interrupt number is put into interrupt control analog module 13, simultaneously, interrupt control analog module 13 will be provided with the context of virtual cpu thread 1, transfer to virtual cpu thread 1 and handle.
Below in conjunction with Fig. 4, Fig. 5 virtual cpu thread T of the present invention is described
1, T
2..., T
nThe principle that parallelization is carried out.
Virtual cpu thread T
1, T
2..., T
nParallelization to carry out be core ingredient of the present invention.Existing legacy system level dummy machine system generally indicates each CPU with array, allocates each virtual CPU timesharing with circulation then and moves on an independent physical cpu.And in the present invention, each virtual CPU uses a thread to realize, thus operating on the multiprocessor servers of can walking abreast simultaneously.
Virtual cpu thread T
1, T
2..., T
nIt is exactly the CPU simulation of threading.Furtherly, be exactly that each virtual cpu all uses a thread to encapsulate, each thread can be visited public memory management module 12, thereby realizes virtual SMP architecture.Further as shown in Figure 4, the number of supposing real physical cpu is p, virtual cpu thread T
1, T
2..., T
nNumber be less than or equal to the CPU number of actual physics, the virtual cpu process can be done man-to-man mapping with the CPU of physics.Like this, can reduce thread and between different CPU, switch the low drawback of cache hit rate that is caused.If the number of virtual CPU is greater than the number of actual physics CPU, local operation system 4 can guarantee each virtual cpu thread T as far as possible
1, T
2..., T
nManagement and running on the physical cpu that can both formerly once move.
As shown in Figure 5, the number of supposing real physical cpu is p, and the virtual CPU number of user is that (a wherein, b, p are positive integers to a*p+b, b＜p).Local operation system 4 can be the 1st, p+1, and 2p+1 ..., a*p+1 establishment virtual cpu thread is assigned on No. 1 physical cpu and moves.In like manner: the 2nd, p+2,2p+2 ..., a*p+2 virtual cpu thread is assigned on No. 2 physical cpus and moves.So, the virtual cpu thread will be divided into the p group, and every group has a or a+1 virtual cpu thread to run on the physical cpu.But it should be noted that: if following situation, the summation of user program process or number of threads is not as good as the number of virtual cpu, for example, current have 4 actual physical CPU, and the user has created 8 virtual cpu threads, 2 virtual cpu threads just arranged like this in operation on each true CPU.At this moment, if having only 2 user threads on virtual machine, to move just, and all concentrate and operate on the same virtual cpu thread.Local operation system 4 can not reschedule the virtual cpu thread yet.If this is because when not having task run on the virtual CPU thread, all can have an idle process to move thereon.Whether local operation system 4 basic there is no telling virtual cpu threads are idle.Therefore, operating system can be according to the virtual CPU thread of loading condition scheduling of virtual machine.That is to say that in case virtual CPU thread is created, it determines to move basically on same CPU, so can improve the hit rate of cache, reduce the cache synchronization overhead between the home server CPU, and the internal memory synchronization overhead, the travelling speed and the efficient of raising system.
In order to guarantee that virtual machine of the present invention can true(-)running under the situation of executed in parallel, the present invention proposes its parallel executing method of control.Comprise: the method for synchronous of parallel virtual cpu and the access control method of critical resource.
Further for the method for synchronous (as Fig. 6) of parallel virtual cpu, the present invention is each virtual cpu thread T
1, T
2..., T
nAll be provided with the transmission of a pair of message communicating and wait for operation; Simultaneously in all virtual cpu thread outer setting a synchronization control module 112.After the instruction of the intact bar number of stipulating of each virtual cpu thread execution, just send a notification message to synchronization control module.Oneself enter the Messages-Waiting operation subsequently.After the notification message of all CPU threads all was sent to synchronization control module 112, synchronization control module 112 was just to all virtual cpu thread T
1, T
2..., T
nSend respectively and continue to carry out message.Virtual cpu thread T
1, T
2..., T
nJust withdraw from wait, continue to carry out the next group instruction, so go round and begin again, the circulation running.Method for synchronous of the present invention makes all virtual cpu threads can both keep the instruction number error of relative execution within certain controlled scope.Guaranteed whole virtual machine correctness in logic like this.
In the access control method for critical resource, the critical resource of management required for the present invention comprises: the read-write to peripheral port is operated with the atomicity of twice access instruction.
Further, about read-write to peripheral port, when the some virtual cpu threads 1 in the virtual machine of the present invention when the memory address to the mapping of certain peripheral port carries out read-write operation, if there is another virtual cpu thread (as virtual cpu thread 2) also during this time identical port to be sent the operation of read-write, the conflict of these two operations will cause the mistake setting of data so, thereby the operation signal of 1 pair of peripheral hardware of virtual cpu thread is got muddled, read or write out illegal data, even read at all less than the data of wanting.Therefore, this virtual machine is simulated a plurality of virtual cpu thread T of operation simultaneously in executed in parallel
1, T
2..., T
nThe time, if virtual cpu thread will send the instruction to the I/O port operation, whether it at first must detection have other virtual cpu thread carrying out the I/O read-write operation.Be exactly whether the function that detects read-write operation on the virtual i/o bus is locked by other virtual cpu thread furtherly, if have then wait for that it discharges the entitlement to this lock, if do not have or other virtual cpu thread has discharged this lock, this virtual cpu thread is just carried out this lock and is added latching operation so.Then carry out read-write operation.Discharge this lock behind the end of operation.So so both guaranteed that each I/O read-write operation can both become an atomic operation and do not interrupted by other operation, can make each virtual cpu thread obtain the read-write power of I/O by competition again.Guaranteed certain fairness.
About the atomicity operation of the instruction of twice memory access, the present invention adopts and judges that the back locks to memory read-write and realize.Further specifically, the instruction of twice memory access is meant the read-write that relates to twice pair of internal memory in the operation of some instruction.As the INC instruction, if the data of a certain memory address are carried out the INC operation, this operation will at first be read in the content in this internal memory in the register of CPU, subsequently the numerical value in the register is added one, at last new data is write original memory address again.If the operation that the instruction that moves on other the virtual cpu thread when the instruction that this class relates to twice memory access is carried out has also been carried out read-write to this memory address so or read dirty data, or write and lose.
In order to prevent to read dirty data and write the generation of losing, the specific practice that the present invention takes is: judge at first whether next the bar instruction that will carry out on the virtual cpu thread is the instruction of twice memory access of this class, if then memory read-write is locked, behind the end of operation this lock is lifted a blockade.Do not relate to the instruction of twice access memory for other,, will detect at first whether memory read-write is locked if they need read/write memory.If no, expression does not relate to the instruction of twice access memory this moment to be carried out, and can carry out.If find that memory read-write is locked, expression this moment just in time has the instruction of twice memory access of a design carry out, then it will wait in the original place cycle detection, be disengaged up to the Read-Write Locks of internal memory, till the instruction that relates to twice memory access executes, continue normal the execution then.The atom that the present invention has adopted above method to avoid relating to the instruction of twice memory access is carried out and is interrupted, and has guaranteed that the operation of this type of instruction can both accurately realize.
Issuable conflict on critical resource access when the present invention utilizes above-mentioned method effectively to control the execution of virtual cpu thread parallel.In conjunction with the method for synchronous of above-mentioned parallel virtual cpu, the present invention has guaranteed virtual machine in logic correct execution after parallelization.
Total system service procedure of the present invention as shown in Figure 7.Need use parallel multiprocessor virtual machine provided by the present invention as the user.If use for the first time, at first should edit the configuration script that native system provides, specify model, the number of the processor of required simulation, memory size, the information such as address of disk size and specification, virtual network.The operating system of the support SMP that meets consumers' demand is installed for virtual machine then.The user directly starts virtual machine of the present invention then, just can use this parallel virtual machine system as any real computing machine of use after waiting the os starting in the virtual machine.
If not using for the first time, the user can directly start virtual machine of the present invention, and waiting behind the os starting in the virtual machine just can be as any real computing machine trial edition parallel virtual machine system of use.
If the virtual hardware configuration the when user used the first time is dissatisfied, the user can at first stop the execution of virtual machine of the present invention, revise configuration script that native system provides and all meet user's demand, restart this virtual machine and can continue to use up to every configuration.
The task that virtual machine among the present invention will be distributed to the user virtual cpu automatically is unit executed in parallel on real hardware server with virtual CPU, thereby utilize the computational resource of multiprocessor on the existing hardware efficiently, for the user provides high performance service.
Claims (3)
1, a kind of paralleling multi-processor virtual machine system is characterized in that: this system comprises virtual machine (1) and virtual machine internal operating system (2);
Virtual machine internal operating system (2) adopts the operating system of supporting symmetric multiprocessor, goes up operation at virtual machine (1);
Virtual machine (1) is for the user provides virtual platform, and it comprises processor Parallel Simulation module (11), memory management module (12), interrupt control analog module (13) and peripheral hardware analog module (14);
Processor Parallel Simulation module (11) is used for the instruction that sink virtual machine internal operating system (2) is submitted to, is carried out after the translation; If instruction relates to memory read-write, the read-write operation signal will pass to memory management module (12); If processor Parallel Simulation module (11) is wanted handling interrupt, then look-at-me is sent to interrupt control analog module (13);
Memory management module (12) is responsible for the read-write operation management of all internal memories, and memory management module sends the peripheral port address that receives to peripheral hardware analog module (14), and the result of memory read-write operation is fed back to processor Parallel Simulation module (11);
Peripheral hardware analog module (14) is responsible for simulation all peripheral hardware action and echo port access message, interrupts if cause, and then look-at-me is sent to interrupt control analog module (13) and handles;
Interrupt control analog module (13) is responsible for the control and the management of the look-at-me in the virtual machine (1); It receives the external interrupt signal that transmits from peripheral hardware analog module (14) on the one hand, on the other hand with the collaborative execution of processor Parallel Simulation module (11) interrupt operation.
2, system according to claim 1 is characterized in that: processor Parallel Simulation module (11) comprises query statement power function table (111), synchronization control module (112) and virtual cpu thread module (113);
Virtual cpu thread module (113) is used to simulate the behavior of CPU, makes up n virtual cpu thread T
1, T
2..., T
n, wherein, 1≤n≤17, the corresponding physical cpu of each virtual cpu thread;
Query statement power function table (111) is used for the corresponding tables of storage instruction and power function;
The collaborative virtual cpu thread module (113) of synchronization control module (112) is coordinated the synchronous execution of all virtual cpu threads.
3, system according to claim 1 and 2 is characterized in that: memory management module (12) comprises address judgment module (121) and accessing operation module (122); Wherein,
Behind the read-write operation that address judgment module (121) reception virtual cpu thread sends, judge the related physical address of read-write operation; If the action that accessing operation module (122) is carried out memory access is so just directly given in the common memory address; If the port address of peripheral hardware mapping is then passed to peripheral hardware analog module (14) to the mapped port address, peripheral hardware analog module (14) retrieves the corresponding peripheral hardware of port and carries out read-write operation after obtaining corresponding port number;
Accessing operation module (122) is handled the read-write requests of virtual cpu thread, guarantees the atomicity of twice access instruction.
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| CN101908967B (en) * | 2009-06-02 | 2014-02-19 | 百度在线网络技术（北京）有限公司 | Configuration method and system of Linux virtual server |
| CN101593134B (en) * | 2009-06-29 | 2012-05-30 | 北京航空航天大学 | Method and device for allocating CPU resources of virtual machine |
| WO2011046089A1 (en) * | 2009-10-16 | 2011-04-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Simulation method, system, and program |
| CN101788919B (en) * | 2010-01-29 | 2013-08-14 | 中国科学技术大学苏州研究院 | Chip multi-core processor clock precision parallel simulation system and simulation method thereof |
| CN101901207B (en) * | 2010-07-23 | 2012-03-28 | 中国科学院计算技术研究所 | Operating system of heterogeneous shared storage multiprocessor system and working method thereof |
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| US8924596B1 (en) * | 2013-12-06 | 2014-12-30 | Concurrent Ventures, LLC | System and method for dividing and synchronizing a processing task across multiple processing elements/processors in hardware |
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