CN100571092C - Method for forming pseudo mask register in the scrambling code phase deviation - Google Patents
Method for forming pseudo mask register in the scrambling code phase deviation Download PDFInfo
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- CN100571092C CN100571092C CNB2004100961575A CN200410096157A CN100571092C CN 100571092 C CN100571092 C CN 100571092C CN B2004100961575 A CNB2004100961575 A CN B2004100961575A CN 200410096157 A CN200410096157 A CN 200410096157A CN 100571092 C CN100571092 C CN 100571092C
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Abstract
The invention discloses method for forming pseudo mask register in a kind of communication field scrambling code phase deviation, at first seek survival into the initial residue value of pre-segmentation, then the order of the clock unit number of skew and generator polynomial being sent into comparator compares, after respective handling, generate the address value of tabling look-up for the first time, judge then again, operation such as redirect, the value of temporary register is sent to the MASK register; PN code generator register value and the step-by-step of MASK register value " with ", then " with " after all " position " value moulds two add together, export the PN code value after biased the moving; PN sign indicating number of every cyclic shift generates register value and just generates a new PN code value; Repeat above-mentioned with cyclic shift action, generate complete PN sign indicating number sequence.The present invention has overcome many, the ineffective shortcoming that expends time in that prior art exists, and can save the phase deviation time, improve system effectiveness.
Description
Technical field
The invention belongs to field of mobile communication, relate in particular to the implementation method that is used for code division multiple access, broadband CDMA system scrambling code phase deviation.
Background technology
In the mobile communication technology in modern times, code division multiple access and Wideband CDMA Technology more and more are subjected to using widely, and wherein signal scrambling technique is an important step of its realization.Scrambler is that (english abbreviation is one group of pseudo noise code: the PN sign indicating number), in system realizes, usually need scrambler sequence is carried out phase deviation (promptly postponing displacement), and often require the fast as far as possible sequence that produces after the phase deviation in realization.In the prior art, PN sign indicating number sequence after the generation phase deviation mainly adopts " pure displacement method ", this method is by the acquisition that directly is shifted of the initial value before the shift register in the PN code generator skew, this method realizes simple, but when phase deviation is big, its consumed time also is very many, thus very big influence the operating efficiency of system.
Summary of the invention
Technical problem to be solved by this invention is many, the ineffective shortcoming that expends time in that prior art exists, in the hope of propose a kind ofly to save the phase deviation time, pseudo mask register (MASK register) generation method in the scrambling code phase deviation of raising system effectiveness.
In the scrambling code phase deviation of the present invention in the method for forming pseudo mask register, " g (x) " represents generator polynomial, the clock unit number of " K " representative skew, " M " represents the order of generator polynomial g (x), " N " represents every segment length after the segmentation, N will satisfy " smaller or equal to M ", may further comprise the steps:
A) seek survival into the initial residue value of pre-segmentation, the generation method is as follows:
1) evaluator a
N-1X
M+N-1+ a
N-2X
M+N-2+ ... + a
0X
MDivided by the residue value of g (x), a
N-1a
N-2A
1a
0From 00 ... 00 to 11 ... 11 totally 2
NThe state of kind;
2) with a
N-1a
N-2A
1a
0Be the address, residue is value, totally 2
NROM is gone in the programming of the state of kind, and generating a bit wide is 2 for the M degree of depth
NInitial R OM table;
B) K and M are sent into comparator and compare,, jump to j if K less than M, then writes value " 1＜＜K " in the MASK register) carry out; As K more than or equal to M, the number of times that generation need be tabled look-up, generating formula is [K-M+N]/N, the number of times that needs are tabled look-up deposits temporary register J in, counter O reset;
C) generate the address value table look-up for the first time, computing formula is [1＜＜((K-M) %N)], and the address value of tabling look-up is for the first time deposited in temporary register Address0;
D) from the Address0 register, read address value, from the ROM table, find the Address0 value corresponding and deposit temporary register TempVal0 in;
E) counter adds 1, and whether the value of judging counter is set up as condition less than J, then carries out following steps, otherwise, then jump to i) carry out;
F) register TempVal0 value " M-N " position that moves to right is deposited in temporary register Address as reading the address, to be the address find value corresponding from ROM shows deposit temporary register TempVal in the Address value;
G) move to left the value of TempVal0 behind the N position and M ' b1 carries out AND-operation, and then and the value of TempVal carry out the nonequivalence operation on M rank, the result of nonequivalence operation is deposited in register TempVal0, and M ' b1 represents the binary register on M rank, and the value of register is " 1 ";
H) counter adds 1, and whether the value of judging counter is set up as condition less than J, then jumps to f) carry out, on the contrary then carry out following steps;
I) value of TempVal0 is sent to the MASK register;
J) PN code generator register value and the step-by-step of MASK register value " with ", then " with " after all " position " value moulds two add together, export the PN code value after biased the moving;
K) PN sign indicating number of cyclic shift generates register value;
L) repeat j) and k), generate complete PN sign indicating number sequence.
Adopt prior art described " pure displacement method ", when postponing K time, need to consume the PN sign indicating number sequential value after K clock unit could be exported displacement, and adopt the method for the invention, only need carry out [K-M+N]/table look-up for N time getting final product, can save about K-(K-M)/N-1 clock unit.As can be seen, in terms of existing technologies, the present invention can greatly save the scrambling code phase deviation time, improves the operating efficiency of system.
Description of drawings
Fig. 1 is a PN sign indicating number sequence generating structure schematic diagram.
Fig. 2 is the method for the invention flow chart.
Embodiment
Below in conjunction with the drawings and specific embodiments the method for the invention is further described.
Fig. 1 is a PN sign indicating number sequence generating structure schematic diagram.101,102---expression mould two adds; 103---expression and operation; 104---the MASK register, total M position, initial condition is 0 entirely; 105---the PN sign indicating number generates status register, total M position; 106---the PN sign indicating number sequence of skew does not take place; 107---the PN sign indicating number sequence after the skew.
According to the principle of m sequence, the output that PN sign indicating number sequence cycles postpones to be shifted is that the mould two of some generation status register adds sum, determines to claim pseudo mask register (be called for short the MASK register, parts 104 among the figure) by the register which status register participation mould two adds.Supposing need to postpone carry digit be i, and PN sign indicating number generator polynomial is g (x), then according to the principle of m sequence, and x
iThe residue of mod (g (x)) is exactly the mask register value, the value step-by-step in register in the PN code generator (parts 105 among the figure) value and the MASK register with, at last with after all " position " value moulds two add together, the result that mould two adds is exactly a certain of PN sign indicating number sequence after being shifted.The method key point is exactly how to generate the MASK value fast, and the present invention will adopt " segmentation look up table technique " to realize the generation of MASK register value fast.
To be described in detail (flow process as shown in Figure 2) to the method for utilizing " segmentation look up table technique " to generate the MASK register value below." g (x) " represents generator polynomial in this section is described, the clock unit number of " K " representative skew, and " M " represents the order of generator polynomial g (x), after " N " represents segmentation, every segment length (N will satisfy " smaller or equal to M "):
A) at first, seek survival into the initial residue value of pre-segmentation, the generation method is as follows:
1) evaluator a
N-1X
M+N-1+ a
N-2X
M+N-2+ ... + a
0X
MDivided by the residue value of g (x), a
N-1a
N-2A
1a
0From 00 ... 00 to 11 ... 11 totally 2
NThe state of kind;
2) with a
N-1a
N-2A
1a
0Be the address, residue is value, totally 2
NROM is gone in the programming of the state of kind, and generating a bit wide is 2 for the M degree of depth
NInitial R OM table;
B) K and M are sent into comparator and compare,, jump to j if K less than M, then writes value " 1＜＜K " in the MASK register) carry out; As K more than or equal to M, the number of times that generation need be tabled look-up, generating formula is [K-M+N]/N, the number of times that needs are tabled look-up deposits temporary register J in, counter O reset;
C) generate the address value table look-up for the first time, computing formula is [1＜＜((K-M) %N)], and the address value of tabling look-up is for the first time deposited in temporary register Address0;
D) from the Address0 register, read address value, from the ROM table, find the Address0 value corresponding and deposit temporary register TempVal0 in;
E) counter adds 1, and whether the value of judging counter is set up as condition less than J, then carries out following steps, otherwise, then jump to i) carry out;
F) register TempVal0 value (M-N) position that moves to right is deposited in temporary register Address as reading the address, to be the address find value corresponding from ROM shows deposit temporary register TempVal in the Address value;
G) move to left the value of TempVal0 behind the N position and M ' b1 carries out AND-operation, and then and the value of TempVal carry out the nonequivalence operation on M rank, the result of nonequivalence operation is deposited in register TempVal0;
H) counter adds 1, and whether the value of judging counter is set up as condition less than J, then jumps to f) carry out, on the contrary then carry out following steps;
I) value of TempVal0 is sent to the MASK register;
J) PN code generator register value and the step-by-step of MASK register value " with ", then " with " after all " position " value moulds two add together, export the PN code value after biased the moving;
K) PN sign indicating number of cyclic shift generates register value;
L) repeat j) and k), generate complete PN sign indicating number sequence.
Further combined with specific embodiment the method for the invention is described below.
Suppose K=25, g (x)=x
8+ x
3+ 1, M=8, N=8:
1) seek survival into the initial residue value of pre-segmentation, the generation method is as follows:
Evaluator a
7X
15+ a
6X
14+ ... + a
0X
8Divided by the residue value of g (x), a
7a
6A
1a
0From 00 ... 00 to 11 ... 11 states in totally 256;
With a
7a
6A
1a
0Be the address, residue is value, and making a bit wide is that 8 degree of depth are 256 Initial R OM table;
2) ask the number of times that need table look-up, computing formula is [K-(M-1)+(N-1)]/N (this example=3);
3) generate the address value Address0 table look-up for the first time, computing formula is [1＜＜((K-M) %N)] (this example=2);
4) from register, read address value Address0 (this example=2), from the ROM table, read the state value TempVal0 (this example=18) of Address0 correspondence;
5) move to right (M-N) (this example=0) of TempVal0 position as reading address Address (this example=18), from the ROM table, read the state value TempVal (this example=130) of Address (this example=18) correspondence;
6) the value of TempVal0 (this example=18) move to left after 8 with M ' b1 (this example=8 ' b1) with, then and the value of TempVal (this example=130) carry out the XOR on 8 rank, the result of XOR is deposited in register TempVal0 (this example=130);
7) move to right (M-N) (this example=0) of TempVal0 position as reading address Address (this example=130), from the ROM table, read the state value TempVal (this example=182) of Address (this example=130) correspondence;
8) the value of TempVal0 (this example=130) move to left after 8 with M ' b1 (this example=8 ' b1) with, then and the value of TempVal (this example=182) carry out the XOR on 8 rank, the result of XOR is deposited in register TempVal0 (this example=182);
9) TempVal0 is sent into the MASK register.
10) PN code generator register value and the step-by-step of MASK register value " with ", then " with " after all " position " value moulds two add together, export the PN code value after biased the moving.
From instantiation as can be seen, adopt " pure displacement method " to need 25 clock cycle of cost, and adopt this method only need look into table 3 times, approximately spend 3 clock cycle, can save for about 7/8 time.
Claims (1)
1, method for forming pseudo mask register in a kind of scrambling code phase deviation, it is characterized in that, " g (x) " represents generator polynomial, the clock unit number of " K " representative skew, " M " represents the order of generator polynomial g (x), " N " represents every segment length after the segmentation, and N will satisfy " smaller or equal to M ", may further comprise the steps:
A) seek survival into the initial residue value of pre-segmentation: evaluator a
N-1X
M+N-1+ a
N-2X
M+N-2+ ...+a
0X
MDivided by the residue value of g (x), with a
N-1a
N-2... a
1a
0Be the address, residue is value, totally 2
NROM is gone in the programming of the state of kind, and generating a bit wide is 2 for the M degree of depth
NInitial R OM table;
B) K and M are sent into comparator and compare,, jump to j if K less than M, then writes value " 1＜＜K " in the MASK register) carry out; More than or equal to M, generate the number of times that need table look-up according to formula [K-M+N]/N as K, the number of times that needs are tabled look-up deposits temporary register J in, counter O reset;
C) according to formula 1＜＜((K-M) %N) generate the address value table look-up for the first time, the address value of tabling look-up for the first time deposited in temporary register Address0;
D) from the Address0 register, read address value, from the ROM table, find the Address0 value corresponding and deposit temporary register TempVal0 in;
E) counter adds 1, and whether the value of judging counter is set up as condition less than J, then continue, otherwise, then jump to i) carry out;
F) register TempVal0 value " M-N " position that moves to right is deposited in temporary register Address as reading the address, to be the address find value corresponding from ROM shows deposit temporary register TempVal in the Address value;
G) move to left the value of TempVal0 behind the N position and M ' b1 carries out AND-operation, and then and the value of TempVal carry out the nonequivalence operation on M rank, the result of nonequivalence operation is deposited in register TempVal0, and M ' b1 represents the binary register on M rank, and the value of register is " 1 ";
H) counter adds 1, and whether the value of judging counter is set up as condition less than J, then jumps to f) carry out, on the contrary then carry out following steps;
I) value of TempVal0 is sent to the MASK register;
J) PN code generator register value and the step-by-step of MASK register value " with ", then " with " after all " position " value moulds two add together, export the PN code value after biased the moving;
K) PN sign indicating number of cyclic shift generates register value;
L) repeat j) and k), generate complete PN sign indicating number sequence.
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|---|---|---|---|
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| CN101110015B (en) * | 2007-08-29 | 2012-05-23 | 中国人民解放军国防科学技术大学 | Data reversal bucket shaped shift method based on mask code |
| US8848913B2 (en) | 2007-10-04 | 2014-09-30 | Qualcomm Incorporated | Scrambling sequence generation in a communication system |
| US8923249B2 (en) | 2008-03-26 | 2014-12-30 | Qualcomm Incorporated | Method and apparatus for scrambling sequence generation in a communication system |
| CN105049147A (en) * | 2015-05-28 | 2015-11-11 | 上海晨思电子科技有限公司 | Device and method for quickly jumping to state of long code generator |
| CN112861154A (en) * | 2021-02-24 | 2021-05-28 | 中国科学院计算技术研究所 | SHA algorithm execution method, storage medium and electronic device for data flow architecture |
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Effective date of registration: 20151112 Address after: Dameisha Yantian District of Shenzhen City, Guangdong province 518085 Building No. 1 Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Nanshan District, Guangdong high tech Industrial Park, science and Technology Industrial Park, ZTE building, block A, layer 6, layer Patentee before: ZTE Corp. |
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Application publication date: 20060607 Assignee: Xi'an Chris Semiconductor Technology Co.,Ltd. Assignor: SANECHIPS TECHNOLOGY Co.,Ltd. Contract record no.: 2019440020036 Denomination of invention: Method for forming pseudo mask register in scrambling code phase deviation Granted publication date: 20091216 License type: Common License Record date: 20190619 |
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Granted publication date: 20091216 Termination date: 20211130 |