CN100570572C - The error detection and correction system that the tiny satellite star load computer data storage is used - Google Patents
The error detection and correction system that the tiny satellite star load computer data storage is used Download PDFInfo
- Publication number
- CN100570572C CN100570572C CNB2008101122725A CN200810112272A CN100570572C CN 100570572 C CN100570572 C CN 100570572C CN B2008101122725 A CNB2008101122725 A CN B2008101122725A CN 200810112272 A CN200810112272 A CN 200810112272A CN 100570572 C CN100570572 C CN 100570572C
- Authority
- CN
- China
- Prior art keywords
- circuit
- memory
- way
- address
- interface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The error detection and correction system that the tiny satellite star load computer data storage is used belongs in the spationautics computer memory technical field in the microsatellite, it is characterized in that, contain: static memory memory assembly and on-site programmable device FPGA, this FPGA contains: the Hamming error correction circuit, the triplication redundancy decision circuit, two two-way three-state gates, address logic circuit and mode control circuit, address contents according to outside central processing unit, mode control circuit is selected the Hamming error correction, triplication redundancy judgement and zero defect are controlled any in three kinds of patterns, and by the data-signal of two two-way three-state gates to the central processing unit input, according to the storage space that address logic circuit disposed that is subjected to mode control circuit control, the memory module of being made up of 12 static memory storeies carries out read-write operation.Because the present invention has done flexible and adjustable grouping to the memory headroom of internal memory memory assembly respectively by three kinds of patterns, thereby can carry out flexible allocation according to error correction mode, has made full use of internal memory.
Description
Technical field
The single particle effect that the present invention is directed to the outer space generation has been realized a kind of data-storage system EDC error detect correction technology that can be used for tiny satellite star load computer, belongs to microsatellite (Micro Satellite) and aerospace electron technology (Space Avionics) field.
Background technology
Radiation is one of subject matter of facing in space environment of spacecraft.Various high energy particles in the space (comprising high energy proton, neutron, α particle, heavy ion etc.) have very high kinetic energy, by the time may influence the logic state of semiconductor circuit, even semiconductor material is caused permanent damage.Single high energy particle is referred to as single particle effect to the influence that the electron device function produces.Wherein, need special concern cause memory contents to exist ' 0 ', the single-particle inversion that changes between ' 1 ' (SEU) problem.
The research and development thinking of microsatellite is short period, low cost, employs new technology, handy business level electron device on therefore a large amount of employings market.These devices have characteristics such as high density, low-power consumption, low cost, extendability are strong, but usually not through strict radioresistance test, also do not adopt perfect radiation hardening process.The radioresistance problem that solves microsatellite need be taked comprehensive measure, comprises integral protection, design redundancy or the like, specifically then adopts methods such as coding, backup to utilize information redundancy to deal with the SEU phenomenon usually for data-carrier store.Match with physical memory devices, the circuit of realizing above-mentioned error detection/correction function be exactly the data error of tiny satellite star load computer system detect and correct module (Error Detection AndCorrection, EDAC).The error correction and detection scheme of spaceborne data-storage system is the single particle effect that produces at the outer space, reaches the purpose that detects and correct the data storage random error between CPU and the internal memory, is an important ring of data processing on the star.
In 2002 08 phases " application of electronic technology ", in the article " utilizing the variable satellite data memory error correction system of FPGA implementation pattern ", the coordination memory configurations had once been proposed to realize multimodal EDC error detect correction scheme, structure is as shown in Figure 1.This article does not have concrete operational means only in the conceptual phase, and the present invention is intended to this paper is transformed achievement.
In this article, mention compatible three times of redundant decision circuits and hamming code and error correction circuit as shown in Figure 2, be positioned at same the 16bit memory modules on the address bus by 3 and form the configuration of internal memory.Each memory modules sheet separately selects its high byte or low byte, controls the error correction and detection pattern of EDAC module with control bus.Each memory modules is by chip selection signal ah, al, and bh, bl, ch, the control of cl, the memory modules that 6 width are in fact just arranged is 8bit just can be visited separately.The data line of 48bit (3x16bit) all inserts the EDAC control module.
When system works during in pattern 0, ah, al, bh, bl, ch, cl is driven by identical chip selection signal.So just need a 3x16bit redundancy memory space.When system works during in pattern 1, ah, al, one group of bh, bl, ch, one group of cl is driven by identical chip selection signal respectively, has constituted two independently 16+8bit storage spaces.For (22,16) Hamming code, the actual use in each space 16+6bit.In this configuration, address space doubles for 0 time than pattern.System works when pattern 2 times, ah, one group of al, bh, one group of bl, ch, one group of cl is driven by identical chip selection signal respectively, has constituted three independently 16bit storage spaces.Memory address space under this configuration increases twice than under the TMR pattern.
In the configuration mode of the present invention, this article is mentioned before having reached, and the address decoding of sheet choosing is all finished in the EDAC control module, and transparent fully to software.
Summary of the invention
The invention provides a kind of tiny satellite star load computer data storage EDC error detect correction system, hardware is formed the field programmable device that comprises 1 main EDC error detect correction function of carrying, 12 common static memory storage in the environment of cosmic space, and standard patches interface, reach the purpose of plug and play, thereby satisfy of the requirement of the moonlet of different aerial missions reliability.
The invention is characterized in, contain field programmable device and static memory memory assembly, wherein:
The static memory memory assembly, form by 12 static memory storeies, be divided into into three groups, every by 4 static memory storeies compositions, each group # is respectively A, B and C, described 12 static memory storeies are provided with: two-way 48 memory data interfaces, the low order address input interface, have A0～A17 totally 18 address input ends link to each other with the low order address output interface of outside central processing unit, the chip selection signal input interface contains 12 chip selection signal input end: CE0～CE3, every 1 chip selection signal input end, and read to enable and write to enable input interface;
Field programmable device, contain: Hamming error correction circuit, triplication redundancy decision circuit TMR, the first two-way three-state gate, the second two-way three-state gate, mode control circuit and address logic circuit, wherein:
The Hamming error correction circuit, adopt the Hamming code error correction mode, add 6 redundanat codes with 16 bit data, totally 22 bit data realize, take 22 data lines, redundancy backup becomes two parts, its form is 22+0000+22, described Hamming error correction circuit is provided with: the first two-way 16 bit data IO interface, chip selection signal input interface and the second two-way 16 bit data IO interface, when writing data, the common write memory address space of the redundanat code of data, decoding and realization EDC error detection and correction when reading of data
Triplication redundancy decision circuit TMR adopts the hardware redundancy method of majority voting to realize EDC error detection and correction, and this TMR circuit is provided with: the first two-way 16 bit data IO interface, chip selection signal input interface and the second two-way 16 bit data IO interface,
The first two-way three-state gate, be provided with: with the two-way 16 bit data IO interface of 16 bit data IO interface interconnection in the outside central processing unit, two respectively with described Hamming error correction circuit, the two-way 16 bit data IO interface of triplication redundancy decision circuit a certain two-way 16 bit data IO interface interconnection separately, and read-write operation signal input interface, the described first two-way three-state gate is sent into described outside central processing unit to 16 bit data of being read by described Hamming error correction circuit or described triplication redundancy decision circuit according to the read-write operation instruction of input under chip selection signal control separately, perhaps under described chip selection signal control, 16 bit data of described outside central processing unit input are write described Hamming error correction circuit or described triplication redundancy decision circuit
The second two-way three-state gate is provided with: two second two-way 16 bit data IO interface, be connected respectively to described Hamming error correction circuit and the triplication redundancy decision circuit second two-way 16 bit data IO interface separately, and also be provided with; Two-way 48 bit data IO interface, and read a little control signal input interfaces, be connected to the two-way 48 bit data IO interface of described static memory memory assembly, so that be input to described static memory memory assembly under the write control signal control again after 16 bit data from the input of affiliated Hamming error correction circuit or described triplication redundancy decision circuit are backed up into 3 parts, or under read control signal control, from described static memory memory assembly, read
Address logic circuit, be provided with: the address signal input interface, the address wire A18 of described central processing unit～A22 links to each other with described address signal input interface, also be provided with: read enable signal nWE, write two read-writes of enable signal n0E and enable control signal output ends, be provided with Memory slice again and select signal output interface, link to each other with described static memory memory assembly, sheet choosing with every 12 static memories of 12 line traffic controls, most-significant byte and least-significant byte with every static memory storer of 6 line traffic controls, described outside central processing unit is implemented in the function of config memory address under the different mode by the address logic circuit of field programmable device inside, total following three kinds of described pattern: pattern 0 is the triplication redundancy decision pattern, pattern 1 is the Hamming error correction mode, pattern 2 is the zero defect control model, for pattern 0, described outside central processing unit is divided into 3 groups to described static memory storer by address wire A18 and A19 by this address logic circuit, every group 4 * 16, for pattern 1, by this address logic circuit described static memory storer is divided into two groups with address wire A20, every group 4 * 22, under described three kinds of different patterns, all use same read-write enable signal to drive
Mode control circuit, be provided with the mode select signal input interface, described outside central processing unit is connected to this mode select signal input interface by address wire A23 and A24, address wire A23 and A24 are associative modes 0 for " 00 ", " 01 " associative mode 1, " 10 " associative mode 2, also be provided with: the chip selection signal output port, select control line to be connected to the chip selection signal input end of described Hamming error correction circuit and triplication redundancy decision circuit by sheet respectively, also be provided with: the model selection control signal output ends of address logic circuit under being used to control, and two be respectively applied for control first, the mode select signal output terminal of the second two-way three-state gate, described mode control circuit is according to the content of address wire A23 and A24, the control address logical circuit makes its allocate memory space in view of the above, simultaneously, gating is opened two two-way three-state gates more respectively and is carried out read-write operation the sheet choosing of the Hamming error correction circuit or the triplication redundancy decision circuit of each pattern.
The workflow of native system as shown in Figure 4, realized based on the variable data-storage system of the error detection/correction mode of field programmable device, the internal storage location use-pattern of distributing according to the selection of pattern, make this system can require conversion error detection/correction scheme according to difference to the data reliability, made full use of memory headroom, improved the dirigibility of data-storage system greatly, and realized transparent and pattern may command software.
Description of drawings
Fig. 1 is variable memory configurations synoptic diagram: described field programmable device uses chip XCV200, and described static memory storer uses chip cy62146v.
Fig. 2 is the system construction drawing of variable error correction scheme.
Fig. 3 is the physical memory cell hardware structure diagram.
Fig. 4 is EDC error detect correction EDAC system works flow process figure.
Fig. 5 is a triplication redundancy decision circuit workflow.
Fig. 6 is that triplication redundancy decision circuit software is realized.
Fig. 7 is a Hamming code error correction circuit workflow.
Fig. 8 is that Hamming code error correction circuit software is realized.
Embodiment
Native system need cooperate the central processing unit collaborative work of concrete spaceborne computer, and its interface need be drawn the data bus line of this processor, address bus, and control bus.For possessing versatility, native system need be drawn 16 single data buses of ppu, 25 address buss, 3 control buss, wherein the read-write state of control line connection field programmable device is indicated, is read to enable and write to enable, and the model selection control line provides in the mode of high address line.
In native system inside, from the line that ppu is drawn, low order address line A0 to A17 is connected on the static memory in the native system, and other lines all are connected on the field programmable device in the native system.16 position datawire Dinout (0～15) are expanded into Dinouta (0～15) via field programmable device, Dinoutb (0～15), 48 of Dinoutc (0～15), be connected on the static memory assembly, 12 static memory storage numberings are respectively A (0～3), B (0～3), C (0～3) here.
Native system internal circuit functional structure is formed as shown in Figure 1, mainly comprises Hamming error correction circuit and three times of redundant decision circuits, mode control circuit, address logic circuit.Preceding two circuit are respectively two kinds of error correction circuits under the different mode, and mode control circuit is used to control the selection and the switching of different mode, and address logic circuit is used for the address logic of allocate memory storer.
Like this, on the one hand, native system can be worked under three kinds of patterns, is respectively 0, three times of redundant decision pattern of pattern, adopts the method error correction of majority voting; Pattern 1, the Hamming error correction mode adopts the error correction of existing Hamming code technology; Pattern 2, zero defect control model, the function of no EDC error detection and correction.On the other hand, the memory address sky disposes according to the selection of pattern, thereby satisfies the requirement of different aerial missions to memory headroom.
The native system inner function circuit is described below:
Carry out encoding operation when (1) this circuit application Hamming code algorithm of Hamming error correction circuit writes data, carry out decode operation during reading of data, thereby realize error detection and error correction.The sheet choosing of this circuit is connected on the mode control circuit, and 16 bit data bus of being drawn by processor are connected on the Hamming error correction circuit by the first two-way three-state gate, in this circuit inside, is that 16 bit data are added 6 redundanat codes, takies 22 data lines.Redundancy backup becomes 2 parts, with the form of " 22+0000+22 ", by the second two-way three-state gate, is connected on the static memory storer via 48 position datawires once more.When writing data, data and redundanat code be the write memory address space together; During reading of data, decoding also realizes EDC error detection and correction, and detailed process is introduced in the software realization flow.
The hardware redundancy method of (2) three times of these circuit application majority voting of redundant decision circuit realizes error correction, data are write fashionable, write static memory storer A, B, C simultaneously, during reading of data, with the contrast of three piece of data,, then read the result if all consistent, if inconsistent, get most last output results of two conducts identical in three data that promptly get.The sheet choosing of this circuit is connected on the mode control circuit, 16 bit data bus of being drawn by processor are connected on three times of redundant decision circuits by the first two-way three-state gate, become 3 parts to be 48 bit data 16 bit data redundancy backups in this circuit inside, after the second two-way three-state gate, be connected on the static memory memory assembly via 48 position datawires.When writing data, same piece of data is written in 3 groups of static memory storeies redundantly; During reading of data, realize the result of majority vote, detailed process is introduced in the software realization flow.
(3) mode control circuit two root mode control lines are provided by a high position two bit address line A23 and the A24 of processor, output is the link address logical circuit respectively, the choosing of the sheet of pattern 0 and pattern 1, and the one the second two-way three-state gates of using in these two kinds of pattern read-write processes.The content of high two bit address A23 and A24 is respectively: 0, three times of redundant decision pattern of " 00 " associative mode: " 01 " associative mode 1, Hamming error correction mode; " 10 " associative mode 2, the zero defect control model.
Mode control circuit when writing data according to the content of these two address wires, send mode signal to address logic circuit on the one hand, make it according to this mode signal allocate memory space, simultaneously on the other hand, the choosing of the sheet of the circuit of gating associative mode, and the one the second two-way three-state gates of opening these circuit two ends carry out write operation.During reading of data, mode signal is provided by address wire A23 and A24, mode control circuit is passed to address logic circuit with this signal on the one hand, be addressed to corresponding address space, simultaneously on the other hand, the choosing of the sheet of the circuit of gating associative mode, and the one the second two-way three-state gates of opening these circuit two ends carry out read operation.
(4) address logic circuit A23 and A24 are used for (3) mode control circuit.A18 to A22 is connected on the native system, realizes the function of config memory address by the address logic circuit of inside.Wherein, pattern 0 uses A18 and A19 coordinates 3 groups of static memory storeies, and pattern 1 is used the 21st address wire after A20 enlarges as memory headroom, and pattern 2 is removed above-mentioned address wire and also used A21 and A22, the 22nd and 23 address wire after enlarging as memory headroom.
The lower end that address logic circuit output connects the static memory storer comprises: the reading of 2 line nWE and n0E control store enables and writes to enable, the sheet choosing of 12 line CE0 (0～3), CE1 (0～3), CE2 (0～3) and 12 static memory storeies of CE3 (0～3) control, the most-significant byte and the least-significant byte of 6 line BHE (a-c) and every static memory storer of BLE (a-c) control.
Pattern 0, address logic circuit is divided into 3 groups with the static memory storer, and every group of 4 * 16bit driven by same enable signal, and memory address space reaches 1M; Pattern 1, address logic circuit is divided into 2 groups with the static memory storer, and every group of 4 * 24bit driven by same enable signal, and memory address space reaches 1.5M; Pattern 2, address logic circuit is weaved into 1 group with the unification of static memory storer, and every group of 12 * 16bit driven by same enable signal, and memory address space reaches 3M.
(5) the memory storage line as shown in Figure 3.
Specify concrete software realization flow of the present invention below in conjunction with accompanying drawing, native system is that VHDL language designs with top-down modularization idea usefulness:
When processor write data, data were at first advanced the field programmable device in the native system, entered associative mode according to the content of address wire A23 and A24:
0, three times of redundant decision pattern of pattern.After this pattern of mode control circuit gating, address logic circuit is divided into three groups with the static memory storer, every group drives with identical enable signal, flow process as shown in Figure 5 when reading and writing data, the inner function that realizes this part with two module 3bitcom and tmr of field programmable device, as shown in Figure 6, after data enter module tmr, 16 unit datas enter 16 module 3bitcom respectively, write fashionablely, give Dinouta, Dinoutb and Dinoutc three times writing of each data Dinout redundancy; When reading, with these three unit data two two-phases and three results get again or, realize (Dinouta and Dinoutb) or (Dinoutb and Dinoutc) or (Dinouta and Dinoutc), its net result has reached the result of bits per inch according to majority voting, like this, cooperate the static memory storer of redundancy backup just to realize the triplication redundancy decision circuit.
Pattern 2, the zero defect control model.The function of no EDC error detection and correction, is is normally read and write all internal memory unified addressing by address logic circuit.
In debug process, notice on the circuit diagram that the present invention generates in the RTL combined process, when using VHDL to describe the two-way three-state door, must guarantee all to point out under all conditions clear and definite state, otherwise the logical circuit after RTL is comprehensive can not be realized the function of two-way three-state.
Claims (1)
1. the error detection and correction system that uses of tiny satellite star load computer data storage is characterized in that, contains field programmable device and static memory memory assembly, wherein:
The static memory memory assembly, form by 12 static memory storeies, be divided into into three groups, every group by 4 static memory storeies compositions, each group # is respectively A, B and C, described 12 static memory storeies are provided with: two-way 48 memory data interfaces, the low order address input interface, have A0～A17 totally 18 address input ends link to each other with the low order address output interface of outside central processing unit, the chip selection signal input interface contains 12 chip selection signal input end: CE0～CE3, every 1 chip selection signal input end, and read to enable and write to enable input interface;
Field programmable device, contain: Hamming error correction circuit, triplication redundancy decision circuit TMR, the first two-way three-state gate, the second two-way three-state gate, mode control circuit and address logic circuit, wherein:
The Hamming error correction circuit, adopt the Hamming code error correction mode, add 6 redundanat codes with 16 bit data, totally 22 bit data realize, take 22 data lines, redundancy backup becomes two parts, its form is 22+0000+22, described Hamming error correction circuit is provided with: the first two-way 16 bit data IO interface, chip selection signal input interface and the second two-way 16 bit data IO interface, when writing data, the common write memory address space of the redundanat code of data, decoding and realization EDC error detection and correction when reading of data
Triplication redundancy decision circuit TMR adopts the hardware redundancy method of majority voting to realize EDC error detection and correction, and this TMR circuit is provided with: the first two-way 16 bit data IO interface, chip selection signal input interface and the second two-way 16 bit data IO interface,
The first two-way three-state gate, be provided with: with the two-way 16 bit data IO interface of 16 bit data IO interface interconnection in the outside central processing unit, two respectively with described Hamming error correction circuit, the two-way 16 bit data IO interface of triplication redundancy decision circuit a certain two-way 16 bit data IO interface interconnection separately, and read-write operation signal input interface, the described first two-way three-state gate is sent into described outside central processing unit to 16 bit data of being read by described Hamming error correction circuit or described triplication redundancy decision circuit according to the read-write operation instruction of input under chip selection signal control separately, perhaps under described chip selection signal control, 16 bit data of described outside central processing unit input are write described Hamming error correction circuit or described triplication redundancy decision circuit
The second two-way three-state gate, be provided with: two second two-way 16 bit data IO interface, be connected respectively to described Hamming error correction circuit and the triplication redundancy decision circuit second two-way 16 bit data IO interface separately, also be provided with: two-way 48 bit data IO interface, and read-write control signal input interface, be connected to the two-way 48 bit data IO interface of described static memory memory assembly, so that under write control signal control, be input to described static memory memory assembly after 16 bit data from the input of described Hamming error correction circuit or described triplication redundancy decision circuit are backed up into 3 parts, or under read control signal control, from described static memory memory assembly, read
Address logic circuit, be provided with: the address signal input interface, the address wire A18 of described central processing unit～A22 links to each other with described address signal input interface, also be provided with: read enable signal nWE, write two read-writes of enable signal nOE and enable control signal output ends, be provided with Memory slice again and select signal output interface, link to each other with described static memory memory assembly, sheet choosing with every static memory storer of 12 line traffic controls, most-significant byte and least-significant byte with every static memory storer of 6 line traffic controls, described outside central processing unit is implemented in the function of config memory address under the different mode by the address logic circuit of field programmable device inside, total following three kinds of described pattern: pattern 0 is the triplication redundancy decision pattern, pattern 1 is the Hamming error correction mode, pattern 2 is the zero defect control model, for pattern 0, described outside central processing unit is divided into 3 groups to described static memory storer by address wire A18 and A19 by this address logic circuit, every group 4 * 16, for pattern 1, this address logic circuit is divided into two groups to described static memory storer, every group 4 * 24, for pattern 2, address logic circuit is weaved into one group to the unification of static memory storer, every group of 12 * 16bit, under described three kinds of different patterns, all use same read-write enable signal to drive
Mode control circuit, be provided with the mode select signal input interface, described outside central processing unit is connected to this mode select signal input interface by address wire A23 and A24, address wire A23 and A24 are associative modes 0 for " 00 ", " 01 " associative mode 1, " 10 " associative mode 2, also be provided with: the chip selection signal output port, select control line to be connected to the chip selection signal input end of described Hamming error correction circuit and triplication redundancy decision circuit by sheet respectively, also be provided with: the model selection control signal output ends that is used to control described address logic circuit, and two be respectively applied for control first, the mode select signal output terminal of the second two-way three-state gate, described mode control circuit is according to the content of address wire A23 and A24, the control address logical circuit makes its allocate memory space in view of the above, simultaneously, gating is opened two two-way three-state gates more respectively and is carried out read-write operation the sheet choosing of the Hamming error correction circuit or the triplication redundancy decision circuit of each pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008101122725A CN100570572C (en) | 2008-05-22 | 2008-05-22 | The error detection and correction system that the tiny satellite star load computer data storage is used |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2008101122725A CN100570572C (en) | 2008-05-22 | 2008-05-22 | The error detection and correction system that the tiny satellite star load computer data storage is used |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101354666A CN101354666A (en) | 2009-01-28 |
| CN100570572C true CN100570572C (en) | 2009-12-16 |
Family
ID=40307483
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2008101122725A Expired - Fee Related CN100570572C (en) | 2008-05-22 | 2008-05-22 | The error detection and correction system that the tiny satellite star load computer data storage is used |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100570572C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103197554A (en) * | 2013-03-18 | 2013-07-10 | 南京航空航天大学 | Spacecraft closed-loop attitude control system based on redundant controller and control method thereof |
Families Citing this family (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101833535B (en) * | 2010-04-29 | 2011-12-28 | 哈尔滨工业大学 | Finite state machine with radiating resistant function for reconfigurable satellite-loaded computer |
| CN102355348A (en) * | 2011-06-28 | 2012-02-15 | 中国人民解放军国防科学技术大学 | Fault-tolerant data encryption standard (DES) algorithm accelerator |
| CN102385936A (en) * | 2011-09-16 | 2012-03-21 | 中国科学院微电子研究所 | Hamming code based method for carrying out fault tolerance on static RAM multiple bit upset |
| CN102945217B (en) * | 2012-10-11 | 2015-03-04 | 浙江大学 | Triple modular redundancy based satellite-borne comprehensive electronic system |
| CN105095095B (en) * | 2014-05-12 | 2018-04-06 | 上海大学 | A kind of computer system and data read-write method |
| CN104092629A (en) * | 2014-07-08 | 2014-10-08 | 中国航空无线电电子研究所 | AFDX switch for resisting single event upset |
| CN104616698A (en) * | 2015-01-28 | 2015-05-13 | 山东华翼微电子技术股份有限公司 | Method for sufficiently utilizing memory redundancy unit |
| CN104866390B (en) * | 2015-04-15 | 2018-07-20 | 中国科学院高能物理研究所 | Asynchronous static random access memory triplication redundancy controller |
| CN106339327B (en) * | 2015-07-06 | 2019-08-20 | 上海大学 | A kind of computer system and blade server cabinet |
| CN105760250B (en) * | 2016-02-04 | 2018-11-06 | 北京时代民芯科技有限公司 | A kind of single-particle reinforcing FPGA configuration circuit with code stream error correction and detection function |
| CN106095611A (en) * | 2016-06-20 | 2016-11-09 | 中国航天科技集团公司第九研究院第七七研究所 | The error-tolerance type SDRAM control method that a kind of quick response AHB accesses |
| CN113204446B (en) | 2020-02-03 | 2022-09-23 | 瑞昱半导体股份有限公司 | Register data checking device and method |
| US11928341B2 (en) | 2022-02-24 | 2024-03-12 | Changxin Memory Technologies, Inc. | Sleep control method and sleep control circuit |
| EP4258267A4 (en) | 2022-02-24 | 2024-04-24 | Changxin Memory Tech Inc | Data transmission circuit, data transmission method, and memory |
| KR20230129499A (en) | 2022-02-24 | 2023-09-08 | 창신 메모리 테크놀로지즈 아이엔씨 | Data error correction circuit and data transmission circuit |
| CN116701044A (en) * | 2022-02-24 | 2023-09-05 | 长鑫存储技术有限公司 | Data transmission circuit and data transmission method |
-
2008
- 2008-05-22 CN CNB2008101122725A patent/CN100570572C/en not_active Expired - Fee Related
Non-Patent Citations (6)
| Title |
|---|
| 一种差错控制编译码算法的FPGA 实现. 田晓燕，陈雷.现代电子技术，第2004年第19期. 2004 |
| 一种差错控制编译码算法的FPGA 实现. 田晓燕，陈雷.现代电子技术，第2004年第19期. 2004 * |
| 利用FPGA实现模式可变的卫星数据存储器纠错系统. 蒋洵，熊剑平，尤政.电子技术应用，第2002年第8期. 2002 |
| 利用FPGA实现模式可变的卫星数据存储器纠错系统. 蒋洵，熊剑平，尤政.电子技术应用，第2002年第8期. 2002 * |
| 微小卫星数据存储器单粒子作用的检测及纠错. 熊剑平，贾惠波，尤政.中国空间科学技术，第2000年第6期. 2000 |
| 微小卫星数据存储器单粒子作用的检测及纠错. 熊剑平，贾惠波，尤政.中国空间科学技术，第2000年第6期. 2000 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103197554A (en) * | 2013-03-18 | 2013-07-10 | 南京航空航天大学 | Spacecraft closed-loop attitude control system based on redundant controller and control method thereof |
| CN103197554B (en) * | 2013-03-18 | 2015-07-29 | 南京航空航天大学 | Based on spacecraft closed-loop attitude control system and the control method thereof of redundant manipulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101354666A (en) | 2009-01-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100570572C (en) | The error detection and correction system that the tiny satellite star load computer data storage is used | |
| CN103455283B (en) | A kind of mixing storage system | |
| CN101826038B (en) | Circuit and method for resisting SEU of SRAM FPGA device | |
| CN104049687B (en) | Embedded cube of star house keeping computer and its reconstructing method based on FPGA | |
| CN104239090A (en) | FPGA (Field Programmable Gate Array)-based on-orbit reconfiguration system and method for satellite on-board computer | |
| CN101615147A (en) | The skin satellite is based on the fault-tolerance approach of the memory module of FPGA | |
| CN109947358A (en) | Storage system and its operating method | |
| CN111433758A (en) | Programmable operation and control chip, design method and device thereof | |
| CN107346214A (en) | Accumulator system and its operating method | |
| CN110473582A (en) | Storage system and its operating method | |
| CN110347330A (en) | Storage system and its operating method | |
| CN106681652A (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN101587744B (en) | Multi-level data redundancy method of large scale FLASH memory array | |
| CN105045335A (en) | FPGA information processing system with embedded 8051IP core | |
| CN107562653A (en) | Accumulator system and its operating method | |
| CN112181304B (en) | Satellite-borne NAND Flash storage management system | |
| CN109656469A (en) | For controlling the controller and its operating method of one or more memory devices | |
| CN104866390B (en) | Asynchronous static random access memory triplication redundancy controller | |
| CN102376348A (en) | Low-power dynamic random memory | |
| CN103413571A (en) | Memory and method realizing error detection and error correction through utilizing memory | |
| CN102129353A (en) | Flash storage system, flash controller and data writing method | |
| CN107807902B (en) | FPGA dynamic reconfiguration controller resisting single event effect | |
| CN113849121A (en) | Memory system for accessing stripe form data and operating method thereof | |
| CN108628756A (en) | Storage system and its operating method | |
| CN202677396U (en) | Heterogeneous fault-tolerant circuit design system based on space searching technology |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091216 Termination date: 20140522 |