CN100552683C - The method that the semiconductor physical layout is filled - Google Patents

The method that the semiconductor physical layout is filled Download PDF

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Publication number
CN100552683C
CN100552683C CNB2006101193897A CN200610119389A CN100552683C CN 100552683 C CN100552683 C CN 100552683C CN B2006101193897 A CNB2006101193897 A CN B2006101193897A CN 200610119389 A CN200610119389 A CN 200610119389A CN 100552683 C CN100552683 C CN 100552683C
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array
aref
filled
data
gdsii
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CN101201849A (en
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张兴洲
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
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Abstract

The invention discloses a kind of method that the semiconductor physical layout is filled, adopt the AREF array in the GDSII data to fill domain to be filled, carry out the geometric configuration analysis by the division unit zone, after calculating the AREF filling array of minimum number, to append the mode that writes binary data, the AREF array that calculates is written in the GDSII data, has realized that the AREF array with minimum number is realized quick filling on the GDSII data.

Description

The method that the semiconductor physical layout is filled
Technical field
The present invention relates to a kind of method for designing of semiconductor physics domain, particularly a kind of method that the semiconductor physical layout is filled.
Background technology
At present in the manufacture process of deep-submicron large scale integrated circuit, CMP processes such as (chemically mechanical polishings) can the characteristic to circuit devcie exert an influence because of the density unevenness of semiconductor physics domain, and therefore existing way mainly is to utilize the layout editing instrument that processing steps such as metal are manually filled at corresponding domain white space.Yet such way is very consuming time, and might cause the significantly increase of GDSII (Gerber Data Stream II) data volume.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of method that the semiconductor physical layout is filled, and can realize filling fast how much filling material to domain.
For solving the problems of the technologies described above, the method that the present invention fills the semiconductor physical layout may further comprise the steps:
The step of reading of data is read in the GDSII data in binary mode, by to the searching of GDSII binary data stream, searches out each structure in the domain to be filled;
Divide the step of domain to be filled, domain to be filled is divided into a rectangular array of being made up of a plurality of square shaped cells zone, the size of unit area determines by layout design rules, and the size that the length of side of unit area equals filling material adds the spacing of filling material;
Calculate the step of AREF array, adopt the AREF array in the GDSII data to fill domain to be filled, carry out the geometric configuration analysis, and calculate the AREF filling array of minimum number by the division unit zone;
The step of filling to append the mode that writes binary data, is written to the AREF array that draws above in the GDSII data, has so just realized that the AREF array with minimum number is realized quick filling on the GDSII data.
The present invention is by being converted into the problem of finding the solution linear equation with the filling problem, and is implemented on the GDSII data AREF array with minimum number according to solving result and fills, and fills how much filling materials in the domain fast thereby be implemented in.
Description of drawings
Fig. 1 is a domain structure, is made up of m * n square shaped cells zone;
Fig. 2 is the filling synoptic diagram of the AREF array in zone shown in Figure 1;
But Fig. 3 is the fill area of the embodiment of the invention, is made up of 5 * 4 square shaped cells zones.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing.
The present invention is a kind of by geometric configuration analysis and mathematical computations, the method for directly the semiconductor physical layout being filled fast on the GDSII data.
The GDSII form is a kind of binary data structure, is the semiconductor physics domain storage format that present industry is generally acknowledged, it is with data stream form storage data.The present GDSII form various information that have 70 kinds of record (record) to be used to store domain comprise the structural information, coordinate information, hierarchical information of domain etc.Directly carry out data processing on the GDSII data, often Billy is with the next efficient height of layout editing instrument, because can save the time of data importing to instrument and derivation.
The present invention is at first read in the GDSII data in binary mode, by to the searching of GDSII binary data stream, searches out each structure in the domain to be filled.
For arbitrary domain structure as shown in Figure 1, the border that defines it is made up of m * n square shaped cells zone, and the size of unit area determines by layout design rules, and the size that the length of side of unit equals filling material adds the spacing of filling material.The present invention adopts the AREF array (array reference record) in the GDSII data to fill domain, and the GDSII data volume that can avoid like this causing because fill significantly increases.
As shown in Figure 2, the form of AREF array is:
The x axial coordinate s of starting point;
The y axial coordinate t of starting point;
The columns u of x direction;
The line number v of y direction;
The x axial coordinate s+u * Δ x of terminal point;
The y axial coordinate t+v * Δ y of terminal point.
Filling material will write the GDSII data according to above form.Simultaneously because Δ x and Δ y equal the size of unit area in the present invention, be a fixed value, so the AREF array in the present invention can with four variablees be expressed as simply a (s, t, u, v), wherein the implication of s, t, u, v as previously mentioned.
The present invention is by geometric configuration analysis and mathematical computations, and the AREF array with minimum number on the GDSII data is realized quick filling.
At first, each unit area is numbered, definable individual unit zone be Δ (i, j), 1≤i≤m wherein, 1≤j≤n.
The unit area has had physical graph, and g (i, j) assignment is 0; The unit area need be filled, and g (i, j) assignment is 1, as the g in the accompanying drawing 3 (4,3)=0, g (1,1)=1.
Then, consider how to fill those blank unit areas with the AREF array, the front has defined (s, t with a, u v) represents the AREF array, so satisfy 1≤s≤m, 1≤t≤n, 1≤u≤m, the AREF array of 1≤v≤n are effectively, can define a (s, t at this, u, v) equaling at 1 o'clock is an adopted filling array, equaling to be one at 0 o'clock does not have adopted filling array, as a in the accompanying drawing 3 (1,1,5,2)=1, a (1,1,2,2)=0.
Next at certain a (s, t, u, v) individual unit zone Δ (i, several possibilities of situation analysis j):
(1) a (s, t, u, v)≤g (i, j), as long as this explanation is certain a (s, t, u, v) covered the unit area Δ (i, j), (i j) just can only equal 1 to g, in accompanying drawing 3, because a (1,1,5,2) covered unit area g (1,1), so a (1,1,5,2)≤g (1,1)=1.In the same way, and ∑ a (s, t, u, v)≤∑ g (i, j).
(2) g (i, j)≤∑ a (s, t, u, v), this explanation can only have at most an a (s, t, u, v) capping unit zone Δ (i, j).
To sum up, can draw following relation: g (i, j)≤∑ a (s, t, u, v)≤∑ g (i, j), wherein ∑ a (s, t, u, v) be each a (u v) is worth sum for s, t, ∑ g (i, j) be each g (i, j) value sum.
For arbitrary domain structure, can find the solution the linear equation that satisfies above-mentioned condition, can draw then a ∑ a (s, t, u, possible minimum value v), among the embodiment, a (1,1,5,2) and a (1,3,3,2) are final adopted AREF array as shown in Figure 3.
At last,, the AREF array that draws above is written in the GDSII data, has so just realized that the AREF array with minimum number is realized quick filling on the GDSII data to append the mode that writes binary data.
Be example explanation said method now with domain structure shown in the accompanying drawing 3:
At first read in the GDSII data,, search out domain structure as shown in Figure 3, it is divided into 5 * 4 square shaped cells zones according to layout design rules by to the searching of GDSII binary data stream in binary mode.
Can draw unit area g (4,3)=g (4,4)=g (5,3)=g (5,4)=0 from the geometric configuration analysis, (i, j) assignment is 1 with remaining g.
Because for each unit area, have g (i, j)≤∑ a (s, t, u, v)≤(i j), so just can find the solution a linear problem to ∑ g, draws the AREF array a (1,1,5,2) and a (1,3,3,2) of minimum number then.
At last,, the AREF array that draws above is written in the GDSII data, just can finishes and in domain structure shown in the accompanying drawing 3, fill filling material how much to append the mode that writes binary data.
The present invention is read in the GDSII data in binary mode, by searching to the GDSII binary data stream, search out each structure in the domain, again by geometric configuration analysis and mathematical computations, the AREF that calculates minimum number fills array, directly the semiconductor physical layout is filled fast on the GDSII data then.This with utilized domain instrument manually to fill to compare in the past, improved the efficient of filling, be a kind of new method of robotization.Simultaneously, fill with the AREF array in the GDSII data, the GDSII data volume that can avoid causing because fill significantly increases.

Claims (1)

1, a kind of method that the semiconductor physical layout is filled is characterized in that, may further comprise the steps:
The step of reading of data is read in the GDSII data in binary mode, by to the searching of GDSII binary data stream, searches out each structure in the domain to be filled;
Divide the step of domain to be filled, domain to be filled is divided into a rectangular array of being made up of a plurality of square shaped cells zone, the size of unit area determines by layout design rules, and the size that the length of side of unit area equals filling material adds the spacing of filling material;
Calculate the step of AREF array, adopt the AREF array in the GDSII data to fill domain to be filled, carry out the geometric configuration analysis, find the solution the g (i that satisfies condition by the division unit zone, j)≤∑ a (s, t, u, v)≤and ∑ g (i, linear equation j), and calculate the AREF array of minimum number;
The step of filling to append the mode that writes binary data, is written to the AREF array that draws above in the GDSII data, has so just realized that the AREF array with minimum number is realized quick filling on the GDSII data;
Wherein, and g (i is that i is individual on the x direction of principal axis j), j unit area on the y direction of principal axis, and 1≤i≤m, and 1≤j≤n, m and n are respectively the length of side in zone to be filled; The unit area has had physical graph, and g (i, j) assignment is 0; The unit area need be filled, and g (i, j) assignment is 1;
(u v) represents the AREF array to a for s, t; Wherein, s is the x axial coordinate of starting point, and t is the y axial coordinate of starting point, and u is the columns of x direction, and v is the line number of y direction; Satisfy 1≤s≤m, 1≤t≤n, 1≤u≤m, the AREF array of 1≤v≤n all is effective; This definition a (s, t, u, v) equaling at 1 o'clock is an adopted array, equaling to be one at 0 o'clock does not have adopted array.
CNB2006101193897A 2006-12-11 2006-12-11 The method that the semiconductor physical layout is filled Active CN100552683C (en)

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Application Number Priority Date Filing Date Title
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CN100552683C true CN100552683C (en) 2009-10-21

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Patentee before: Shanghai Huahong NEC Electronics Co., Ltd.