CN100547520C - The method for managing power supply of computer system and computer system - Google Patents
The method for managing power supply of computer system and computer system Download PDFInfo
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Abstract
The invention provides the method for managing power supply of a kind of computer system and computer system.Described computer system comprises that a primary processor, a coprocessor and are used to store the instruction stack of the task of needing the coprocessor processing.The method for managing power supply of described computer system comprises: judge the memory bus idle special time whether between a described coprocessor and the storer; If idle this special time of the bus between described coprocessor and the described storer judges then whether described instruction stack is empty.If described instruction stack is empty, then sends a switching order and make described coprocessor enter a low-power consumption mode.The less primary processor of power consumption can make the relatively large coprocessor of power consumption enter low-power consumption mode in the computer system of the present invention, thereby can reach the effect of the power consumption that reduces computer system.
Description
Technical field
The invention relates to a kind of method for managing power supply of computer system, particularly relevant for a kind of method for managing power supply and equipment with computer system of multiprocessor.
Background technology
Along with the fast development of integrated circuit technique, multimedia function is the basic need of consumer to portable set.With the mobile phone is example, mobile phone develops into operating systems such as can moving Window mobile, Symbian, PalmOS from the equipment that at first is used to converse merely, and integrated recreation, voice playing, video playback, digital photography and functions such as personal information processing that can free downloading application software.For realizing these functions, mobile phone can not only be connected to mobile telephone network, but also may be connected to WLAN (wireless local area network) and communicate by letter with PC, perhaps uses Bluetooth technology to connect wireless headset.All these additional functions all will provide electric energy by electric battery.In addition, system and function complicated makes the processor (for example ARM7) of mobile phone must have higher calculation process ability, and this directly causes the power consumption of processor to increase.In fact, except improving battery itself, improving the cellular phone power supplies management function also is the effective ways that promote the mobile phone effect.This is for the service time of improve using and to prolong battery serviceable life etc. all extremely helpful, and under the prerequisite of user's using system all functions significant prolongation stand-by time, air time or reproduction time.
Therefore, how when supporting what's new, keeping the long stand-by time of computer system is problem demanding prompt solution.
Summary of the invention
The object of the present invention is to provide a kind of multi-functional computer system and method for managing power supply that reduces power consumption of computer systems supported.
The invention provides a kind of method for managing power supply of computer system.Described computer system comprises that a primary processor, a coprocessor and are used to store the instruction stack that described primary processor is distributed to the task of described coprocessor processing.The method for managing power supply of described computer system comprises: judge the memory bus idle special time whether between a described coprocessor and the storer; If idle this special time of the bus between described coprocessor and the described storer judges then whether described instruction stack is empty.If described instruction stack is empty, then sends a switching order and make described coprocessor enter a low-power consumption mode.
The present invention provides a kind of computer system again, comprising: a first processor, one second processor, an instruction stack, a storer and are coupled to the bridge between described first processor and described second processor.Second processor is used to carry out the task that described first processor distributes.Instruction stack is used to store the instruction that described first processor is distributed to the task of described second processor execution.Storer is coupled to described second processor by a memory bus, and is used for temporary deal with data.Bridge comprises a bus state detecting unit and an instruction stack state detecting unit.The bus state detecting unit is used to detect the state of described memory bus, and exports a timeout signal, is in idle condition to represent described memory bus.Instruction stack state detecting unit is used to detect the state of described instruction stack, and exports an instruction stack spacing wave, is sky to represent described instruction stack.Described first processor switches order according to described timeout signal and instruction stack spacing wave output one, so that described second processor switches to a low-power consumption mode by a normal mode of operation.
The less primary processor of power consumption can make the relatively large coprocessor of power consumption enter low-power consumption mode in the computer system of the present invention, and only when task of needing coprocessor to carry out reaches a certain amount of, just can make coprocessor be converted to normal mode of operation, thereby can reach the effect of the power consumption that reduces computer system by low-power consumption mode.
Description of drawings
By the description of carrying out in conjunction with the following examples and the accompanying drawing that illustrates, above-mentioned other purposes of the present invention and characteristics will become apparent, wherein:
Fig. 1 is the synoptic diagram of computer system according to an embodiment of the invention;
Fig. 2 is the detailed maps of computer system shown in Figure 1;
Fig. 3 is the process flow diagram of method for managing power supply according to an embodiment of the invention;
Fig. 4 is the process flow diagram of method for managing power supply according to another embodiment of the present invention.
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and cooperate appended graphicly, be described in detail below.
In general, in computer realm, there are two kinds of general processor architectures, promptly adopt the x86 architecture processor of complex instruction set and the ARM architecture processor that adopts reduced instruction set.X 86 processor is generally used in the personal computer, handles official business, Flame Image Process and database processing etc.With respect to X 86 processor, arm processor has characteristics such as cost is low, power consumption is little, and opening is good, thereby is generally used in the consumption electronic products, for example, and mobile phone, digital camera etc.Yet, use the computer system of arm processor not support most of hardware or software equipment of expanding, for example, can not handle electronic documents such as WORD, EXCEL, PPT and ACROBAT, thereby the functional promotion of consumption electronic products has been caused restriction.
For addressing the above problem, as shown in Figure 1, the invention provides a coprocessor 11 and a multimedia processor 12 that a computer system 100 comprises an X86 framework, so that the Processing tasks of computer system 100 is rationally divided, realize the optimization of performance and power consumption.For instance, coprocessor 11 is used for the task that handling property is had relatively high expectations, for example formula calculating etc.Multimedia processor 12 is made up of arm processor and graph processing chips (GPU), is used to carry out the conventional task and the processing of multimedia messages.Computer system 100 also comprises a bridge 13, is connected with coprocessor 11 and multimedia processor 12 to carry out the protocol conversion between coprocessor 11 and the multimedia processor 12.In present embodiment, computer system 100 also comprises the transmission control unit (TCU) 110 that is connected with coprocessor 11, peripheral control unit 120 that is connected with multimedia processor 12 and the storer 111,121 that is connected with transmission control unit (TCU) 110 and multimedia processor 12 respectively.Transmission control unit (TCU) 110 can be realized by a chipset (chipset), with communicating by letter of control data transmission and coprocessor 11 and other assemblies.Peripheral control unit 120 can be realized by Yi Xiqiao (westbridge), be responsible for multimedia processor 12 and other assemblies communicate by letter and specific peripheral hardware between direct communication.As is known to the person skilled in the art, (power managementunit PMU), is used for the power consumption of management system can be integrated with Power Management Unit usually in computer system 100.For example, the coprocessor 11 based on the X86 framework can enter energy saver mode C0～C5 according to ACPI (ACPI, advancedconfiguration and power interface) standard.Multimedia processor 12 based on the ARM framework also can enter idle pulley, park mode and shutdown mode.
For further reducing the power consumption of computer system 100, the coprocessor 11 of present embodiment computer system 100 can also (Active State Power Management, ASPM) mechanism enters link (link) low-power consumption mode according to the defined Active State Power Management of PCIE standard.As shown in Figure 2, in present embodiment, multimedia processor 12 can be regarded the primary processor of computer system 100 as, is responsible for handling day-to-day work and Multimedia Task, 11 of coprocessors are counted as PCIE equipment, are used to handle the task that multimedia processor 12 is distributed.Storer 111 is used for the data of temporary needs processing or the data after the processing.Storer 121 is used for storage system program and data, and is provided with an instruction stack (instruction stack) 1211, and storage multimedia processor 12 is distributed to the instruction that coprocessor 11 is carried out.Bridge 13 is connected with coprocessor 11 and multimedia processor 12 by the PCIE bus, and comprises a detecting module 131 and a protocol converter 132.Protocol converter 132 is used to finish the protocol conversion between ARM order (command) and the X86 order.
Detecting module 131 comprises bus state detecting unit 133, instruction stack state detecting unit 134 and output unit 135.In present embodiment, if bus state detecting unit 133 does not detect in a special time between storer 111 and the transmission control unit (TCU) 110 data transfer operation is arranged, and instruction stack state detecting unit 134 detects instruction stack 1211 for empty, then output unit 135 meeting output signal GNT can be converted to the link low-power consumption mode with coprocessor 11 to inform multimedia processor 12.Specifically, bus state detecting unit 133 is provided with a bus cycles detecting unit 1331 and a timer 1332.Bus cycles detecting unit 1331 is connected to the memory bus (not shown) between storer 111 and the transmission control unit (TCU) 110, so that whether data are arranged between detecting coprocessor 11 and the storer 111 transmits.Timer 1332 is used for timing one special time, and this special time is pre-configured by multimedia processor 12.When bus cycles detecting unit 1331 detects reportedly defeated bus cycles (data transfer bus cycle) of a stroke count, timer 1332 zero clearings; When bus cycles detecting unit 1331 does not detect data transmission bus during the cycle, timer 1332 this special time that picks up counting.If the timing time of timer 1332 surpasses this special time, then send a timeout signal T_OUT to output unit 135, with show memory bus idle this special time, promptly in this special time, do not have data transfer operation between coprocessor 11 and the storer 111.The address realm of instruction stack 1211 in storer 121 can be write in the corresponding registers of instruction stack state detecting unit 134 in advance by multimedia processor 12.Instruction stack state detecting unit 134 is according to the value of the address realm of instruction stack 1211 and the stack pointer that detects (stackpointer), whether decision instruction stack 1211 is empty, if it is empty, then send an instruction stack spacing wave S_EMPTY to output unit 135, to show task of not needing coprocessor 11 to carry out at present.As seen from the above description, when output unit 135 receives timeout signal T_OUT and instruction stack spacing wave S_EMPTY at the same time, just understand output signal GNT,, and do not have new task to need to carry out with the idle special time of explanation coprocessor 11.Multimedia processor 12 can send one and switch order after receiving the GNT signal that detecting module 131 sends, so that coprocessor 11 enters the link low-power consumption mode, this switching command exports coprocessor 11 to after handling by protocol conversion module 132.Yet, because coprocessor 11 also has some back-end datas or process this moment in processing and can't enter the link low-power consumption mode probably.Therefore, coprocessor 11 can judge that after receiving switching command whether in addition current data or process in processing in the present embodiment, if not, then send a back-signalling ACK to multimedia processor 12 and enter the link low-power consumption mode by protocol conversion module 132.If current also have data or process in processing, then do not send it back induction signal ACK.
As previously mentioned, the coprocessor 11 of present embodiment is the processor of X86 framework, thereby can enter processor low-power consumption mode C0～C5 according to the ACPI standard.In general, when coprocessor 11 will enter the processor low-power consumption mode, need send a special configuration information to storer 111, and this configuration information can be sent to storer 111 by memory bus by a configuration cycle (C state configure cycle).Thereby the bus state detecting unit 133 of present embodiment detecting module 131 also is provided with a low-power consumption mode recognition unit 1333, is used to detect the configuration cycle on the memory bus.If low-power consumption mode recognition unit 1333 detects configuration cycle, then send one and entered processor low-power consumption mode signal C_MODE to output unit 135, at this moment, even output unit 135 receives timeout signal T_OUT and instruction stack spacing wave S_EMPTY simultaneously, can output signal GNT yet.That is to say that after the coprocessor 11 of example of the present invention entered the processor low-power consumption mode, multimedia processor 12 can not send and make coprocessor 11 enter the order of link low-power consumption mode.Need to prove that if coprocessor 11 is not the processor of X86 framework, then low-power consumption mode recognition unit 1333 can be set, promptly output unit 135 is only according to timeout signal T_OUT and instruction stack spacing wave S_EMPTY output signal GNT.
On the other hand, the multimedia processor 12 of present embodiment is provided with a state recording unit 122 and a decision package 123.State recording unit 122 is used for writing down by a processor state value mode of operation of coprocessor 11, for example, the processor state value is 1 o'clock, and expression coprocessor 11 is in normal mode of operation, the processor state value is 0 o'clock, and expression coprocessor 11 is in the link low-power consumption mode.The initial value of this state recording unit 122 is a normal mode of operation.Also according to the address realm of stack pointer and instruction stack 1211, whether the residue size of decision instruction stack 1211 is less than a particular value in instruction stack state detecting unit 134, and promptly whether decision instruction stack 1211 is soon full.If instruction stack 1211 is soon full, then export the decision package 123 of the full signal S_FULL of an instruction stack to multimedia processor 12.Decision package 123 is expired the value of signal S_FULL and state recording unit 122 according to the signal GNT of output unit 134 outputs, the instruction stack of instruction stack state detecting unit 134 outputs, judges whether to export to make coprocessor 11 be converted to the order of normal mode of operation by the link low-power consumption mode.For instance, when decision package 123 receives the full signal S_FULL of instruction stack, if the value representation coprocessor 11 of state recording unit 122 is in the link low-power consumption mode, then output makes coprocessor 11 be converted to the order of normal mode of operation by the link low-power consumption mode, and revises the value of state recording unit 122.When decision package 123 receives the signal GNT of output unit 134 outputs, if the value representation coprocessor 11 of state recording unit 122 is in normal mode of operation, then output makes coprocessor 11 enter the switching command of link low-power consumption mode, and revises the value of state recording unit 122.
In present embodiment, storer 111 and storer 121 can be two storeies independently physically, and for example DDR, DDR2 etc. also can be for being positioned at two storage spaces on the same physical storage.As known to persons of ordinary skill in the art, coprocessor 11 can read instruction stack 1211 in the storer 121 by transmission control unit (TCU) 110, to carry out the task (not shown) that multimedia processor 12 distributes.
Figure 3 shows that process flow diagram according to the method for managing power supply of one embodiment of the invention computer system.At first, in step S30, bus state detecting unit 133 judge the memory bus between storer 111 and the transmission control unit (TCU) 110 whether idle a special time, if, execution in step S31 then.In step S31, whether instruction stack state detecting unit 134 decision instruction stacks 1211 are empty, if illustrate that X 86 processor had not both had data to transmit and do not had new task to need to carry out yet, thereby enter step S32.In step S32, judge whether X 86 processor is in the processor low-power consumption mode, if, then skip to step S34, if not, then make X 86 processor enter link low-power consumption mode (step S33).After step S33, execution in step S34, whether the decision instruction stack soon will be filled with, if not, then make X 86 processor remain on the link low-power consumption mode, if, then make X 86 processor be converted to normal mode of operation (step S35) by the link low-power consumption mode, and process ends.
Figure 4 shows that process flow diagram according to the method for managing power supply of another embodiment of the present invention computer system.At first, in step S401, if bus cycles detecting unit 1331 do not detect a data transmission bus cycle, execution in step S402 then starts timer 1332 special time that picks up counting.Then, in step S403, judge once more whether the data transmission bus cycle is arranged on the memory bus,, then will return step S401 after timer 1332 zero clearings (step S404) if having.If do not find the data transmission bus cycle yet in step S403, then execution in step S405 judges whether timer 1332 is overtime.If timer 1332 is overtime, promptly the idle special time of memory bus follows then whether decision instruction stack 1211 is empty (step S406).If instruction stack 1211 is empty, promptly X 86 processor does not have new task to need to carry out, and does not have data to need to transmit yet, and then execution in step S407 judges whether X 86 processor is in the processor low-power consumption mode.If instruction stack 1211 is not empty, then return step S401.At step S407, if coprocessor 11 is in processor low-power consumption mode, then process ends.If coprocessor 11 is not in the processor low-power consumption mode, judge then whether coprocessor 11 is in link low-power consumption mode (step S408), if not, then send one and make coprocessor 11 enter the order (step S409) of link low-power consumption mode.If coprocessor 11 is in the link low-power consumption mode, then skip to step S412.Behind step S410, whether execution in step S410 judges coprocessor 11 according to the order output back-signalling ACK that receives, if, then show current data or the process handled of not needing of coprocessor 11, and entered link low-power consumption mode (step S411).If in step S410, coprocessor 11 is not exported back-signalling ACK, then returns step S401.After step S411, execution in step S412 and step S413, when the remaining space of instruction stack 1211 is less than or equal to a particular value, when promptly instruction stack 1211 is about to expire, sends and make coprocessor 11 be converted to the order of normal mode of operation by the link low-power consumption mode.Then, judge whether coprocessor 11 exports back-signalling ACK (step S414), if show that then coprocessor 11 is converted to normal mode of operation (step S415) by the link low-power consumption mode, promptly finishes the power management flow process of present embodiment.If not, process ends then.
Power management flow process by present embodiment, the less multimedia processor 12 of power consumption can make the relatively large coprocessor of power consumption 11 enter the link low-power consumption mode according to the ASPM standard in the computer system 100, and only when task of needing coprocessor 11 to carry out reaches a certain amount of, just can make coprocessor 11 be converted to normal mode of operation, thereby can further reduce the power consumption of computer system 100 by the link low-power consumption mode.
The above only is preferred embodiment of the present invention; so it is not in order to limit scope of the present invention; any personnel that are familiar with this technology; without departing from the spirit and scope of the present invention; can do further improvement and variation on this basis, so the scope that claims were defined that protection scope of the present invention is worked as with the application is as the criterion.
Claims (12)
1. the method for managing power supply of a computer system, described computer system comprises that a primary processor, a coprocessor and are used to store the instruction stack that described primary processor is distributed to the task of described coprocessor processing, it is characterized in that the method for managing power supply of described computer system comprises:
Judge the memory bus idle special time whether between a described coprocessor and the storer;
If idle this special time of the bus between described coprocessor and the described storer judges then whether described instruction stack is empty; And
If described instruction stack is empty, then sends a switching order and make described coprocessor enter a low-power consumption mode.
2. the method for managing power supply of computer system according to claim 1, it is characterized in that, switch order described coprocessor is also comprised before entering the step of a low-power consumption mode sending one: judge whether described coprocessor is in described low-power consumption mode, if not, then send described switching command.
3. the method for managing power supply of computer system according to claim 2 is characterized in that, also comprises:
If described coprocessor is in described low-power consumption mode, whether the remaining space of then judging described instruction stack is less than a particular value; And
If the remaining space of described instruction stack then sends one and makes described coprocessor enter the order of a normal mode of operation less than this particular value.
4. the method for managing power supply of computer system according to claim 1 is characterized in that, described judge the memory bus between a described coprocessor and the storer whether the step of idle this special time comprise:
Judge whether a data transmission bus cycle is arranged on the memory bus between described coprocessor and the described storer; And
If do not have the described data transmission bus cycle on the described memory bus, then start this special time of timer timing;
If the timing time of this timer surpasses this special time, then show described memory bus idle this special time.
5. the method for managing power supply of computer system according to claim 4 is characterized in that, also comprises: if behind the described timer initiation, arranged, then with described timer zero clearing a data transmission bus cycle on the described memory bus.
6. the method for managing power supply of computer system according to claim 1 is characterized in that, also comprises:
Judge whether described coprocessor enters a processor low-power consumption mode according to the ACPI standard;
If then finish the power management flow process.
7. a computer system is characterized in that, comprising:
One first processor;
One second processor is used to carry out the task that described first processor distributes;
One instruction stack is used to store the instruction that described first processor is distributed to the task of described second processor execution;
One storer is coupled to described second processor by a memory bus, with temporary deal with data;
One bridge is coupled between described first processor and described second processor, comprising:
One bus state detecting unit is used to detect the state of described memory bus, and exports a timeout signal, is in idle condition to represent described memory bus;
One instruction stack state detecting unit is used to detect the state of described instruction stack, and exports an instruction stack spacing wave, is sky to represent described instruction stack; And
Wherein, described first processor switches order according to described timeout signal and instruction stack spacing wave output one, so that described second processor switches to a low-power consumption mode by a normal mode of operation.
8. computer system according to claim 7 is characterized in that, described bus state detecting unit comprises:
One bus cycles detecting unit is used to detect the data transmission bus cycle on the described memory bus;
One timer, the bus cycles detecting unit detects the data transmission bus cycle as described, this timer zero clearing; The bus cycles detecting unit does not detect the data transmission bus cycle as described, then this timer special time that picks up counting; And
Wherein, described bus cycles detecting unit is not if detect the data transmission bus cycle, and the timing time of this timer then should can be exported described timeout signal by the bus cycles detecting unit above this special time.
9. computer system according to claim 8 is characterized in that, the remaining space that described instruction stack state detecting unit detects described instruction stack is exported the full signal of an instruction stack to described first processor during less than a particular value.
10. computer system according to claim 9, it is characterized in that, described first processor is provided with a decision package, is used for making described second processor be switched to the order of normal mode of operation by low-power consumption mode according to full signal of described instruction stack and processor state value output one; And a state recording unit, be used to write down the described processor state value of described second processor, and export described processor state value to described decision package.
11. computer system according to claim 7 is characterized in that, described bus state detecting unit is provided with a low-power consumption mode recognition unit, is used for exporting a low-power consumption mode signal according to the configuration cycle on the described memory bus.
12. computer system according to claim 11, it is characterized in that, this bridge also comprises an output unit, it receives this low-power consumption mode signal, as this moment this output unit receive this timeout signal and this instruction stack spacing wave simultaneously, will can not export the described switching command that makes this second processor enter this low-power consumption mode.
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