CN100530157C - Galois field linear transformer trellis system - Google Patents
Galois field linear transformer trellis system Download PDFInfo
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- CN100530157C CN100530157C CNB2004800142079A CN200480014207A CN100530157C CN 100530157 C CN100530157 C CN 100530157C CN B2004800142079 A CNB2004800142079 A CN B2004800142079A CN 200480014207 A CN200480014207 A CN 200480014207A CN 100530157 C CN100530157 C CN 100530157C
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- galois field
- field linear
- trellis
- linear transformer
- matrix
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Abstract
A galois field linear transformer trellis system includes a Galois field linear transformer matrix; an input selection circuit for providing to the matrix a number of input bits in one or more trellis bit streams and a trellis state output of the matrix and a programmable storage device for configuring the matrix to perform a multi-cycle Galois field transform of the one or more trellis bit steams and trellis state output to provide a plurality of trellis output channel symbols and a new trellis state output in a single cycle.
Description
Technical field
The present invention relates to a kind of improved Galois field linear transformer trellis system, and relate more specifically to a kind of can be in the monocycle to one or more positions and/or even the system of the capable complete grid computing of outgoing position swap-in.
Related application
The application requires Stein to equal the right of priority of the title of application on April 8th, 2003 for 60/461, No. 267 provisional application of the U.S. of " Entitledmethod to predict trellis output using the FG-2 ALU (utilizing the method for FG-2 ALU prediction grid output) ".
Background technology
The purposes of forward error correction (FEC) is to improve the ability of this channel by the redundant information of the data of channel transmission being added some careful design.The process of adding this redundant information is called chnnel coding.Convolutional encoding and block encoding are two kinds of principal modes of chnnel coding.Convolutional code is computing on serial data, next position or several position.Block code computing on the message blocks of big relatively (typically up to 200 bytes).Convolutional code may be more more convenient than block code in some cases, because the former produces redundant digit and error correction continuously.
Grid is a kind of equipment, for example is that redundancy is introduced in error detection thereby be used for by extension bits with the contraposition coding.Grid is made of trigger that comprises linear feedback shift register (LFSR) and the partial sum gate that comprises modulo 2 adder.Because LFSR, convolutional code has storer.For example, two or three or more inputs can produce the output of three or four or more channel symbol, and these symbols depend on that not only current input hyte piece also depends on former piece.There are many different trellis system of realizing of may needing: basic 1:2 scrambler, basic 1:3 scrambler or any basic n:m scrambler.Trellis system may be programmable or may relate to the hardware solution.A problem of conventional grid able to programme is that they need be in the computing in each enterprising line number cycle in order to produce channel symbol.Typical approach relates to the linear feedback shift register of realizing requiring a large amount of additions or shift operation.In addition, the channels bits that is produced may not be on the required order of subsequent processes.Although hardware solution is more effective for certain specific function, can not reconfigure them to adapt to many dissimilar grids that may needs.
Summary of the invention
Thereby an object of the present invention is to provide a kind of Galois field linear transformer trellis system.
Another object of the present invention provides faster a kind of and can be replaced as channel symbol output anyly wishes that order is to adapt to the Galois field linear transformer trellis system of subsequent processes.
A further object of the present invention provide a kind of can be in the single cycle from the Galois field linear transformer trellis system of a plurality of delivery channel symbols of one or more position predictions.
A further object of the present invention provides a kind of Galois field linear transformer trellis system that can export from some input position predictions concurrently in one-period.
A further object of the present invention provides a kind of Galois field linear transformer trellis system that various independently i/o sites +s change that also can be configured to finish.
Can be by the Galois field linear transformer matrix that adopts to have a plurality of unit, input selection circuit and programmable storage device are realized a kind ofly receiving one or more positions concurrently and providing the faster of delivery channel symbol with direct or displacement format, much simple reconfigurable trellis system, thereby realization the present invention, wherein this input selection circuit is used for providing a plurality of input positions of one or more trellis bit stream and the grid states output of this matrix to this matrix, thereby and this programmable storage device be used for to a plurality of unit programme and set this matrix with one or more trellis bit stream and grid state output carrying out multicycle Galois Field linear transformation were provided in the single cycle a plurality of grid delivery channel symbols or even displacement after grid output channel symbol and new grid state.
The present invention is characterised in that a kind of Galois field linear transformer trellis system, and it comprises a Galois field linear transformer trellis matrix and a plurality of input selection circuits of importing the grid state output of position and this matrix that are used for this matrix is provided one or more trellis bit stream with a plurality of unit.Thereby programmable storage device is used for described a plurality of unit are programmed and dispose this matrix providing a plurality of grid delivery channel symbols and new grid state output so that these one or more trellis bit stream and grid state are carried out multicycle Galois Field linear transformation in the single cycle.
This matrix can comprise a plurality of unit in a preferred embodiment, each unit comprises an XOR circuit, and its output terminal is connected on this XOR circuit and input end is connected to this input selection circuit to receive the AND logic circuits of a plurality of inputs position.This programmable storage device can comprise a plurality of storage unit, and each storage unit is programmed to and enables different Galois Field linear transformations.May have a controller circuitry, be used for reshuffling this programmable storage device with grid delivery channel signpermutation in predesigned order.In each row and column of this matrix, only start a unit thereby this controller circuitry can also be reshuffled this programmable storage device one given input bit pattern is replaced as a kind of different output bit pattern.
Description of drawings
Can expect other purpose, feature and advantage from following explanation insider to preferred embodiments and drawings, in the accompanying drawing:
Fig. 1 is the simplification calcspar according to reconfigurable Galois field linear transformer trellis system of the present invention;
Fig. 2 A is the block schematic diagram that the hardware linear feedback shift register of typical prior art ADSL Modem trellis system realizes;
Fig. 2 B is the figure Table I, and the four condition situation of the prior art ADSL Modem grid of last Fig. 2 of eight clock period is described;
Fig. 3 A is the more detailed block schematic diagram of reconfigurable Galois field linear transformer trellis system of Fig. 1;
Fig. 3 B and 3C are figure Table II and III, two kinds of four condition situations that occur in the Galois field linear transformer trellis system of key diagram 3A;
Fig. 4 is the more detailed maps of the Galois field linear transformer matrix of Fig. 3, and it is configured to produce grid delivery channel symbol from the input hyte in one-period;
Fig. 5 is the synoptic diagram of the Galois field linear transformer matrix of Fig. 3, and its reprovision is set to the grid delivery channel symbol that produces the displacement of input hyte in one-period;
Fig. 6 is the more detailed maps of the Galois field linear transformer trellis system of Fig. 3;
Fig. 7 is the synoptic diagram that has the matrix unit of programmable storage device;
Fig. 8 is the block schematic diagram of Galois field linear transformer trellis system of the present invention, has to have a plurality of programmable parts plane and a controller circuitry that is used for disposing and disposing it;
Fig. 9 A-9H illustrative is utilized the sample of the displacement that Galois field linear transformer trellis system able to programme of the present invention reaches.
Embodiment
Except the preferred embodiment or each embodiment that the following describes, the present invention can and can or finish in the variety of way realization for other embodiment.Thereby should be understood that declarative description below the present invention is not subject on using or CONSTRUCTED SPECIFICATION illustrated in the accompanying drawings and member setting.
The Galois field linear transformer trellis system 10 of the present invention of foundation shown in Fig. 1, it receives briefly with the some inputs position in one or more trellis bit stream of u3, u2 and u1 mark and with the grid state output of this matrix of Sn mark, and this system produces output 12 and exports 14 with the next or new grid state of Sn+1 mark from these inputs.
The typical trellis system that realizes with linear feedback shift register (LFSR) 22 in hardware shown in Fig. 2 A, for example the ADSL Modem grid 22.Linear feedback shift register 22 comprises that four memory devices are trigger 24,26,28 and 30, and they represent state s0, s1, s2 and the s3 of this linear feedback shift register.Trellis bit stream u3, u2 and u1 are as bit stream u3
0, u3
1, u3
2... u3
7..., u2
0, u2
1, u2
2, u2
3... u2
7... u1
0, u1
1, u1
2, u1
3... u1
7... appear on each input end 32.Bit stream u3 directly provides output v0 in input 32.Output v1 is that response u3 input and u1 input produce by partial sum gate 34.Output w0 is that response u3 and u2 input produce by partial sum gate 36.Output w1 is that the reach the standard grade output state S3 of the linear feedback shift register 22 on 40 of all input u3, u2, u1 and adding of response provides by partial sum gate 38.Although each particular grid position u3 that trellis system 20 responses are briefly represented with u3, u2, u1
0, u3
1, u3
2... u3
7..., u2
0, u2
1, u2
2, u2
3... u2
7... u1
0, u1
1, u1
2, u1
3... u1
7... finish computing fast obtaining exporting v0, v1, w0, w1, thereby it has the shortcoming that its hardware can not reconfigure for other any purposes easily for the service of ADSL Modem grid function specially.
In operation under each clock period at state s0, s1 shown in the row 50 of the figure of Fig. 2 B Table II, s2 and s3.
The grid of Fig. 2 A be exclusively used in the function of finishing particular grid and in the situation of ADSL Modem grid next time only handling a position, and the Galois field linear transformer trellis system 10a of the present invention of Fig. 3 A can handle four, eight, 12,16 or any amount of position simultaneously according to the concrete size of using the Galois field linear transformer matrix that allows.This is shown in Fig. 3 A, and wherein the generalization trellis bit stream is imported u1
0-u1
3, u2
0-u2
3, u3
0-u3
3Illustrate all and receive simultaneously.To first constantly or first clock period use z1
0To z1
3-, y2
0To y2
3And x3
0To x3
3Specific position is shown.Because GFLT trellis system 10 once receives four in this object lesson, output under its true Galois Field transducer form will represent and the 4th clock period or figure Table I in the output of No. three clock period correspondences, this frame district 52 with the figure Table I in Fig. 2 B emphasizes.Thereby in Fig. 2 B chart 1 54,56,58 and 60 shown in the value of state s0, s1, s2 and s3 be new grid state 54a, 56a, 58a and 60a among Fig. 3 A.They are new grid state s0
N+1, s1
N+1, s2
N+1, s3
N+1And feed back to grid input end s3n, s2n, s1n, s0n.Thereby according to first moment of Galois field linear transformer trellis system of the present invention or the 4th clock period or No. 3 identical output of clock period of generation of first clock period and prior art systems 20.Not to handle a position but the position of handling four (or eight or 12 or any other quantity) like this in one-period.What its software reconfigurable system in office by contrast can need several cycles for finishing this.
In Fig. 3 B figure Table II with next or second clock cycle of clock period 0 mark, in row 51 state S0
N+1Be shown as is s3, y2
1(y2
1Be u2
1Currency), s0, y2
0(y2
0Be u2
0Currency) and z1
2(z1
2Be u1
2Currency) distance combination.This can launch as shown in secondary series 53 and then eliminate redundant (mould 2 adds) so that next grid state to be provided, to s1 as shown in the 3rd row 55
N+1, s2
N+1, s3
N+1Finish identical work.Do not list output v0, v1, w0 and w1, because they are that the direct distance combination of signal is for example as shown on the Galois Field linear transformation trellis system matrix 60 of Fig. 4 with diagrammatic form.As can be seen, the distance gate cell 62 of the selected row and column intersection by enabling matrix 60 obtains output required among figure Table I and the II.For example, with reference to the figure Table II of Fig. 3 B, the value of s3 can be regarded s1, s2, s3, u2 as
1, u2
2, u1
3And u1
0Distance combination, and for example for w0
3Its expression formula should be u3
3And u2
3Simple nonequivalence operation, for v1
2It can be u3
2And u1
2Distance, or the like.In the computing in single cycle, can handle four positions like this so that output and state are provided, and this needs four cycles usually under the hardware shown in the ADSL Modem grid of Fig. 2 A is realized, realizes the execution cycle that next needs are much more at reconfigurable software in addition.
Thereby another advantage of the present invention is can assemble grid delivery channel symbol under the form in hope in this matrix in the dirigibility of handling output by the order of any hope.For example, replace providing output at single all after dates as shown in Figure 4 and (wherein make up all w1 of from 0 to 3, all w0 of from 0 to 3, and make up all v1 and all v0), can alternatively make up w1[3 as shown in Figure 5], wo[3], v1[3], v0[3], the combination w1[2], w0[2], v1[2], v0[2], or the like.
The Galois field linear transformer trellis system of Fig. 6 can comprise matrix 70 and input selection circuit 72, and this circuit 72 can comprise the latch 86,88,90,92 of input or " u " register 74, state or " s " register 76, some multiplexers 78,80,82,84 and respective amount.At first, because all states " s " are zero, all inputs on the level 94 of register 76 all are zero.On the first order 96 of input register 74, there is not the trellis bit stream hyte, but has the trellis bit stream hyte of previous identification: the position u1 on the level 98
0, u1
1, u1
2, u1
3Position u2 on the level 100
0, u2
1, u2
2, u2
3And the position u3 on the level 102
0, u3
1, u3
2, u3
3When the zero condition in the level 94 of they and register 76 exists together, Galois field linear transformer matrix 60b prediction output and in output register 104, produce it in one-period immediately.Present status condition s0
0, s0
1, s0
2, s0
3Also reside in the output register 104 and feed back to status register 76 the level 94, then each group in next four position of group and this state are handled together so that next output to be provided in output register 104, thereby carry out with reference to Fig. 3 A, 3B, 4 and 5 computings of explaining.Each unit 62a among Fig. 7 can comprise the partial sum gate 110 that an output terminal 112 is connected with next unit and the output of input end 114 and previous element is connected, but the input end of first module and zero is connected and the output of this matrix is represented in each last unit in capable in the row.116 pairs of partial sum gates 110 of AND gate provide another input, thereby and programmable storage device be write signal on trigger 118 line of response 120 and control AND gate 116 forbid start unit 62a.Each programmable memory cell or trigger 118 can be independent of the remaining element realization on a separate plane 122 as shown in Figure 6.Thereby then this control circuit simply the programmable plane 122 of addressing trigger so that configuration or reconfigure this matrix and realize service for any concrete grid.
This diagram in Fig. 8 illustrates, and wherein controller circuitry 130, and for example DSP, microprocessor or sequencer are controlled one or more memory planes 122,122a, 122b, 122n.At United States Patent (USP) 3,658, the structure of Galois field linear transformer shown in 864 and auxiliary circuit, this paper integral body is included it as a reference.The programming of programmable storage device 122,122a, 122b...122n is not limited to only reshuffle this matrix for different grid operations, but can also between the grid computing, reshuffle it, for example finish the various displacements between grid incoming bit stream and the grid delivery channel symbol.There are two kinds of displacement type that realize by the start unit 62 of reshuffling matrix 60.The first kind relates to the displacement that input and output hyte quantity equates.Each row and column to matrix only starts a unit in the case.Second type relates to the displacement (expansion) of carry-out bit more than the input position.In every row of matrix, only start a unit in the case.In this typical case of two types displacement shown in Fig. 9 A-9H, wherein Fig. 9 A represents exchange (BitFlip) displacement before and after the position, Fig. 9 B represent the position interweave (Bit Interleave) displacement, Fig. 9 C represents byte exchange (Byte Swap) displacement, Fig. 9 D represents position deinterleave (Bit Deinterleave), Fig. 9 E represents byte unpack (Byte Unpack), Fig. 9 F represents position expansion (Bit Expand), Fig. 9 G represents byte packing (Byte Pack), and Fig. 9 H represents dextroposition and merge byte (Shift Right and Merge Byte).
Following leading case integral body is included as a reference: the title that Stein etc. applied on January 18th, 2002 is No. 10/051,533, the U.S. Patent application (AD-239J) of " GALOIS FIELD LINEAR TRANSFORMER (Galois field linear transformer) "; The title that Stein etc. applied on June 12nd, 2002 is No. 10/170,267, the U.S. Patent application (AD297J) of " PROGRAMMABLE DATA ENCRYPTIONENGINE (programmable data encryption equipment) "; The title that Stein etc. applied on May 1st, 2002 is No. 10/136,170, the U.S. Patent application (AD-300J) of " PROCONFIGURABLE INPUT GALOIS FIELD LINEARTRANSFORMER SYSTEM (reconfigurable input galois field linear transformer system) ".
Although in some figure and not at special characteristic of the present invention shown in other figure, this just for convenience because every kind of feature can with make up according in the further feature of the present invention any or all.Speech used herein " comprises ", " comprising ", " having " and " having " are extensively and synthetically to explain and do not limit any physical interconnections.In addition, among the application disclosed any embodiment should not become be unique possible embodiment.
The insider can it is contemplated that other embodiment from following claims.
Claims (8)
1. Galois field linear transformer trellis system comprises:
A Galois field linear transformer matrix that comprises a plurality of unit;
An input selection circuit is used for described matrix is provided at a plurality of inputs position of one or more trellis bit stream and a grid state output of described matrix; And
A programmable storage device, be used for to described a plurality of unit programme and with described matrix configuration in pairs described one or more trellis bit stream and the output of grid state carry out multicycle Galois Field linear transformation, so that a plurality of grid delivery channel symbols and new grid state output to be provided in the single cycle.
2. Galois field linear transformer trellis system as claimed in claim 1, wherein, each unit comprises an XOR circuit and a "AND" circuit, and the output terminal of described "AND" circuit is connected with this XOR circuit and input end is connected with the described input selection circuit that is used to receive described input position.
3. Galois field linear transformer trellis system as claimed in claim 1, wherein said programmable storage device comprises a plurality of storage unit, each storage unit is programmed to start a different Galois Field linear transformation.
4. Galois field linear transformer trellis system as claimed in claim 1 comprises a controller circuitry, is used to reshuffle described programmable storage device so that described grid delivery channel signpermutation is become predesigned order.
5. Galois field linear transformer trellis system as claimed in claim 1, comprise a controller circuitry, with a unit of each row and column of only starting described matrix given input bit pattern is replaced as a different output bit pattern thereby be used for reshuffling described programmable storage device.
6. Galois field linear transformer trellis system as claimed in claim 1, wherein said input selection circuit comprises an input register, a status register and a switched system circuit, is used for optionally will being input to described matrix from the data of described input register and status register one or both of.
7. Galois field linear transformer trellis system as claimed in claim 1 comprises a controller circuitry, be used for reshuffling the unit of described programmable storage device, thereby given input bit pattern is extended to a different output bit pattern with every row of only starting described matrix.
8. Galois field linear transformer trellis system comprises:
A Galois field linear transformer matrix that comprises a plurality of unit;
An input selection circuit is used for providing a plurality of inputs position of one or more trellis bit stream and a grid state output of described matrix to described matrix; And
A programmable storage device, be used for to described a plurality of unit programme and with described matrix configuration in pairs described one or more trellis bit stream and the output of grid state carry out multicycle Galois Field linear transformation, so that grid delivery channel symbol after a plurality of displacements and new grid state output to be provided in the single cycle.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US46126703P | 2003-04-08 | 2003-04-08 | |
| US60/461,267 | 2003-04-08 | ||
| US10/753,301 | 2004-01-07 |
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| Publication Number | Publication Date |
|---|---|
| CN1926531A CN1926531A (en) | 2007-03-07 |
| CN100530157C true CN100530157C (en) | 2009-08-19 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1230058A (en) * | 1998-03-18 | 1999-09-29 | 富士通株式会社 | Method for calculating phase shift coefficients of M sequence |
| US6141786A (en) * | 1998-06-04 | 2000-10-31 | Intenational Business Machines Corporation | Method and apparatus for performing arithmetic operations on Galois fields and their extensions |
| US6230179B1 (en) * | 1997-04-18 | 2001-05-08 | Motorola, Inc. | Finite field multiplier with intrinsic modular reduction |
| US6343305B1 (en) * | 1999-09-14 | 2002-01-29 | The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University | Methods and apparatus for multiplication in a galois field GF (2m), encoders and decoders using same |
-
2004
- 2004-04-07 CN CNB2004800142079A patent/CN100530157C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6230179B1 (en) * | 1997-04-18 | 2001-05-08 | Motorola, Inc. | Finite field multiplier with intrinsic modular reduction |
| CN1230058A (en) * | 1998-03-18 | 1999-09-29 | 富士通株式会社 | Method for calculating phase shift coefficients of M sequence |
| US6141786A (en) * | 1998-06-04 | 2000-10-31 | Intenational Business Machines Corporation | Method and apparatus for performing arithmetic operations on Galois fields and their extensions |
| US6343305B1 (en) * | 1999-09-14 | 2002-01-29 | The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University | Methods and apparatus for multiplication in a galois field GF (2m), encoders and decoders using same |
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