CN100527398C - Bump structure for a semiconductor device and method of manufacture - Google Patents

Bump structure for a semiconductor device and method of manufacture Download PDF

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Publication number
CN100527398C
CN100527398C CNB2005100649588A CN200510064958A CN100527398C CN 100527398 C CN100527398 C CN 100527398C CN B2005100649588 A CNB2005100649588 A CN B2005100649588A CN 200510064958 A CN200510064958 A CN 200510064958A CN 100527398 C CN100527398 C CN 100527398C
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China
Prior art keywords
salient point
conductive
sidewall
bump structure
semiconductor device
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CNB2005100649588A
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Chinese (zh)
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CN1684253A (en
Inventor
权容焕
李忠善
姜思尹
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority claimed from KR1020040025853A external-priority patent/KR100632472B1/en
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Publication of CN100527398C publication Critical patent/CN100527398C/en
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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
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    • H01L2924/1901—Structure
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Abstract

The invention provides a semiconductor device comprising a large number of bump structures arranged along first direction of a substrate. Each bump structure has first direction width which is wider than pitch gap between bump structures sequentially arranged. At least one bump structure is equipped with a non-conductive side wall opposed to the first direction.

Description

The bump structure of semiconductor device and manufacture method
Technical field
The present invention relates to the bump structure and the manufacture method of semiconductor device.
Background technology
There is the multiple different technologies that is used between semiconductor chip or encapsulation and circuit board or other substrate, providing electrical connection.Present trend in many these technology is to use solder bump (solderbump) to be electrically connected with formation and fetches replacement wire-bonded (wiring bonding).For example, on as band year encapsulation (TCP), film, use salient point in the technology of chip (COF) and glass top chip (COG).Be called belt more widely as the technology of TCP and COF and welded (TAB) automatically.
Though reduce than the interval between the wire-bonded at the interval between the solder bump by allowing, salient point provides the advantage that is better than wire-bonded, even Bumping Technology also faces the potential restriction on the interval between the salient point.For example, in the COG technology, semiconductor chip (for example LCD driver ic (IC) encapsulation) can be welded direct on the LCD substrate.In this technology, between the relevant salient point of the pad of LCD substrate and driver IC encapsulation, ACF (anisotropic conductive film) band is set and is electrically connected to form.The ACF band is included in the conductive particle that embeds in the insulating material.Conductive particle provides electrical connection between the pad of LCD substrate and solder bump.But when the gap smaller between the salient point, the particle in the ACF band can provide the electrical connection between the salient point; Therefore cause short circuit.
Summary of the invention
The invention provides the bump structure of the barrier of a kind of removal on the interval between the solder bump of semiconductor chip or encapsulation.So, the present invention allows littler and thinner semiconductor device.
In an one exemplary embodiment, on first direction, arrange a plurality of bump structures along substrate.The width of each bump structure on first direction is greater than the spacing of the bump structure of arranged in succession.This spacing can be thought in the gap of substrate along the measurement between the plane of the opposing sidewalls of the bump structure of first direction arranged in succession.At least one bump structure has non-conductive sidewall right on first direction.Because this sidewall is non-conductive, the conductive particle that is provided with between this salient point and the salient point adjacent to non-conductive sidewall can not form short circuit between two salient points.
In an one exemplary embodiment, each bump structure has at least one non-conductive side wall surface to first direction.
In another one exemplary embodiment, each bump structure has the right non-conductive side wall surface of two opposite faces to first direction.
In an one exemplary embodiment again, each bump structure have a non-conductive side wall surface to first direction and a conductive side wall to first direction, make the conduction sidewall in the face of the conduction sidewall of another bump structure.
In another one exemplary embodiment, the bump structure array from first type to the second type alternately.The bump structure of first type has the right non-conductive side wall surface of two opposite faces to first direction, and the bump structure of second type has the right conductive side wall of two opposite faces to first direction.
For any one of the foregoing description, the bump structure of arranged in succession can be set to skew each other along substrate on second direction.
One exemplary embodiment of the present invention also comprises a plurality of along the salient point of arranging on the substrate first direction and a plurality of conductor wire that forms on second direction.Each conductor wire is relevant with one of salient point, and each conductor wire is arranged on the right sidewall of two opposite faces of the top surface of relevant salient point and salient point; The right side wall surface of two opposite faces is to second direction.Each conductor wire extends at substrate from each of the right sidewall of two opposite faces.Therefore, conductor wire helps to keep relevant salient point to be attached to substrate.
Other one exemplary embodiment of the present invention provides the method that forms the foregoing description.
Description of drawings
From the following the detailed description and the accompanying drawings that provide, the present invention will become and become apparent.In the accompanying drawing, similar element is by similar Reference numeral indication.Only the method by explanation provides the detailed description and the accompanying drawings, and therefore is not used in restriction of the present invention.
Fig. 1 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention;
Fig. 2 illustrates the profile at substrate II-II along the line shown in Figure 1;
Fig. 3 illustrates the profile at substrate III-III along the line shown in Figure 1;
Fig. 4 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention;
Fig. 5 illustrates the profile at substrate V-V along the line shown in Figure 4;
Fig. 6 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention;
Fig. 7 illustrates the profile at substrate VII-VII along the line shown in Figure 4;
Fig. 8 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention;
Fig. 9 illustrates the vertical view of the semiconductor device with three groups of bump structures;
Figure 10 A-15B illustrates the embodiment of the manufacture method of bump structure of the present invention, wherein Figure 10 A, 11A, 12,13A, 14 and 15A show the profile of the substrate during the manufacturing process, and Figure 10 B, 11B, 13B and 15B show the vertical view of the substrate during the manufacturing process.
Embodiment
The invention provides the bump structure of the barrier on the interval between a kind of solder bump of removing semiconductor chip or encapsulation.So, the present invention allows littler and thinner semiconductor device.At first, will describe several structure embodiment of the present invention, describe the method for formation bump structure of the present invention subsequently.
The first structure embodiment
Fig. 1 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention.As shown, on the insulating barrier on the substrate 200 202 on by the first direction of four-headed arrow A indication array bump structure 100.Each bump structure 100 comprises non-conductive salient point 102.Non-conductive salient point 102 has two in the face of the opposite face of first direction right sidewall 104 and two right sidewalls 106 of opposite face in the face of second direction, and second direction is basically perpendicular to first direction, is indicated by four-headed arrow B.
In an example embodiment, each salient point 102 has the height H of 2 to 30 μ m, the width W b of 10 to 50 μ m and the length L b of 20 to 200 μ m.
The conductive layer 108 that each bump structure 100 is also included within the top surface of associated salient point 102 and is provided with on right each sidewall 106 on second direction.Conductive layer 108 on salient point 102 forms the part of conductor wire 110, and conductor wire 110 extends than short distance above substrate 200 from a sidewall 104, and extends a substantial distance above substrate 200 from another sidewall 106.As shown, conductor wire 110 extends upward in second party.Long extension of conductor wire 110 led to relevant chip bonding pad 204, and wherein conductive layer 110 is electrically connected on relevant pad 204.Be appreciated that pad 204 provides conductor wire 110 and the electrical connection between the circuit (not shown) that forms on the substrate 200.
Fig. 2 illustrates at the profile of substrate II-II along the line shown in Figure 1 and Fig. 3 illustrates the profile at substrate III-III along the line shown in Figure 1.Though for purpose demonstration in Fig. 1 clearly, the bump structure of this embodiment of the present invention also is included in the passivation layer 180 that forms on the part of substrate 200, shown in Fig. 2 and 3.
Fig. 2 has shown the spacing PG between the adjacent bump structure 100 among Fig. 1.Spacing PG is two distances between the bump structure; And can be more specifically, along the gap of measuring between the plane at opposing sidewalls 104 places of the bump structure 100 of arranged in succession on the first direction at substrate 200 or passivation layer 180.In the present embodiment, the width W b of bump structure 100 is greater than spacing PG.For example, spacing PG can be approximately 10 μ m.
Because spacing PG is less than the width W b of bump structure 100, when for example using the ACF band, may be short-circuited.But, because bump structure 100 is non-conductive towards the sidewall 104 of first direction, so prevented this type of short circuit.Therefore, the invention provides the bump structure of the barrier of removal on the interval between the solder bump of semiconductor chip or encapsulation.So, the present invention allows littler and thinner semiconductor device.
The second structure embodiment
Fig. 4 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention, and Fig. 5 illustrates the profile at substrate V-V along the line shown in Figure 4.As shown, the embodiment of Fig. 4 embodiment with Fig. 1 except bump structure is identical.In the embodiment of Fig. 4, each bump structure 100 ' is identical with bump structure 100 shown in Figure 1, and just conductive layer 108 has covered one of identical sidewall 104 right on first direction.So, the conduction sidewall 104 of a bump structure 100 is in the face of the non-conductive sidewall 104 of another bump structure 100.
Because one of sidewall 104 of right bump structure 100 is non-conductive on first direction, so avoided short circuit.Therefore, the invention provides the bump structure of the barrier of removal on the interval between the solder bump of semiconductor chip or encapsulation.So, the present invention allows littler and thinner semiconductor device.
The 3rd structure embodiment
Fig. 6 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention, and Fig. 7 illustrates the profile at substrate VII-VII along the line shown in Figure 6.As shown, the embodiment of Fig. 6 embodiment with Fig. 1 except bump structure is identical.Comprise two types bump structure alternately at the embodiment of Fig. 6.The first type bump structure 100 is identical with bump structure 100 shown in Figure 1.The second type bump structure 100 " identical with bump structure 100 shown in Figure 1, except conductive layer 108 covers two right above first direction sidewalls 104.But, because two types of bump structure are along the first direction of substrate 200 alternately, the second type bump structure 100 " conduction sidewall 104 in the face of the non-conductive sidewall 104 of the first type bump structure 100.Therefore avoided short circuit.Therefore, the invention provides the bump structure of the barrier of removal on the interval between the solder bump of semiconductor chip or encapsulation.So, the present invention allows littler and thinner semiconductor device.
The 4th structure embodiment
Fig. 8 illustrates the semiconductor device with bump structure of one exemplary embodiment of the present invention.As shown, the bump structure among Fig. 8 is identical with bump structure shown in Figure 1, except the bump structure of arranged in succession on the second direction from skew each other.More specifically, bump structure 100 is divided into two groups.Bump structure 100-1 in first group has the conductor wire 110 shorter than the bump structure 100-2 in second group, and first group bump structure 100-1 replaces on first direction with second group bump structure 100-2.
Should be appreciated that as shown in Figure 8 skew bump structure 100 further helps to prevent possible short circuit.Because continuous bump structure 100 is not in line, short circuit is difficult for taking place, and because the gap between the bump structure that is in line big (for example, greater than 20 μ m), short circuit is difficult for taking place.
Though use the bump structure 100 of Fig. 1 to show and describe the embodiment of Fig. 8, be to be understood that this embodiment can be combined in any one bump structure of the preceding embodiment that describes.
In addition,, be to be understood that to form that each is from other group skew more than two groups of bump structures though illustrated two groups of bump structures that are in line.Fig. 9 illustrates the vertical view of the semiconductor device with three groups of bump structures 100.
Method embodiment
Next, will the manufacture method with semiconductor device of bump structure of the present invention be described.Only purpose is for example described this method with reference to the manufacturing of bump structure shown in Figure 1 100.With reference to Figure 10 A-15B this method is described, wherein Figure 10 A, 11A, 12,13A, 14 and 15A show the profile of the substrate during the manufacturing process, and Figure 10 B, 11B, 13B and 15B show the vertical view of the substrate during the manufacturing process.
Shown in Figure 10 A and 10B, technology begins by having chip bonding pad 204 substrates 200 formed thereon.For purpose clearly, only shown single chip bonding pad.Equally, for clear, the not device that is electrically connected of display chip pad 204, circuit etc.First passivation layer 202 is formed on the substrate 200 and patterned part 225 with exposure chip bonding pad 204.First passivation layer 202 can be SiN, SiO 2Or SiN+SiO 2, and can form by chemical vapor deposition (CVD).
Afterwards, for example, by being spin-coated on the dielectric layer that forms on the substrate as polyimides, BCB (benzocyclobutane), PBO (polyphenyl azoles), photosensitive resin etc.Dielectric layer can be formed up to the thickness of 2-30 μ m.Then, use mask composition dielectric layer to form the non-conductive salient point 102 shown in Figure 11 A and Figure 11 B.Salient point 102 can have the height of 2-30 μ m, and can have the length of width and the 50-200 μ m of 10-50 μ m.In an example embodiment, width is that 20 μ m and length are 100 μ m.
As shown in figure 12, on substrate 200, form the first metal layer 140.The first metal layer 140 can have the thickness of 0.05-1 μ m.The first metal layer 140 can have the good bonding performance and low-resistance metal forms by any, as TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, NiV/Cu etc.Equally, the first metal layer 140 can pass through formation such as pressure vapor (PVD), plating or electroless plating (electroless plating) technology.
Afterwards, shown in Figure 13 A and 13B, on substrate 200, form photoresist pattern 150.The mask that photoresist pattern 150 forms shown in Figure 13 B.Use this mask, on the part of the substrate 200 that exposes by this mask, form second metal level 160.First and second metal levels 140 and 160 form conductive layer 108 and conductor wire 110.
Second metal level 160 can be formed up to the thickness of 1-10 μ m.In an example embodiment, first and second metal levels 140 and 160 gross thickness are less than 10 μ m.Second metal level 160 can form by the multilayer of for example electroplating by Au, Ni, Cu, Pd, Ag, Pt etc. or these metals.
Afterwards, as shown in figure 14, remove photoresist pattern 150, keep bump structure 100 to be electrically connected on pad 204.Second passivation layer 180 can be formed on the substrate 200 and be patterned to expose bump structure 100, shown in Figure 15 A and 15B then.Second passivation layer can be polyimides, BCB, PBO, photosensitive resin etc., and can be applied by spin coating proceeding.
Bump structure and manufacture method can be applied to the technology of any use salient point as described above, carry chip (COF) and glass top chip (COG) on encapsulation (TCP), the film as band.And bump structure and manufacture method can be applied to make any semiconductor chip or encapsulation (for example, LCD (LCD) driver IC (IC) encapsulation) as described above.
So describe the present invention, obviously the present invention can change with many methods.Such change does not think to deviate from the present invention, and all such changes are intended to be included in the scope of the present invention.

Claims (48)

1. semiconductor device comprises:
A plurality of bump structures of on first direction, arranging along substrate, each bump structure at the width on the first direction greater than the spacing between the bump structure of arranged in succession and comprise non-conductive salient point and be arranged on conductive layer on the top surface of described non-conductive salient point at least, and the non-conductive salient point of at least one bump structure has towards first direction and the external sidewall that exposes, wherein, adjacent one another are and at least one external exposure in the described sidewall of first direction of facing with each other.
2. semiconductor device as claimed in claim 1, wherein the non-conductive salient point of each bump structure has at least one towards described first direction and the external sidewall that exposes.
3. semiconductor device as claimed in claim 2, wherein the non-conductive salient point of each bump structure has two towards described first direction and the external right sidewall of opposite face that exposes.
4. semiconductor device as claimed in claim 3, wherein in each bump structure, described conductive layer is arranged at the top surface of described non-conductive salient point and faces on the sidewall of second direction with at least one, and described conductive layer extends upward in second party on the part of described substrate from the sidewall in the face of described second direction.
5. semiconductor device as claimed in claim 4, wherein each conductive layer is electrically connected on the relevant pad on the described substrate, described relevant pad is set separates described relevant bump structure.
6. semiconductor device as claimed in claim 4, wherein each conductive layer comprises lower metal layer and last metal level at least.
7. semiconductor device as claimed in claim 4, wherein the bump structure of arranged in succession along described substrate on described second direction from departing from each other.
8. semiconductor device as claimed in claim 7, wherein said second direction is basically perpendicular to described first direction.
9. semiconductor device as claimed in claim 2, wherein the non-conductive salient point of each bump structure has one towards described first direction and the sidewall that externally exposes and one towards described first direction and the sidewall that is covered by described conductive layer, make its described sidewall that covers towards described first direction and by described conductive layer in the face of the non-conductive salient point of another bump structure towards described first direction and the described sidewall that covered by described conductive layer.
10. semiconductor device as claimed in claim 9, wherein in each bump structure, described conductive layer is arranged at the top surface of described non-conductive salient point and faces on the sidewall of second direction with at least one, and described conductive layer extends upward in second party on the part of described substrate from the sidewall in the face of described second direction.
11. semiconductor device as claimed in claim 10, wherein each conductive layer is electrically connected on the relevant pad on the described substrate, described relevant pad is set separates described relevant bump structure.
12. semiconductor device as claimed in claim 10, wherein each conductive layer comprises lower metal layer and last metal level at least.
13. semiconductor device as claimed in claim 10, wherein the bump structure of arranged in succession along described substrate on described second direction from departing from each other.
14. semiconductor device as claimed in claim 13, wherein said second direction is basically perpendicular to described first direction.
15. semiconductor device as claimed in claim 1, wherein the array of bump structure from first type to the second type alternately, the non-conductive salient point of the bump structure of described first type has two sidewalls towards described first direction and external exposure that opposite face is right, and each sidewall that the non-conductive salient point of the bump structure of described second type has is covered by described conductive layer.
16. semiconductor device as claimed in claim 15, wherein in each bump structure, described conductive layer is arranged at the top surface of described non-conductive salient point and at least one of described non-conductive salient point faced on the sidewall of second direction, and described conductive layer extends upward in second party on the part of described substrate from the sidewall in the face of described second direction.
17. semiconductor device as claimed in claim 16, wherein each conductive layer is electrically connected on the relevant pad on the described substrate, described relevant pad is set separates described relevant bump structure.
18. semiconductor device as claimed in claim 16, wherein each conductive layer comprises as above metal level of lower metal layer at least.
19. semiconductor device as claimed in claim 16, wherein the bump structure of arranged in succession along described substrate on described second direction from departing from each other.
20. semiconductor device as claimed in claim 19, wherein said second direction is basically perpendicular to described first direction.
21. semiconductor device as claimed in claim 1, wherein in each bump structure, described conductive layer is arranged at the top surface of described non-conductive salient point and at least one of described non-conductive salient point faced on the sidewall of second direction, and described conductive layer extends upward in described second party on the part of described substrate from the sidewall in the face of described second direction.
22. semiconductor device as claimed in claim 21, wherein each conductive layer is electrically connected on the relevant pad on the described substrate, described relevant pad is set separates described relevant bump structure.
23. semiconductor device as claimed in claim 21, wherein each conductive layer comprises lower metal layer and last metal level at least.
24. semiconductor device as claimed in claim 23, wherein said lower metal layer has the thickness of 0.05 to 1 μ m, and described upward metal level has the thickness of 1 to 10 μ m.
25. semiconductor device as claimed in claim 23, wherein said lower metal layer comprises at least a of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, NiV/Cu, and the described metal level of going up comprises that Au, Ni, Cu, Pd, Ag and Pt's is at least a.
26. semiconductor device as claimed in claim 1, the bump structure that arranged in succession wherein is set along substrate on second direction from departing from each other.
27. semiconductor device as claimed in claim 26, wherein said second direction is basically perpendicular to described first direction.
28. semiconductor device as claimed in claim 1, wherein said bump structure has the width of 10 to 50 μ m.
29. semiconductor device as claimed in claim 1, wherein each non-conductive salient point has the height of 2-30 μ m.
30. semiconductor device as claimed in claim 1, wherein in each bump structure, described conductive layer be arranged on two opposite faces right in the face of on the sidewall of second direction, and described conductive layer extends at substrate from each of the right sidewall of two opposite faces.
31. semiconductor device as claimed in claim 1, wherein each non-conductive salient point comprises one of polyimides, benzocyclobutane, polyphenyl azoles and photosensitive resin.
32. a semiconductor device comprises:
A plurality of non-conductive salient points are arranged on first direction along substrate, each non-conductive salient point at the width that has on the described first direction greater than the spacing between the salient point of arranged in succession;
A plurality of conductor wires, on second direction, form, each conductor wire is relevant with one of non-conductive salient point, each conductor wire be arranged at two opposite faces of the top surface of relevant described non-conductive salient point and described non-conductive salient point right in the face of on the sidewall of described second direction and expose at least one sidewall in the face of the described non-conductive salient point of described first direction, and each conductor wire extends at described substrate from each of the right sidewall of two opposite faces, wherein, adjacent one another are and face with each other in the face of at least one the external exposure in the described sidewall of described first direction.
33. a semiconductor device comprises:
A plurality of non-conductive salient points are arranged on first direction along substrate, each non-conductive salient point at the width that has on the described first direction greater than the spacing between the salient point of arranged in succession; With
A plurality of conductor wires, on second direction, form, each conductor wire is relevant with one of non-conductive salient point, top surface that each conductor wire is arranged at relevant described non-conductive salient point and relevant described non-conductive salient point one in the face of on the sidewall of described second direction and expose at least one sidewall in the face of the described non-conductive salient point of described first direction, and each conductor wire extends at described substrate from the sidewall in the face of second direction, wherein, adjacent one another are and face with each other in the face of at least one the external exposure in the described sidewall of described first direction.
34. a method that forms semiconductor device comprises:
Form a plurality of bump structures, described bump structure is arranged on first direction along substrate, each bump structure at the width that has on the described first direction greater than the spacing between the bump structure of arranged in succession and comprise non-conductive salient point, have in the face of described first direction and the external sidewall that exposes with the non-conductive salient point of at least one bump structure, wherein, adjacent one another are and face with each other in the face of at least one the external exposure in the described sidewall of described first direction.
35. method as claimed in claim 34 wherein forms step and comprises:
Form a plurality of non-conductive salient points, described non-conductive salient point is arranged on described first direction along described substrate; With
On second direction, form the conductor wire relevant with each non-conductive salient point, top surface that each conductor wire is arranged at relevant described non-conductive salient point and relevant described non-conductive salient point in the face of on the sidewall of described second direction, and each conductor wire extends at substrate from the described sidewall in the face of described second direction.
36. method as claimed in claim 34, the step of the described a plurality of non-conductive salient points of wherein said formation comprises:
The non-conductive convex point material of spin coating on described substrate; And
The described non-conductive convex point material of composition is to form described a plurality of non-conductive salient point.
37. method as claimed in claim 36, wherein each non-conductive salient point comprises one of polyimides, benzocyclobutane, polyphenyl azoles and photosensitive resin.
38. forming described a plurality of non-conductive salient point, method as claimed in claim 36, wherein said pattern step make each non-conductive salient point have the width of 10 to 50 μ m.
39. forming described a plurality of non-conductive salient point, method as claimed in claim 36, wherein said pattern step make each non-conductive salient point have the height of 2-30 μ m.
40. method as claimed in claim 35, wherein each conductor wire comprises lower metal layer and last metal level at least.
41. method as claimed in claim 40, wherein said lower metal layer has the thickness of 0.05 to 1 μ m, and described upward metal level has the thickness of 1 to 10 μ m.
42. method as claimed in claim 40, wherein said lower metal layer comprises at least a of TiW, Cr, Cu, Ti, Ni, NiV, Pd, Cr/Cu, TiW/Cu, TiW/Au, NiV/Cu, and the described metal level of going up comprises that Au, Ni, Cu, Pd, Ag and Pt's is at least a.
43. method as claimed in claim 40, the step of wherein said formation conductor wire comprises:
Form described lower metal layer; With
Use metal layer material and electroplate described lower metal layer to form the described metal level of going up.
44. method as claimed in claim 34, wherein the non-conductive salient point of each bump structure has one at least in the face of described first direction and the external sidewall that exposes.
45. method as claimed in claim 34, wherein the non-conductive salient point of each bump structure has two sidewalls in the face of described first direction and external exposure that opposite face is right.
46. method as claimed in claim 34, wherein the non-conductive salient point of each bump structure have one in the face of described first direction and the sidewall that externally exposes and one in the face of described first direction and by the sidewall that conductive layer covers, make its face described first direction and the described sidewall that covered by described conductive layer in the face of the non-conductive salient point of another bump structure in the face of described first direction and the described sidewall that covered by described conductive layer.
47. method as claimed in claim 34, the array of wherein said bump structure from first type to the second type alternately, the non-conductive salient point of the bump structure of described first type has two sidewalls in the face of described first direction and external exposure that opposite face is right, and each sidewall of the non-conductive salient point of the bump structure of described second type is all covered by conductive layer.
48. a method that forms semiconductor device comprises:
Form a plurality of non-conductive salient points, described non-conductive salient point is arranged on first direction along substrate, each non-conductive salient point at the width that has on the described first direction greater than the spacing between the salient point of arranged in succession; With
On second direction, form a plurality of conductor wires, each conductor wire is relevant with one of non-conductive salient point, top surface that each conductor wire is arranged at relevant described non-conductive salient point and relevant described non-conductive salient point in the face of on the sidewall of described second direction and expose at least one sidewall in the face of the described non-conductive salient point of described first direction, and each conductor wire extends at substrate from the described sidewall in the face of second direction, wherein, adjacent one another are and face with each other in the face of at least one the external exposure in the described sidewall of described first direction.
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US11/091,869 US20050233569A1 (en) 2004-04-14 2005-03-29 Bump structure for a semiconductor device and method of manufacture
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CN1684253A (en) 2005-10-19
DE102005018280B4 (en) 2008-02-07

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