CN100517701C - Polycrystal pieces packaging structure - Google Patents
Polycrystal pieces packaging structure Download PDFInfo
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- CN100517701C CN100517701C CN 200710164175 CN200710164175A CN100517701C CN 100517701 C CN100517701 C CN 100517701C CN 200710164175 CN200710164175 CN 200710164175 CN 200710164175 A CN200710164175 A CN 200710164175A CN 100517701 C CN100517701 C CN 100517701C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
This invention relates to a packaging structure of multiple wafers including: a first base board, a first wafer, a primary package structure and a first colloid, in which, said first wafer is adhered to the first base board, said first colloid covers said first wafer, said package structure and the surface of said first base board, and the lower surface of the package structure is adhered onto the first wafer and the package structure includes: a second base board, a second wafer and a second colloid, in which, the second base board includes a top surface and a bottom surface and connected with the first wafer, said second wafer is adhered to the top surface of the second base board and is connected with the second base board and the second colloid wraps said second wafer and part of the top surface of the second board to reduce the area arrayed by multiple package structures.
Description
The present invention is dividing an application of Chinese patent application 200410096607.0, and the applying date of original application is on December 2nd, 2004, and the original application invention and created name is " packaging structure of multiple wafers ".
Technical field
The invention relates to a kind of semiconductor package, particularly a kind of encapsulating structure that contains one encapsulating structure.
Background technology
High density for electronic product, the demand of high-performance and cost control has been quickened SoC (System On a Chip, SOC) and single encapsulation (the System In a Package of system, SIP) development, present most widely used encapsulation technology is polycrystalline sheet module encapsulation construction (Multi-Chip Module, MCM), it is the wafer of integrated difference in functionality, microprocessor (microprocessors) for example, internal memory (memory), logic element (logic), optical integrated circuit (optic ICs) and capacitor (capacitors) placed the individual package structure on one circuit board to replace before.
With reference to figure 1 and Fig. 2, show the solid and the generalized section of polycrystalline sheet module encapsulation construction commonly used respectively.Polycrystalline sheet module encapsulation construction 10 commonly used comprises: one first substrate 11, one first encapsulating structure 12, one second encapsulating structure 13 and a plurality of first soldered ball 14.
This first substrate 11 has a upper surface 111 and a lower surface 112.
This first encapsulating structure 12 comprises one first wafer 121, many first leads 122 and one first sealing 123.This first wafer 121 is attached to the upper surface 111 of this first substrate 11, and utilizes these first leads 122 to be electrically connected with this first substrate 11.This first sealing 123 coats these first substrate, 11 upper surfaces 111 of this first wafer 121, these first leads 122 and part.
This second encapsulating structure 13 comprises one second substrate 131, one second wafer 132, many second leads 133, one second sealing 134 and a plurality of second soldered balls 135.This second substrate 131 has a upper surface 1311 and a lower surface 1312.This second wafer 132 is attached to the upper surface 1311 of this second substrate 131, and utilizes these second leads 133 to be electrically connected with this second substrate 131.This second sealing 134 coats this second wafer 132, these second leads 133 and this second substrate 131 upper surfaces 1311.These second soldered balls 135 are formed at the lower surface 1312 of this second substrate 131.This second encapsulating structure 13 be in itself the encapsulation finish after, utilize these second soldered balls 135 to be incorporated into the upper surface 111 of this first substrate 11 in the mode of mounted on surface (surface mounting).
First soldered ball 14 is formed at the lower surface 112 of this first substrate 11.
In this polycrystalline sheet module encapsulation construction 10 commonly used, this first wafer 121 is a little processing wafer, this second wafer 132 is an internal memory wafer, because the size of this different internal memory wafers is all different, and the number of I/O pin is also different, when therefore different internal memory wafers is made signal integration with different little processing wafers, need its signaling path of redesign, cause cost to increase and the research and development time lengthening.In addition, in this polycrystalline sheet module encapsulation construction 10 commonly used, this first encapsulating structure 12 and this second encapsulating structure 13 are to be arranged in parallel, and shared area is bigger.
Therefore, be necessary to provide the packaging structure of multiple wafers of an innovation and rich progressive, to address the above problem.
Summary of the invention
Main purpose of the present invention provides a kind of encapsulating structure that contains one encapsulating structure, and it produces with stack manner, the bigger problem of area occupied when being arranged in parallel to reduce a plurality of encapsulating structures.
Another object of the present invention provides a kind of encapsulating structure that contains one encapsulating structure, this time encapsulating structure is for testing the packaging body of finishing, it can be used as known good crystal grain (Known-Good Die, KGB) be integrated in the encapsulating structure, because encapsulating structure test (package test) has the easy and lower-cost advantage of test compared with known good crystal grain, so can reduce manufacturing cost.
Another object of the present invention provides a kind of encapsulating structure that contains one encapsulating structure, has at least two wafers in this encapsulating structure, does not need to redesign signaling path between these wafers again.
Another purpose of the present invention provides a kind of packaging structure of multiple wafers, and it comprises: one first substrate, one first wafer, encapsulating structure and one first sealing.
This first substrate has a upper surface and a lower surface.This first die attach is in the upper surface of this first substrate, and is electrically connected with this first substrate.
This time encapsulating structure has a upper surface and a lower surface, and the lower surface of this time encapsulating structure is to be attached on this first wafer, and this time encapsulating structure comprises: one second substrate, one second wafer and one second sealing.This second substrate has a upper surface and a lower surface, and is electrically connected with this first wafer.This second die attach is in the upper surface of this second substrate, and is electrically connected with this second substrate.This second upper surface of base plate of this second wafer of this second sealant covers and part.
This first wafer of this first sealant covers, this time encapsulating structure and this first upper surface of base plate.
Description of drawings
Fig. 1 shows the schematic perspective view of polycrystalline sheet module encapsulation construction commonly used;
Fig. 2 shows the generalized section of polycrystalline sheet module encapsulation construction commonly used;
Fig. 3 shows the generalized section of first embodiment of the invention;
Fig. 4 shows the generalized section of second embodiment of the invention;
Fig. 5 shows the generalized section of third embodiment of the invention;
Fig. 6 shows the generalized section of fourth embodiment of the invention;
Fig. 7 shows the generalized section of fifth embodiment of the invention;
Fig. 8 shows the generalized section of sixth embodiment of the invention;
Fig. 9 shows the generalized section of second kind encapsulating structure among the present invention;
Figure 10 shows the generalized section of the third time encapsulating structure among the present invention;
Figure 11 shows the generalized section of seventh embodiment of the invention;
Figure 12 shows the generalized section of the 5th kind encapsulating structure among the present invention;
Figure 13 shows the generalized section of the 6th kind encapsulating structure among the present invention;
Figure 14 shows the generalized section of the 7th kind encapsulating structure among the present invention;
Figure 15 shows the generalized section of eighth embodiment of the invention;
Figure 16 shows the generalized section of ninth embodiment of the invention; And
Figure 17 shows the generalized section of tenth embodiment of the invention.
Embodiment
The invention relates to a kind of packaging structure of multiple wafers, it comprises at least one semiconductor device (semiconductor device) and at least one time encapsulating structure (sub-package), it is characterized in that this semiconductor device and this time encapsulating structure are to arrange along a longitudinal direction to be provided with, this semiconductor device can be a wafer or another time encapsulating structure.
With reference to figure 3, show the generalized section of first embodiment of the invention.The packaging structure of multiple wafers 20 of present embodiment comprises: one first substrate 21, one first wafer 22, a plurality of first lead 23, encapsulating structure 24, a plurality of privates 25, one first sealing 26 and an a plurality of soldered ball 27.
This first substrate 21 has a upper surface 211 and a lower surface 212.This first wafer 22 is attached to the upper surface 211 of this first substrate 21, and utilizes these first leads 23 to be electrically connected with this first substrate 21.Be understandable that, then not have the setting of these first leads 23 if this first wafer 22 is to be attached to this first substrate 21 in flip chip mode (flip-chip).
This time encapsulating structure 24 has a upper surface 241 and a lower surface 242, the lower surface 242 of this time encapsulating structure 24 be with an adhesive bond on this first wafer 22, this time encapsulating structure 24 comprises: one second substrate 243, one second wafer 244, a plurality of second lead 245 and one second sealing 246.
This second substrate 243 has a upper surface 2431 and a lower surface 2432, and utilizes these privates 25 to be electrically connected with this first wafer 22, and perhaps these privates 25 are electrically connected with this first substrate 21.This second wafer 244 is attached to the upper surface 2431 of this second substrate 243, and utilizes these second leads 245 to be electrically connected with this second substrate 243.This second sealing 246 coats these second substrate, 243 upper surfaces 2431 of this second wafer 244 and part.It should be noted that, this second sealing 246 does not cover this second substrate, 243 upper surfaces 2431 fully, and the part that these second substrate, 243 upper surfaces 2431 are not covered by this second sealing 246 is provided with a plurality of weld pads (not shown), for the usefulness of these privates 25 connections.
This time encapsulating structure 24 is a kind of being selected from by Land Grid Array (Land Grid Array, LGA), square flat non-pin formula (Quad Flat Non-leaded, QFN), double little outward appearance do not have pinned (Small Outline Non-leaded, SON) and cover the group that brilliant film encapsulating structures such as (Chip On Film) is formed.In the present embodiment, this time encapsulating structure 24 is the Land Grid Array encapsulating structure, its lower surface 2432 has the usefulness of a plurality of bond pads (landing pad) for test, and this time encapsulating structure 24 is by adhering on this first wafer 22, to cut the waste after the test again.
This first sealing 26 coats this first wafer 22, this time encapsulating structure 24, these first leads 23, these privates 25 and this first upper surface of base plate 211.These soldered balls 27 are formed at the lower surface 212 of this first substrate 21, use for this first wafer 22 to be electrically connected with external device whereby.
This first wafer 22 and second wafer 244 can be optical crystal chip, logic wafer, little processing wafer or internal memory wafer.In the present embodiment, this first wafer 22 is a little processing wafer, and this second wafer 244 is an internal memory wafer.
With reference to figure 4, show the generalized section of second embodiment of the invention.The present embodiment and first embodiment are roughly the same, do not exist together and only add a fin 28 for present embodiment, it comprises a heat sink body 281 and a support portion 282, and this support portion 282 is outwards to be extended downwards by this heat sink body 281, in order to support this heat sink body 281.The upper surface of this heat sink body 281 is exposed in the air, to increase radiating efficiency.
With reference to figure 5, show the generalized section of third embodiment of the invention.The present embodiment and first embodiment are roughly the same, do not exist together only in the present embodiment, this first wafer 22 is exchanged with the position of this time encapsulating structure 24, promptly this first wafer 22 is the upper surfaces 241 that are stacked at this time encapsulating structure 24, and the lower surface 242 of this time encapsulating structure 24 adheres to the upper surface 211 of this first substrate 21.In addition, in the present embodiment, these privates 25 are electrically connected the upper surface 211 of these second substrate, 243 upper surfaces 2431 and this first substrate 21.In addition, these privates 25 can electrically connect this first wafer 22 and this first substrate 21, and perhaps these privates 25 can electrically connect this first wafer 22 and this second substrate 243.
With reference to figure 6, show the generalized section of fourth embodiment of the invention.Present embodiment is to add a wafer in first embodiment.The packaging structure of multiple wafers 30 of present embodiment, it comprises: one first substrate 31, one first wafer 32, a plurality of first lead 33, encapsulating structure 34, a plurality of privates 35, one first sealing 36, a plurality of soldered ball 37, one the 3rd wafer 38, a plurality of privates 39, a plurality of the 5th lead 391.
This first substrate 31 has a upper surface 311 and a lower surface 312.This first wafer 32 is attached to the upper surface 311 of this first substrate 31, and utilizes these first leads 33 to be electrically connected with this first substrate 31.Be understandable that, then not have the setting of these first leads 33 if this first wafer 32 is to be attached to this first substrate 31 in flip chip mode (flip-chip).
This time encapsulating structure 34 has a upper surface 341 and a lower surface 342, the lower surface 342 of this time encapsulating structure 34 be with an adhesive bond on this first wafer 32, this time encapsulating structure 34 comprises: one second substrate 343, one second wafer 344, a plurality of second lead 345 and one second sealing 346.
This second substrate 343 has a upper surface 3431 and a lower surface 3432, and utilizes these privates 35 to be electrically connected with this first wafer 32.This second wafer 344 is attached to the upper surface 3431 of this second substrate 343, and utilizes these second leads 345 to be electrically connected with this second substrate 343.This second sealing 346 coats these second substrate, 343 upper surfaces 3431 of this second wafer 344 and part.It should be noted that, this second sealing 346 does not cover this second substrate, 343 upper surfaces 3431 fully, and the part that these second substrate, 343 upper surfaces 3431 are not covered by this second sealing 346 is provided with a plurality of weld pads (not shown), for the usefulness of these privates 35 connections.
This time encapsulating structure 34 is that a kind of being selected from by Land Grid Array, square flat non-pin formula, double little outward appearance do not have pinned and cover the group that encapsulating structures such as brilliant film are formed.In the present embodiment, this time encapsulating structure 34 is to be the Land Grid Array encapsulating structure, its lower surface 3432 has the usefulness of a plurality of bond pads (landing pad) for test, and this time encapsulating structure 34 is by adhering on this first wafer 32, to cut the waste after the test again.
The 3rd wafer 38 is attached to the upper surface 341 of this time encapsulating structure 34, and utilizes these privates 39 to be electrically connected with this first substrate 31, or utilizes these grade in an imperial examination five leads 391 to be electrically connected with this first wafer 32.
This first sealing 36 coats this first wafer 32, this time encapsulating structure 34, these first leads 33, these privates 35, the 3rd wafer 38, these privates 39 and this first upper surface of base plate 311.These soldered balls 37 are formed at the lower surface 312 of this first substrate 31.
This first wafer 32, second wafer 344 and the 3rd wafer 38 can be optical crystal chip, logic wafer, little processing wafer or internal memory wafer.In the present embodiment, this first wafer 32 is a little processing wafer, and this second wafer 344 is an internal memory wafer, and the 3rd wafer 38 is another little processing wafer.
With reference to figure 7, show the generalized section of fifth embodiment of the invention.Present embodiment and the 4th embodiment are roughly the same, do not exist together is between this first wafer 32 and this time encapsulating structure 34 for the 3rd wafer 38 of present embodiment only, also be, this first wafer 32 is attached to the upper surface 311 of this first substrate 31, the 3rd wafer 38 is attached on this first wafer 32, and the lower surface 342 of this time encapsulating structure 34 is attached on this 3rd wafer 38.The length of this second substrate 343 is less than the length of the 3rd wafer 38.
In the present embodiment, these first leads 33 are in order to be electrically connected this first wafer 32 and first substrate 31.These second leads 345 are in order to be electrically connected this second wafer 344 and this second substrate 343.These privates 35 are in order to be electrically connected this second substrate 343 and this first wafer 32.These privates 392 are in order to be electrically connected this second substrate 343 and the 3rd wafer 38.These grade in an imperial examination five leads 391 are in order to be electrically connected this first wafer 32 and the 3rd wafer 38.
With reference to figure 8, show the generalized section of sixth embodiment of the invention.Present embodiment and the 4th embodiment are roughly the same, only do not exist together and all to be positioned on this time encapsulating structure 34 for first wafer 32 of present embodiment and the 3rd wafer 38, also be, the lower surface 342 of this time encapsulating structure 34 is attached to this first upper surface of base plate 311, upper surface 341, the three wafers 38 that this first wafer 32 is attached to this time encapsulating structure 34 are attached on this first wafer 32.
In the present embodiment, these first leads 33 are in order to be electrically connected this first wafer 32 and first substrate 31.These second leads 345 are in order to be electrically connected this second wafer 344 and this second substrate 343.These privates 35 are in order to being electrically connected this first substrate 31 and this second substrate 343, or are electrically connected this second substrate 343 and this first wafer 32 (not shown).These privates 392 are in order to be electrically connected this first substrate 31 and the 3rd wafer 38.These grade in an imperial examination five leads 391 are in order to be electrically connected this first wafer 32 and the 3rd wafer 38.
With reference to figure 9, show the generalized section of second kind encapsulating structure.In the above-described embodiments, this second wafer of these first kind encapsulating structure 24,34 is the upper surface that directly is attached to this second substrate.In this figure, this second kind time encapsulating structure 40 has a upper surface 401 and a lower surface 402, and it comprises: one second substrate 41, one second wafer 42, a plurality of second lead 43 and one second sealing 44.
This second substrate 41 has a upper surface 411, a lower surface 412 and a perforate 45.This second wafer 42 is attached in the perforate 45 of this second substrate 41, and utilizes these second leads 43 to be electrically connected with this second substrate 41.This second sealing 44 coats these second substrate, 41 upper surfaces 411 of this second wafer 42 and part.It should be noted that, this second sealing 44 does not cover this second substrate, 41 upper surfaces 411 fully, and the part that these second substrate, 41 upper surfaces 411 are not covered by this second sealing 44 has at least one lead wire welding mat (finger pad) 46 and at least one detection welding pad (test pad) 47, this lead wire welding mat 46 is in order to connecting other leads, and this detection welding pad 47 is to use for test.In this figure, this lead wire welding mat 46 is positioned at the upper surface 411 of this second substrate 41, and this detection welding pad 47 is positioned at the lower surface 412 of this second substrate 41.
With reference to Figure 10, show the generalized section of the third time encapsulating structure.Shown in this figure the third time encapsulating structure 40 is roughly the same with second kind encapsulating structure 40 shown in Figure 9, do not exist together only is that this lead wire welding mat 46 and this detection welding pad 47 all are positioned at the upper surface 411 of this second substrate 41 in the third time encapsulating structure 40 shown in this figure.
With reference to Figure 11, show the generalized section of seventh embodiment of the invention.The present embodiment and first embodiment are roughly the same, only do not exist together in the present embodiment, and this time encapsulating structure 24 is to turn over turnback.Therefore, these second substrate, 243 upper surfaces 2431 are the upper surface of this time encapsulating structure 24, and the lower surface of this second sealing 246 is the lower surface of this time encapsulating structure 24.This second wafer 244 is attached to this second substrate, 243 lower surfaces 2432.This of this enforcement time encapsulating structure 24 is the 4th kind encapsulating structure 24.
With reference to Figure 12, show the generalized section of the 5th kind encapsulating structure.In above-mentioned the 7th embodiment, this second wafer 244 of this time encapsulating structure 24 is the lower surfaces 2432 that directly are attached to this second substrate 243.In this figure, the 6th kind time encapsulating structure 50 has a upper surface 501 and a lower surface 502, and it comprises: one second substrate 51, one second wafer 52, a plurality of second lead 53 and one second sealing 54.
This second substrate 51 has a upper surface 511, a lower surface 512 and a perforate 55.This second wafer 52 is attached in the perforate 55 of this second substrate 51, and utilizes these second leads 53 to be electrically connected with this second substrate 51.This second sealing 54 coats these second substrate, 51 lower surfaces 512 of this second wafer 52 and part.It should be noted that, this second sealing 54 does not cover this second substrate, 51 lower surfaces 512 fully, and the part that these second substrate, 51 lower surfaces 512 are not covered by this second sealing 54 has at least one lead wire welding mat (finger pad) 56 and at least one detection welding pad (test pad) 57, this lead wire welding mat 56 is in order to connecting other leads, and this detection welding pad 57 is to use for test.In this figure, this lead wire welding mat 56 is the upper surfaces 511 that are positioned at this second substrate 51, and this detection welding pad 57 is the lower surfaces 512 that are positioned at this second substrate 51.
With reference to Figure 13, show the generalized section of the 6th kind encapsulating structure.Shown in this figure the 6th kind time encapsulating structure 50 is roughly the same with the 5th kind encapsulating structure 50 shown in Figure 12, do not exist together only is that this lead wire welding mat 56 and this detection welding pad 57 all are positioned at the upper surface 511 of this second substrate 51 in time encapsulating structure 50 of the 6th kind shown in this figure.
With reference to Figure 14, show the generalized section of the 7th kind encapsulating structure.Shown in this figure the 7th kind time encapsulating structure 50 is roughly the same with the 6th kind encapsulating structure 50 shown in Figure 13, do not exist together only in time encapsulating structure 50 of the 7th kind shown in this figure, this lead wire welding mat 56 is the lower surfaces 512 that are positioned at this second substrate 51, and this detection welding pad 57 is the upper surfaces 511 that are positioned at this second substrate 51.
With reference to Figure 15, show the generalized section of eighth embodiment of the invention.The packaging structure of multiple wafers 60 of present embodiment, it comprises encapsulating structure 61, an encapsulating structure 62, one the 3rd substrate 63, one the 3rd sealing 64, a plurality of privates 65, a plurality of privates 66 and an a plurality of soldered ball 67 for the second time for the first time.
It is in order to coat this of encapsulating structure 61, this encapsulating structure 62 and the 3rd substrate 63 upper surfaces 631 that the 3rd substrate 63 has a upper surface 631 and a lower surface 632, the three sealings 64 first time second time.These privates 65 be in order to be electrically connected the 3rd substrate 63 and this first time encapsulating structure 61.These privates 66 be in order to be electrically connected the 3rd substrate 63 and this second time encapsulating structure 62.These soldered balls 67 are formed at the lower surface 632 of the 3rd substrate 63.
This, encapsulating structure 61 had a upper surface 611 and a lower surface 612 first time, and it comprises: one first substrate 613, one first wafer 614, one first sealing 615 and a plurality of first lead 616.This first substrate 613 has a upper surface 6131 and a lower surface 6132.This first wafer 614 is to see through these first leads 616 to be electrically connected with this first substrate 613.This first sealing 615 has a upper surface and a lower surface, and it coats this first wafer 614 and this first substrate 613.
This, encapsulating structure 62 had a upper surface 621 and a lower surface 622 second time, and it comprises: one second substrate 623, one second wafer 624, one second sealing 625 and a plurality of second lead 626.This second substrate 623 has a upper surface 6231 and a lower surface 6232.This second wafer 624 is to see through these second leads 626 to be electrically connected with this second substrate 623.This second sealing 625 has a upper surface and a lower surface, and it coats this second wafer 624 and this second substrate 623.
In the present embodiment, in first time encapsulating structure 61, this first wafer 614 directly is attached to the upper surface 6131 of this first substrate 613.In second time encapsulating structure 62, this second wafer 624 directly is attached to the upper surface 6231 of this second substrate 623.Yet be understandable that, for the first time encapsulating structure 61 or should the second time encapsulating structure 62 can replace to second kind of inferior encapsulating structure 40 or the third time encapsulating structure 40 shown in Figure 10 shown in Figure 9.
In the present embodiment, for having mutually stacked first time of encapsulating structure 61 and encapsulating structure 62 for the second time.Yet be understandable that, the packaging structure of multiple wafers 60 of present embodiment can more comprise one the 3rd wafer, its position can be on second time encapsulating structure 62, or at this for the first time encapsulating structure 61 and this for the second time between the encapsulating structure 62, or at this for the first time between encapsulating structure 61 and the 3rd substrate 63.
With reference to Figure 16, show the generalized section of ninth embodiment of the invention.Present embodiment and the 8th embodiment are roughly the same, and different is, the encapsulating structure second time of present embodiment 62 is to turn over turnback.It should be noted that this of encapsulating structure 61 also turning 180 degree first time.
In the present embodiment, in the encapsulating structure 62, this second wafer 624 directly is attached to the lower surface 6232 of this second substrate 623 for the second time.Yet be understandable that the encapsulating structure 62 second time of this upset can replace to the 5th kind encapsulating structure 50 shown in Figure 12, or the 6th kind encapsulating structure 50 shown in Figure 13, or the 7th kind encapsulating structure 50 shown in Figure 14.
In the present embodiment, for having mutually stacked first time of encapsulating structure 61 and encapsulating structure 62 for the second time.Yet be understandable that, the packaging structure of multiple wafers 60 of present embodiment can more comprise one the 3rd wafer, its position can be on second time encapsulating structure 62, or at this for the first time encapsulating structure 61 and this for the second time between the encapsulating structure 62, or at this for the first time between encapsulating structure 61 and the 3rd substrate 63.
With reference to Figure 17, show the generalized section of tenth embodiment of the invention.The 6th embodiment of present embodiment and Fig. 8 is roughly the same, and difference only is that this time encapsulating structure 34 of present embodiment is inverted.
The encapsulating structure 30 of the multiple encapsulation of present embodiment comprises: one first substrate 31, one first wafer 32, a plurality of first lead 33, encapsulating structure 34, a plurality of privates 35, one first sealing 36, a plurality of soldered ball 37, one the 3rd wafer 38, a plurality of privates 392, a plurality of the 5th lead 391.
This first substrate 31 has a upper surface 311 and a lower surface 312.This time encapsulating structure 34 has a upper surface 341 and a lower surface 342, the lower surface 342 of this time encapsulating structure 34 is the upper surfaces that adhere to this first substrate 31 with a viscose glue, and this time encapsulating structure 34 comprises: one second substrate 343, one second wafer 344, a plurality of second lead 345 and one second sealing 346.
This second substrate 343 has a upper surface 3431 and a lower surface 3432, and utilizes these privates 35 to be electrically connected with this first substrate 31.This second wafer 344 is the lower surfaces 3433 that are attached to this second substrate 343, and utilizes these second leads 345 to be electrically connected with this second substrate 343.This second sealing 346 coats the lower surface 3432 of this second wafer 344 and this second substrate 343 of part.
This first wafer 32 is attached to the upper surface 3411 of this time encapsulating structure 34, and utilizes these first leads 33 to be electrically connected with this first substrate 31.The 3rd wafer 38 is attached on this first wafer 32, and utilizes these privates 392 to be electrically connected with this first substrate 31, or utilizes these grade in an imperial examination five leads 391 to be electrically connected with this first wafer 32.
This first sealing 36 coats this first wafer 32, this time encapsulating structure 34, these first leads 33, these privates 35, the 3rd wafer 38, these privates 392, this grade in an imperial examination five leads 391 and this first upper surface of base plate 311.These soldered balls 37 are formed on the lower surface 312 of this first substrate 31.
The foregoing description only is explanation principle of the present invention and effect thereof, and unrestricted the present invention, so the those skilled in the art makes amendment to the foregoing description and changes and still do not break away from spirit of the present invention.Interest field of the present invention is listed in the claim as described above.
Claims (8)
1. packaging structure of multiple wafers, it comprises:
One first substrate, it has a upper surface and a lower surface;
One first wafer, it is attached to the upper surface of this first substrate, and is electrically connected with this first substrate;
One the 3rd wafer, it is attached to the upper surface of this first wafer, and is electrically connected with this first substrate;
An encapsulating structure, it has a upper surface and a lower surface, and the lower surface of this time encapsulating structure is attached to the upper surface of the 3rd wafer, and this time encapsulating structure comprises:
One second substrate, it has a upper surface and a lower surface, and is electrically connected with this first substrate, and the length of this second substrate is less than the length of the 3rd wafer;
One second wafer, it is attached to the upper surface of this second substrate, and is electrically connected with this second substrate; And
One second sealing, it coats this second upper surface of base plate of this second wafer and part; And
One first sealing, it coats this first wafer, the 3rd wafer, this time encapsulating structure and this first upper surface of base plate.
2. structure according to claim 1, wherein this second substrate has a perforate, and this second die attach is in this perforate, and second substrate has at least one lead wire welding mat and at least one detection welding pad, this lead wire welding mat is in order to connecting other leads, and this detection welding pad is to use for test.
3. structure according to claim 2, wherein this lead wire welding mat and this detection welding pad all are positioned at the upper surface of this second substrate.
4. structure according to claim 2, wherein this lead wire welding mat is the upper surface that is positioned at this second substrate, this detection welding pad is the lower surface that is positioned at this second substrate.
5. packaging structure of multiple wafers, it comprises:
One first substrate, it has a upper surface and a lower surface;
An encapsulating structure, it has a upper surface and a lower surface, and the lower surface of this time encapsulating structure is attached to the upper surface of this first substrate, and this time encapsulating structure comprises:
One second substrate, it has a upper surface and a lower surface, and is electrically connected with this first substrate;
One second wafer, it is attached to the upper surface of this second substrate, and is electrically connected with this second substrate; And
One second sealing, it coats this second upper surface of base plate of this second wafer and part;
One first wafer, it is attached to the upper surface of this time encapsulating structure, and is electrically connected with this first substrate;
One the 3rd wafer, it is attached to the upper surface of this first wafer, and is electrically connected with this first wafer; And
One first sealing, it coats this first wafer, the 3rd wafer, this time encapsulating structure and this first upper surface of base plate.
6. structure according to claim 5, wherein this second substrate has a perforate, and this second die attach is in this perforate, and second substrate has at least one lead wire welding mat and at least one detection welding pad, this lead wire welding mat is in order to connecting other leads, and this detection welding pad is to use for test.
7. structure according to claim 6, wherein this lead wire welding mat and this detection welding pad all are positioned at the upper surface of this second substrate.
8. structure according to claim 6, wherein this lead wire welding mat is the upper surface that is positioned at this second substrate, this detection welding pad is the lower surface that is positioned at this second substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710164175 CN100517701C (en) | 2004-12-02 | 2004-12-02 | Polycrystal pieces packaging structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710164175 CN100517701C (en) | 2004-12-02 | 2004-12-02 | Polycrystal pieces packaging structure |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100966070A Division CN100416825C (en) | 2004-12-02 | 2004-12-02 | Packaging structure of poly crystal sheet |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101136398A CN101136398A (en) | 2008-03-05 |
| CN100517701C true CN100517701C (en) | 2009-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200710164175 Active CN100517701C (en) | 2004-12-02 | 2004-12-02 | Polycrystal pieces packaging structure |
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| Country | Link |
|---|---|
| CN (1) | CN100517701C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101685545B1 (en) * | 2015-04-29 | 2016-12-12 | 주식회사 바른전자 | Multi die stacking method using Printed Circuit Board and semiconductor package employing it |
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| Publication number | Publication date |
|---|---|
| CN101136398A (en) | 2008-03-05 |
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