CN100517499C - Semiconductor memory device and method of operating same - Google Patents

Abstract

There are many inventions described and illustrated herein. In a first aspect, the present invention is directed to a memory device and technique of reading data from and writing data into memory cells of the memory device. In this regard, in one embodiment of this aspect of the invention, the memory device and technique for operating that device that minimizes, reduces and/or eliminates the debilitating affects of the charge pumping phenomenon. This embodiment of the present invention employs control signals that minimize, reduce and/or eliminate transitions of the amplitudes and/or polarities. In another embodiment, the present invention is a semiconductor memory device including a memory array comprising a plurality of semiconductor dynamic random access memory cells arranged in a matrix of rows and columns. Each semiconductor dynamic random access memory cell includes a transistor having a source region, a drain region, a electrically floating body region disposed between and adjacent to the source region and the drain region, and a gate spaced apart from, and capacitively coupled to, the body region. Each transistor includes a first state representative of a first charge in the body region, and a second data state representative of a second charge in the body region. Further, each row of semiconductor dynamic random access memory cells includes an associated source line which is connected to only the semiconductor dynamic random access memory cells of the associated row.

Description

Integrated circuit (IC)-components and semicondctor storage array

The cross reference of related application

The application requires right of priority: the U.S. Provisional Application sequence number 60/470,384 that on May 13rd, (1) 2003 submitted to is entitled as " Method of Operating Semiconductor Memory Device "; And the U.S. Provisional Application sequence number 60/470 of submission on May 13rd, (2) 2003,318, be entitled as " Dual PortOne Transistor DRAM Memory Cell and Extension to Multi-Port MemoryCell " (hereinafter being referred to as " provisional application ").Here by reference, quote the full content of these provisional application.

Technical field

The present invention relates to the method for semiconductor dynamic random access storer (" DRAM ") unit, array and/or device and control and/or operation semiconductor memory cell array and/or device; Specifically, relate to semiconductor dynamic random access storer (" DRAM ") unit, array and/or device in one aspect, wherein this memory cell comprises that the electricity that wherein stores electric charge floats.

Background technology

The DRAM unit of many dissimilar and/or forms is arranged, for example comprise the semiconductor memory cell that is made of access transistor and capacitor, it stores the electric charge of representing the bistable memory state.Access transistor serves as charging and the discharge that is used for control capacitor and reads and write the switch (promptly to capacitor charge or discharge) of logic state to capacitor.

Although by the DRAM device that has adopted " transistor-a capacitor " memory cell, but realize sizable integration density, but such device tends to be subjected to the restriction and the restriction of memory cell size.About this point, routine techniques has adopted and has piled up and/or trench capacitor approaches, thus capacitor partly be arranged on the access transistor and/or under.

In addition, adopting the DRAM device of " transistor-a capacitor " memory cell to trend towards using with the inequality and/or incompatible production technology of the production technology that is used for logical device (for example microprocessor) makes.As a result, " transistor-a capacitor " memory cell is integrated in the logical device usually not only complexity but also costliness.

The dynamic random access storage unit (hereinafter being called " semiconductor memory device patent application ") that is to submit on June 10th, 2003, describe and illustrated another type in the non-temporary patent application that be assigned sequence number 10/450,238, that be entitled as " Semiconductor Device ".Referring to Figure 1A and 1B, this semiconductor memory device patent application especially also discloses semiconductor DRAM device 10, and wherein each memory cell 12 is made of the transistor 14 with tagma 18, source region 20 and drain region 22 that grid 16, electricity float.Tagma 18 is set between source region 20 and the drain region 22 and is adjacent with it.By applying suitable control signal to selected word line 24, selected source line 26 and/or selected bit line 28, data are written in the selected memory cell or from wherein reading.In response, electric charge carrier is accumulated in the electric float zone 18 or from wherein penetrating or ejecting, wherein: data mode is limited by the charge carrier quantity in the electric float zone 18.

Specifically, in one embodiment, the memory cell of semiconductor memory device patent application is by accumulating majority carrier (electronics or hole) 30 or they operate (seeing Fig. 2 A and 2B) from ejaculation/ejection wherein in the tagma 18 of N channel transistor.About this point, for example in the tagma 18 of memory cell 12, accumulate majority carrier (in this example, being " hole ") 30 and represent logic high or " 1 " data mode (seeing Fig. 2 A) via near the impact ionization source region 20 and/or the drain region 22.For example 18 penetrate or ejection majority carrier 30 is represented logic low or " 0 " (seeing Fig. 2 B) via forward bias source knot and/or drain electrode/body knot and from the tagma.

The data that various technology can be used to store in the storage component part of read semiconductor storage component part patented claim (or write wherein data).For example, current sense amplifier (undeclared) can be in order to read the data of storage in the memory cell 12.About this point, the current sense amplifier can compare memory cell current and reference current, for example the electric current of reference unit (undeclared).According to this relatively, can determine whether memory cell 12 comprises logic high (comprising more relatively majority carrier 30 in the tagma 18) or logic low data state (comprising less relatively majority carrier 28 in body region 18).

It should be noted that transistor 14 can be symmetry or symmetrical device.At transistor 14 is that source electrode and drain region are interchangeable basically in the situation of symmetry.Yet, be in the situation of symmetrical device at transistor 14, the source electrode of transistor 14 has different electricity, physics, doping content and/or dopant profiles (profile) feature with the drain region.So the source electrode of symmetrical device or drain region are generally not interchangeable.

For example can on bit line 28i, use negative drain voltage to come oxide-semiconductor control transistors 14, the hole is removed to write logic low (being binary condition " 0 ") from electric float zone 18 through drain electrode 22.In this case, the negative voltage that is applied to the grid 16 of other (unselected) memory cells in the memory array of device 10 is essential, with writing (logic low) operating period when applying negative bit-line voltage, in being connected to other unit of same bit lines 28i, avoid " leakage current ".

Other operations can use the positive voltage that is applied to word line 24 to carry out such as writing logic high data mode (binary one) and reading of data.So, the transistor 14 of device 10 is pulsed between positive gate bias and negative gate bias termly, wherein: this positive gate bias (1) drives majority carrier (is the hole for the N channel transistor) and leaves the gate insulator 32 of transistor 14 and the interface between the tagma 18, and (2) cause that minority carrier (is electronics for the N channel transistor) flows to the raceway groove that is formed under the grid 16 from source region 20 and drain region 22, this negative gate bias cause that majority carrier (is the hole for the N channel transistor) accumulates in the grid 16 of transistor 14 and the interface between the tagma 18 or near.

Referring to Fig. 3 A, the positive voltage that is applied to grid 16 provides positive gate bias, its channel shape that causes (1) minority carrier 34 is formed under the grid 16, and (2) majority carrier 30 accumulates in tagma 18 in " on the contrary " zone at interface in grid 16 and tagma 18.Here, minority carrier (being the electronics in the N channel transistor) can flow in the raceway groove under the interface of gate oxide 32 and floater area 18, and wherein some of minority carrier 34 " are caught (trap) " by the institute of the defective in the semiconductor or are " trapped " (generally be by from a kind of material type to another kind of material type transformation produced or caused) therein.

Referring to Fig. 3 B, when negative voltage was applied to grid 16, this gate bias was born, and it eliminates the raceway groove of the minority carrier 34 under the grid 16 (with gate oxide 34) substantially.Yet, some of minority carrier still in boundary defect, be hunted down (generally being expressed as electronics 36).

Some electronics of catching 36 are compound with the majority carrier that is attached to grid 16 (because negative gate bias), can reduce (for example seeing Fig. 3 C) in time so be arranged in the net charge of the majority carrier 30 of floater area 18.This phenomenon can be characterized by electric charge pumping (pump).Like this, can reduce the clean amount of electric charge in the memory cell 12 in the pulsation between the gate bias of positive and negative (reading with write operation during), it can eliminate the data that store in the memory cell 12 again gradually.

It should be noted that in order to produce efficient electric charge pumping phenomenon, the free electronic concentration (n of surface during counter-rotating (inversion) _e) should be fully big, thereby interface trap can be during transistor be in counter-rotating trapped electron.The time constant that is used for electron capture can be characterized by:

${\mathrm{\τ}}_e=\frac{1}{v_{\mathrm{th}}\·{\mathrm{\σ}}_n\·n_e}$

Therefore, at τ _e=3ns (typical duration of pulse in the senior DRAM storer), hot speed v _Th=1 * 10 ⁷Cm/s and capture cross-section σ _n=2 * 10 ^-16Cm ²Situation in, may need n at least _e≈ 2 * 10 ¹⁷Cm ^-3Similarly, the free hole concentration (n of surface when accumulation _h) should be fully big, thereby the hole can be in accumulation period and the electron recombination of capturing at transistor 14.If σ _n=σ _p, then may need n at least _h≈ 2 * 10 ¹⁷Cm ^-3If (i.e. grid voltage during counter-rotating is in surface accumulation at least 2 * 10 ¹⁷Cm ^-3The accumulation at least 2 * 10 when accumulation of electronics and grid voltage ¹⁷Cm ^-3Then there is efficient electric charge pumping effect in the hole).

It should be noted that here by reference, in conjunction with semiconductor memory device patent application AllContent, it for example comprises described in it and feature, attribute, structure, configuration, material, technology and the advantage of explanation.

Summary of the invention

This paper describes and shows many inventions.In one aspect, the invention provides a kind of integrated circuit (IC)-components, it comprises: semicondctor storage array, semiconductor memory array comprises: a plurality of semiconductor dynamic random access memory cell, arranged in matrix with row and column, each semiconductor dynamic random access memory cell comprises at least one transistor, and it has: the source region that is connected to the associated source line; Be connected to the drain region of related bit line; The tagma is arranged between source region and the drain region, and wherein the tagma is that electricity is floated; And grid, spaced apart and be capacitively coupled to the tagma with the tagma; Wherein each memory cell comprises first data mode of first electric charge in the tagma of representing associated transistor and represents second data mode of second electric charge in the tagma of associated transistor; Wherein each row of semiconductor dynamic random access memory cell comprises the associated source line, it is connected to the only semiconductor dynamic random access memory cell of associated line, wherein: be connected to the first source line with the first transistorized source region of going corresponding each memory cell of dynamic random access storage unit, be connected to the second source line with the transistorized source region of corresponding each memory cell of second row of dynamic random access storage unit, and be connected to the 3rd source line with the transistorized source region of corresponding each memory cell of the third line of dynamic random access storage unit; And wherein, described first row of memory cell is all adjacent with described second and the third line of memory cell; The transistors share drain region of the neighbor memory cell of the transistorized drain region of each memory cell of described first row of dynamic random access storage unit and described second row of dynamic random access storage unit.

In one aspect, the invention provides a kind of semicondctor storage array, comprise: a plurality of semiconductor dynamic random access memory cell, arranged in matrix with row and column, each semiconductor dynamic random access memory cell comprises at least one transistor, and it has: the source region that is connected to the associated source line; Be connected to the drain region of related bit line; The tagma is arranged between source region and the drain region, and wherein the tagma is that electricity is floated; And grid, spaced apart and be capacitively coupled to the tagma with the tagma; Wherein each memory cell comprises first data mode of first electric charge in the tagma of representing associated transistor and represents second data mode of second electric charge in the tagma of associated transistor; Wherein each row of semiconductor dynamic random access memory cell comprises (1) associated source line, and it is connected to the only semiconductor dynamic random access memory cell of associated line; And (2) different gate lines, be used for each semiconductor dynamic random access memory cell of associated line; Wherein, be connected to the first source line with the first transistorized source region of going corresponding each memory cell of dynamic random access storage unit, be connected to the second source line with the transistorized source region of corresponding each memory cell of second row of dynamic random access storage unit, and be connected to the 3rd source line with the transistorized source region of corresponding each memory cell of the third line of dynamic random access storage unit; And wherein, described first row of memory cell is all adjacent with described second and the third line of memory cell; The transistors share drain region of the neighbor memory cell of the transistorized drain region of each memory cell of described first row of dynamic random access storage unit and described second row of dynamic random access storage unit.

In one aspect, the present invention is a kind of semicondctor storage array, comprises a plurality of semiconductor dynamic random access memory cell, with the arranged in matrix of row and column.Each semiconductor dynamic random access memory cell comprises transistor, and it has source region, drain region, be arranged between source region and the drain region and adjacent with it electrically floating body district and spaced apart and be capacitively coupled to the grid in tagma with the tagma.Each transistor comprises first state of representing first electric charge in the tagma and represents second state of second electric charge in the tagma.In addition, each row of semiconductor dynamic random access memory cell comprises the associated source line, and it only is connected to the semiconductor dynamic random access memory cell of associated line.

In the present invention embodiment in this respect, each memory cell of each row of semiconductor dynamic random access memory cell comprises independent bit line, and it is connected to the drain region of associated transistor.In operation, each memory cell of first row is to be applied to the transistorized grid of each memory cell of first row and the drain electrode that the control signal that will have second amplitude is applied to each memory cell of first row is programmed to first data mode by the control signal that will have first amplitude.Subsequently, the predetermined memory cell of first row is to be applied to the source electrode that control signal that the transistorized grid of predetermined memory cell, the control signal that will have the 4th amplitude be applied to the drain electrode of predetermined memory cell and will have the 5th amplitude is applied to the predetermined memory cell of this row by the control signal that will have the 3rd amplitude to be programmed to second data mode.Please note, the control signal that is applied to the transistorized grid of predetermined memory cell and will has the 6th amplitude by the control signal that will have the 3rd amplitude is applied to the drain electrode of predetermined memory cell, when predetermined memory cell was programmed to second data mode, the memory cell that do not select of first row was maintained in first data mode.

The control signal that the memory cell of first row can be applied to the transistorized grid of predetermined memory cell by the control signal that will have the 7th amplitude and will have the 8th amplitude is applied to the drain electrode of predetermined memory cell and reads.Note that when the memory cell of first row is read all memory cells of second row (not choosing row) are maintained in the illegal state.In one embodiment, be applied to the transistorized grid of memory cell of second row by the control signal that will have the 9th amplitude, all memory cells of second row are maintained at (when the memory cell of first row is read) in the illegal state.

In one embodiment, memory cell in second row of each memory cell of first row of semiconductor dynamic random access memory cell and semiconductor dynamic random access memory cell is shared the drain region, and wherein first of the memory cell row and second row are adjacent lines.In another embodiment, each grid of each memory cell of first of the semiconductor dynamic random access memory cell row is connected to first grid polar curve.In another embodiment, the grid of each memory cell of first of the semiconductor dynamic random access memory cell row is connected to first grid polar curve.

In one aspect, the present invention is a kind of semicondctor storage array, comprises a plurality of semiconductor dynamic random access memory cell, with the arranged in matrix of row and column.Equally, each semiconductor dynamic random access memory cell comprises transistor, and it has source region, drain region, be arranged between source region and the drain region and adjacent with it electrically floating body district and spaced apart and be capacitively coupled to the grid in tagma with the tagma.Each transistor comprises first state of representing first electric charge in the tagma and represents second state of second electric charge in the tagma.

In this regard, each row of semiconductor dynamic random access memory cell comprises (1) associated source line, and it only is connected to the semiconductor dynamic random access memory cell in the associated line; Reach (2) different gate lines, be used for each semiconductor dynamic random access memory cell of associated line.

In the present invention embodiment in this respect, each memory cell of each row of semiconductor dynamic random access memory cell comprises independent bit line, and it is connected to the drain region of associated transistor.In operation, each memory cell of first row is to be applied to the transistorized grid of each memory cell of first row and the control signal that will have second amplitude by the control signal that will have first amplitude to be programmed to first data mode to the drain electrode that applies first capable each memory cell.Subsequently, the predetermined memory cell of first row is to be applied to the source electrode that control signal that the transistorized grid of predetermined memory cell, the control signal that will have the 4th amplitude be applied to the drain electrode of predetermined memory cell and will have the 5th amplitude is applied to the predetermined memory cell of this row by the control signal that will have the 3rd amplitude to be programmed to second data mode.Please note, the control signal that is applied to the transistorized grid of predetermined memory cell and will has the 6th amplitude by the control signal that will have the 3rd amplitude is applied to the drain electrode of predetermined memory cell, when predetermined memory cell was programmed to second data mode, the memory cell that do not select of first row was maintained in first data mode.

The control signal that the memory cell of first row can be applied to the transistorized grid of predetermined memory cell by the control signal that will have the 7th amplitude and will have the 8th amplitude is applied to the drain electrode of predetermined memory cell and reads.Note that when the memory cell of first row is read all memory cells of second row (not choosing row) are maintained in the illegal state.In one embodiment, be applied to the transistorized grid of memory cell of second row by the control signal that will have the 9th amplitude, all memory cells of second row are maintained at (when the memory cell of first row is read) in the illegal state.

In one embodiment, memory cell in second row of each memory cell of first row of semiconductor dynamic random access memory cell and semiconductor dynamic random access memory cell is shared the drain region, and wherein first of the memory cell row and second row are adjacent lines.

Simultaneously, describe and show many inventions herein.This summary of the invention is limit scope of the present invention not.And this summary of the invention is not intended to limit the present invention, should not explain in this way yet.Although in this summary of the invention, described some embodiment of the present invention, feature, attribute and advantage, but be to be understood that, by appended instructions, diagram and claims, of the present invention many other be tangible with different and/or similar embodiment, feature, attribute and/or advantage.

Description of drawings

In follow-up detailed description process with reference to the accompanying drawings.These accompanying drawings show different aspect of the present invention, and in suitable part, illustrate that in different figure the label of analog structure, assembly, material and/or element is similarly marked.Should be appreciated that the various combinations of structure, assembly, material and/or element outside those illustrate are especially considered by scope of the present invention and within it.

Figure 1A is the schematically showing of semiconductor DRAM array of explanation (and describe) in semiconductor memory device patent application;

Figure 1B has illustrated the memory cell according to semiconductor memory device patent application;

Fig. 2 A and 2B are according to the exemplary schematic explanation for the electric charge relation of specific memory state of the buoyancy aid of the memory cell of semiconductor memory device patent application, source electrode and drain region;

Fig. 3 A-3C be by the positive and negative gate bias of Figure 1B memory cell (read and write operation during) between the caused electric charge of pulsation relation and the exemplary schematic and the general remark of electric charge pumping phenomenon;

Fig. 4 is the exemplary voltages impulse level table that can adopt in the method for first embodiment of the invention;

Fig. 5 is the exemplary voltages impulse level table that can adopt in the method for second embodiment of the invention;

Fig. 6 is the exemplary voltages impulse level table that can adopt in the method for third embodiment of the invention;

Fig. 7 is the exemplary voltages impulse level table that can adopt in the method for the embodiment of the invention;

Fig. 8 has illustrated in the method for fourth embodiment of the invention exemplary word (grid) the line voltage waveform that uses;

Fig. 9 has illustrated in the method for fifth embodiment of the invention exemplary word (grid) the line voltage waveform that uses;

Figure 10 has illustrated exemplary word (grid) line of fourth embodiment of the invention and the sequential relationship between the bit-line voltage waveform;

Figure 11 is schematically showing according to the present invention program's semiconductor DRAM storage component part;

Figure 12 is schematically showing of the row sensing that can adopt in the semiconductor DRAM of Figure 11 storage component part and refresh circuit;

Figure 13 A, 13B, 14A and 14B have illustrated the memory array that comprises a plurality of memory cells according to a further aspect of the invention and demonstration writes and/or programming technique (comprising demonstration program voltage value), these memory cells have independent source linear array, and it limits the memory cell of particular row;

Figure 15 A and 15B illustrated the memory array that is used for Figure 13 A, 13B, 14A and 14B, according to the read operation of the embodiment of the invention, comprise exemplary read operation voltage values;

Figure 16 has illustrated the exemplary layout of the memory array of Figure 13 A, 13B, 14A and 14B;

Figure 17 and 18 has illustrated another memory array architecture according to a further aspect of the invention and has write and/or programming technique (comprising demonstration program voltage value) that these memory cells have public source electrode array;

Figure 19 illustrated the memory array that is used for Figure 17 and 18, according to the exemplary read operation voltage values of the embodiment of the invention;

Figure 20 has illustrated the exemplary layout of the memory array of Figure 17 and 18;

Figure 21 has illustrated the memory array that comprises a plurality of memory cells according to a further aspect of the invention and demonstration writes and/or programming technique (comprising demonstration program voltage value), the gate line that these memory cells have independent source linear array (it limits the memory cell of particular row) and are parallel to related bit line;

Figure 22 illustrated the memory array that is used for Figure 21, according to the exemplary read operation voltage values of the embodiment of the invention;

Figure 23 has illustrated the exemplary layout of the memory array of Figure 21 and 22;

Figure 24 and 25 has illustrated the structure of another memory array that comprises a plurality of memory cells according to a further aspect of the invention and has write and/or programming technique (comprising demonstration program voltage value) that these memory cells have public source linear array;

Figure 26 illustrated the memory array that is used for Figure 25 and 26, according to the exemplary read operation voltage values of the embodiment of the invention;

Figure 27 has illustrated the exemplary layout of the memory array of Figure 24 and 25;

Figure 28 illustrated according to a further aspect of the invention dual-port or the example configuration of multiport memory unit; And

Figure 29 has illustrated the exemplary layout of dual-port or the multiport memory unit of Figure 28.

Embodiment

Here describe and illustrated many inventions.In first aspect, the present invention is directed to a kind of from storage component part the memory cell reading of data and data are write wherein storage component part and technology.About this point, in the embodiment of the present invention aspect this, the technology that storage component part and being used to is operated this device has minimized, has reduced and/or eliminated weakening the influence of electric charge pumping phenomenon.This embodiment of the present invention adopts control signal, and it has minimized, reduced and/or eliminated the transformation of amplitude and/or polarity.

Referring to Fig. 1 and 4, in one embodiment, transistor 14 (0.25 micron N-channel MOS FETDRAM unit) can use exemplary voltage values to operate.About this point, in an example embodiment, writing logic low (binary data state " 0 ") operation can write by applying 2.9V word line (being gate bias) voltage and 2.3V bit line (being drain bias) voltage here.In this operation, source line voltage is maintained at 0V.Under these conditions, the knot between tagma 18 and the source region 20 is by forward bias, and superfluous hole moves on to the source region 20 from tagma 18.

Write logic high (binary data state " 1 ") in order to carry out in transistor 14,0.6V voltage is applied to grid 16 (being that gate bias is maintained at 0.6V), and 2.3V voltage is applied to drain electrode 22.In response, in tagma 18, provide impact ionization, the electric current between source region 20 and drain region 22, in tagma 18, generate superfluous majority carrier (hole) again.The grid voltage (sustaining voltage) that note that unselected unit is maintained at 0V.Find the strong accumulation of at the interface having avoided hole of these exemplary voltages at gate oxide 32 and floater area 18, wherein minority carrier 34 has the tendency of " being caught " or being " trapped " therein by the defective in the semiconductor.In this way, the disturbance of data that is caused by the electric charge pumping is suppressed, reduces, minimizes and/or eliminates.

In a second embodiment, referring to Fig. 1 and 5, exemplary voltage values shown in can using is come operate transistor 14 (0.25 micron N-channel MOS FET DRAM unit).About this point, in order to write logic high (binary data state " 1 "), in the strong accumulation that needs majority carrier at the interface of gate oxide 32 and floater area 18.In an example embodiment ,-1.7V voltage is applied to grid 16, and 1.7V voltage is applied to drain region 22, with the strong accumulation that majority carrier is provided at the interface at gate oxide 32 and floater area 18.The distortion that at the interface cause valency (valence) band and conduction band (conduction band) of these control signals between tagma 18 and source region 20.As a result, by tunnel effect (be called as grid induct the effect of drain leakage (GIDL)), minority carrier (being electronics here) is injected in the conduction band, and it causes the generation of majority carrier (being the hole) again here in tagma 18.This operative technique has and is in the nonconducting state of transistor 14 that the hole generates and takes place.By this way, the generation of majority carrier can be finished with relatively low power consumption.

In order to carry out read data operation, in one embodiment, in the generation inversion channel at the interface of gate oxide 32 and floater area 18.This can by apply 0V voltage to grid 16 and drain region 22 (being the 0V gate bias) with apply-0.5V voltage 20 realizes to the source region.

In the 3rd embodiment, referring to Fig. 1 and 6, the able to programme and/or operate transistor 14 (0.13 micron technology DRAM unit) of exemplary voltages shown in the use.The voltage that proposes among Fig. 6 representative " ideal " condition, wherein potential pulse applies the data that store in the interference units not.Yet these unit are arranged in the matrix, wherein: other unit are not still by access during by access when some unit, and therefore row and row decoding are essential, so that this matrix works.This causes voltage level to be different from writing, reading and keeping the level that operating period applies (in practice, all unit and the memory cell that is addressed are shared identical column or row), and as its result, disturbance may take place the data of storage those unit in.

The example is shown in Fig. 1 and 7, wherein: in the intersection of selected word line and bit line, data mode " 0 " is written to memory cell 12.Because identical grid voltage is shared in all unit in Fig. 1 same column, and identical drain voltage is shared in all unit in the row identical with Fig. 7, so the voltage inequality with " ideal " sustaining voltage is applied to those memory cells, as its result, electric charge may leak from the floater area of those unit.

When writing logic high (being data mode " 1 ") or during from memory cell 12 reading of data, occurring similarly being provided with.(by test) finds that worst case represents (being data mode " 0 ") by writing logic low, memory cell 14 a sustainable hundreds ofs word line switching cycle and above 10000 bit line switching cycles.Therefore can see, the fluctuation of grid voltage may apply restriction to the structure of circuit, specifically, if it is admissible supposing to have only 100 word line pulsation periods, then the cycle of peanut may make with these row cut apart to smaller length (for example 64) or along word line refresh all unit become essential, identical on its refreshing frequency and the existing DRAM that comprises transistor and capacitor.

Because these are provided with the number that may increase the operation desired word line driver of this circuit or sensing amplifier significantly, these two settings all are poor efficiencys very.In addition because each data cell is than conventional DRAM unit (8F2) littler (4F2), so circuit layout implement can not otherwise very expensive.

Referring to Fig. 8,11 and 12, in one embodiment, the number of word line driver and/or sensing amplifier is reduced and/or minimizes.About this point, column decoder is set up or is arranged between bit line and the sensing amplifier, to reduce and/or to minimize the number of sensing amplifier; Explicitly, read in the chunk (normally 8 or 16) only unit simultaneously.Memory cell on the row that the row that limited by internal counter (for example 8 or 16 among) are gone up and limited by station address is read, and is refreshed thereafter.Then, at the identical row and column place that is limited by station address, this unit can be used for user access (via read or write operation).

From the viewpoint of signaling, referring to Fig. 8, aspect number and rising/negative edge, the amplitude of grid voltage and the variation of polarity or swing are reduced and/or minimize.(for example seeing Fig. 9) may take place in the read or write operation that it should be noted that predetermined memory cell before refresh operation.

Referring to Figure 11 and 12, the present invention's semiconductor DRAM storage component part in this respect comprises a plurality of matrix 40a-n, and each comprises a plurality of memory cells 12 (being made up of transistor 14).Memory cell 12 is provided with the array with row and column, and it can come addressing by content address storer (CAM) 42 and row refresh counter 44.Be applied to column address Port Multiplier 46 from the column address of row refresh counter 44 outputs.Column address Port Multiplier 46 receives this refresh address and station addresss, provides one of these addresses to row Port Multiplier 48, for example to select eight or one of sixteen bit line (row) 28a.

For example the phase (promptly when not having user access) is refreshed at one's leisure in order to make memory cell 12, all interconnected gates by the signal on the row address bus 50 being applied to this row and the signal on the column address bus 52 is applied to all interconnected drains of this row are come the memory cell 12 of the infall of the given or selected row of addressing and given or selected row.Be used to the row address from user's address bus 58, via row address Port Multiplier 56, the capable refresh counter 54 by gating identifies row to be refreshed.

The column address of the row that 44 supplies of row refresh counter are to be refreshed.As mentioned above, be used to column address from user's address bus 58, via column address Port Multiplier 46, this column address of gating.As a result, the data mode at the memory cell 12 of the infall of selected row and column is determined and writes again memory cell 12.Row refresh counter 44 can increase progressively then to respond selected colleague mutually, as its result, for every row in turn to the row addressing, regardless of the addressing of going order.This just provides such advantage: the risk that minimizing memory unit 12 is not refreshed in the phase in due course.According to the phase place during the access, column address is received from row refresh counter 44 or from station address bus 58, and for example when device (or its part) was idle, row address was provided by row refresh counter 54.

The refresh technique and the circuit that it should be noted that Figure 11 can use with several arrays of parallel connection, and consequently, the number of sensing amplifier 60 can be reduced and/or minimize (this (die) goes up the desired zone of circuit also is like this).

Referring to Figure 12, when row were selected, according to the phase place in this periodic waveform, the signal on the WLDPW line 62 provided supply voltage to word line driver 62a-x.The row that 48 addressing of row Port Multiplier are to be refreshed (and memory cell of selecting thus), the data in selected memory cell are read by sensing amplifier 60, and its result exports (being the DATA data) on signal wire 66.

According to the signal logic level on line 62 (after) and the line 66 by electric pressure converter 68 conversions, the Writing condition that is applied to word line is as follows: during writing one condition, if the DATA signal is " 1 ", XNOR logic gate 68 output logic height (being binary one) on signal wire 68 then, it is written into amplifier 72 and amplifies, is applied to selected memory cell then, so as in selected memory cell the restore data state.If the DATA signal is " 0 ", then logic low (i.e. " 0 ") is applied to bit line, and it represents conservation condition.On the other hand, when writing data mode " 0 ", if the DATA signal is " 0 ", XNOR logic gate 68 output logic height (being binary one) then, it amplifies, is applied to memory cell to recover its data then by writing amplifier 72.If the DATA signal is " 1 ", then " 0 " is applied to bit line, and it represents conservation condition once more.

In certain embodiments, any problem (for example problems such as the loss of store charge or gain in the memory cell) of data mode disturbance that further reduces, minimizes and/or eliminate and just have a memory cell of public gate line, drain line and/or source line at those memory cells of access (promptly for example be read and write) during normal or refresh operation is favourable.In one embodiment, two step write operations can be used to memory cell 21 programmings, and contiguous and/or adjacent cells (promptly sharing the unit of source line, drain line and/or gate line) are had seldom until not disturbing.About this point, the full line memory cell can at first be written to same logic state, according to the desired data state everybody is write relative status (being that everybody is written to another state with reflection desired data state) thereafter.

Intention is to use many different memories unit and many different memory arrays structure of known now or later development, implements the two such steps to write technology; Memory cell that all are such and different memory arrays structure fall within the present invention.For example, this writes technology and can implement under the transistorized memory cell 12a-d of every capable 80a-f has the situation of dedicated source line, to minimize, to reduce and/or to eliminate interference to adjacent row (for example going 80b with respect to row 80c).

Referring to Figure 13 A and 13B, in one embodiment,, can write given capable 80a-f by after the selectivity write operation, applying clear operation.About this point, a plurality of memory cells 100 with the grid that is connected to the common gate polar curve are configured to form capable 80a.In Figure 13 A and 13B, pointed out exemplary voltages, be applied to the clear operation of capable 80a in fact, the remainder (80b-f at once) of array is maintained in the stationary state (promptly do not changed) in response to clear operation.In response, be expert at and store identical logic state (for example logic high or binary one) among the memory cell 12a-d of 80a.In this this mode, the state of memory cell 12a-d is " cleared ".

Thereafter, each transistor of the memory cell 12a-d of row 80a is written to specific, required and/or predetermined logic state (for example seeing Figure 14 A and 14B), so that store this specific, required and/or predetermined logic state in memory cell 12a-d.Specifically, referring to Figure 14 A, as mentioned above, by clear operation, memory cell 12a-d is placed in logic high (binary one), and memory cell 12b and 12d are written to logic low (binary zero) then.The logic state that it should be noted that memory cell 12a and 12c (is forbidden that via applying voltage is to correlative position line 28a and 28c) and is remained logic high (Figure 14 A) during write operation.Referring to Figure 14 B, memory cell 12a-d is scavenged into logic high (binary one), and memory cell 12a and 12d are written to logic low (binary zero) then.Via the writing prohibition voltage that is applied to correlative position line 28b and 28c, memory cell 12b and 12c remain logic high.

Referring to Figure 15 A and 15B, by exemplary voltages shown in applying, data can read from the memory cell 12a-d of row 80b.The demonstration sustaining voltage that is used for array remainder (memory cell that comprises capable 80b-f) also is illustrated.This sustaining voltage/signal (does not promptly change the not choosing part of array in response to read operation) in stationary state for this reason.The demonstration that it should be noted that Figure 15 A and 15B is read with sustaining voltage and can be avoided, reduce and/or minimum charge pumping disturbance.

Thus, in this embodiment, the first step of write operation is removed the memory cell with common source line, and second step writes or stores new or past data (when data do not become).The memory cell that do not select that adopts the array structure of this write operation technology can have array is not subjected to the advantage of " interference " (or the very little and/or insignificant interference of experience), because " height " voltage is applied at (promptly on the source line 26) on the line direction rather than on column direction (promptly on drain electrode or the bit line 28).Be " cleared " earlier in the beginning of the page, each byte (perhaps position) in the page or leaf is written under the situation of new state then, this writes technology and can be used as page mode and write and carry out.

It should be noted that Figure 13 A, 13B, 14A, 14B, 15A and 15B memory construction, write and/or programming technique and read technology and can combine enforcement with the embodiment of Figure 11 and 12 devices.For for purpose of brevity, will not repeat these discussion.

Figure 17-20 has illustrated another memory array architecture, wherein: a plurality of memory cells " are shared " the source line and were adopted for two steps write technology, when from/read and/or write fashionable to adjacent memory cell, it can eliminate, minimizes and/or reduce the interference to memory cell.About this point,, in one embodiment,, write given row by applying of the clear operation (Figure 17) of suitable voltage to implement to follow by selectivity write operation (Figure 18) referring to Figure 17 and 18.Combine to implement this clear operation with applying suitable voltage, the writing prohibition signal is applied to the grid (for example, the writing prohibition signal can be applied to the grid of the memory cell of capable 80b) of the memory cell of sharing source line 26.Should note, write logic low (promptly writing " 0 ") and write the intermediate value of logic high (promptly writing " 1 ") operation by word line 24b being biased in order to balance, to any interference of not selected adjacent row 80b (about row 80a) can avoid, reduce/or minimize.

Specifically, pointed out exemplary voltages among Figure 17, be applied to the clear operation of capable 80a in fact, the neighbor memory cell of array remainder (for example go 80b memory cell) is maintained in the stationary state (promptly do not changed) in response to clear operation.The memory cell 12a-d of row 80a is written to specific, required and/or predetermined logic state and (for example sees Figure 18, in memory cell 12a and memory cell 12d, write " 0 ", in memory cell 12b and memory cell 12c, write " 1 ") so that specific, the required and/or predetermined logic state of storing memory unit 12.

Referring to Figure 19, by exemplary voltages shown in applying, can be from the memory cell 12a-d reading of data of row 80a.It should be noted that the demonstration sustaining voltage that is used for array remainder (comprising the neighbor memory cell of capable 80b and the memory cell of row 80c-f) also is illustrated.Sustaining voltage/signal is partly tieed up this with the not choosing of array and (is not promptly changed in response to read or write operation) in stationary state.

The memory construction of Figure 17-20, write and/or programming technique and read technology and can combine enforcement with the embodiment of the device of Figure 11 and 12.For the sake of brevity, will not repeat these discussion.

Illustrated among Figure 21-23 and can adopt a step to write another memory array architecture of technology, its from/read and/or write fashionable elimination, minimize and/or reduce interference to adjacent memory cell to memory cell.In this structure, source line 26 is separated to be used for each row 80a-e.In addition, word line 24a-d is arranged as respectively and is parallel to correlative position line 28a-d.

Referring to Figure 21, in one embodiment,, can be written to given row (seeing the memory cell 12a-d of capable 80a) by applying suitable voltage with direct enforcement write operation.Combine to implement this write operation with applying suitable voltage, the writing prohibition signal is respectively applied to the source line 26b-e of capable 80b-e.The exemplary voltages (being used for memory cell 12a-d) and the illegal state (memory cell that is used for row 80b-e) of this write operation have been pointed out to implement among Figure 21.Memory cell 12a and the 12d of row 80a are kept and/or are written to specific, required and/or predetermined logic state (being to write " 1 ") here, and memory cell 12b is written to different required and/or predetermined logic state (being to write " 0 ") here with 12c.

Referring to Figure 22, by exemplary voltages shown in applying, can be from the memory cell 12a reading of data of row 80a.Should note also showing the demonstration that is used for array remainder (comprising other memory cells of capable 80a and the memory cell of row 80d-e) reads and forbids voltage.Read and forbid that voltage/signal partly maintains the not choosing of array in the stationary state and (promptly do not change) in response to read operation.

The memory construction of Figure 21-23, write and/or programming technique and read technology and can combine enforcement with the embodiment of the device of Figure 11 and 12.For the sake of brevity, will not repeat these discussion.

Illustrated among Figure 24-27 and can adopt for two steps write another memory array architecture of technology, its from/read and/or write fashionable technology to adjacent memory cell to eliminate, minimize and/or reduce interference to memory cell.In this structure, the source line is shared, but bit line is separated, thus each memory cell on each side of source line, and for example memory cell 12, have special-purpose bit line.The grid of transistor 12a and 12e can link together at the array boundary place.

It should be noted that memory cell 12a and 12e are positioned on the independent row, the grid of each transistor 12a and 12e for example is connected at the array boundary place.In this embodiment, for each memory cell 12a and the separative bit line of 12e (being drain line 28a and 28e), thereby can separately read each transistor 12a and 12e here.

Referring to Figure 24-27, in one embodiment,, can be written to a pair of given row by applying of the clear operation (Figure 24) of suitable voltage to implement to follow by optionally write operation (Figure 25).On the either side of common source line, row (for example, go 80a and 80b) is write and is read (Figure 26) simultaneously corresponding to this of memory cell 12a and 12e.

It should be noted that Figure 24-27 memory construction, write and/or programming technique and read technology and can combine enforcement with the embodiment of the device of Figure 11 and 12.For brevity, will not repeat these discussion.

Here describe and illustrated many inventions.Although some embodiment, feature, material, configuration, attribute and the advantage of these inventions are described and illustrate, but be to be understood that, by this description, explanation and claim, many other and differences of the present invention and/or similar embodiment, feature, material, configuration, attribute, structure and advantage according to instructions, illustrate and what is claimed is significantly.So, inventive embodiment, feature, material, configuration, attribute, structure and advantage described here and explanation are not limit, be to be understood that of the present invention these other, similar and different embodiment, feature, material, configuration, attribute, structure and advantage all within the scope of the invention.

For example, as mentioned above, demonstrate in order to implement to write with voltage level shown in the read operation.Shown in voltage level can be relative or absolute.Just, the voltage shown in for example using here, logic low can be written among the transistor 102a (for example sees Figure 13 A).Alternatively, shown in voltage can be relative because each voltage level for example can be increased or reduce given voltage (for example each voltage can increase by 0.25 volt).

In addition, although the considerable part of instructions comprises details at the N channel transistor (for example remove, write, read and forbid voltage), invention described here (and embodiment) is applicable to p channel transistor fully.In such embodiments, the majority carrier 30 in the tagma 18 is electronics, and minority carrier 34 is holes.In fact, the memory array of matrix 40a-n can comprise N raceway groove, P raceway groove and/or two types of transistors.In addition, the circuit of memory array periphery (for example unaccounted here row and column address decoder and comparer) can comprise P raceway groove and/or N channel type transistor, comprises the transistor of similar transistor 14.

It should be noted that in P channel type transistor is used as memory cell 12 situations in the memory array of matrix 40a-n, suitable removing, write, read and forbid that voltage is known according to the disclosure for those skilled in the art.Therefore for simplicity, will not repeat these discussion.

In addition, be entitled as " Semiconductor Device ", Allotment Serial Number that memory cell 12 (and memory array and matrix 40a-n) also can adopt Fazan and Okhonin to submit on February 18th, 2004 are described in 10/487,157 the non-temporary patent application (hereinafter being called " semiconductor device patent application ") and structure, feature, attribute, structure, configuration, material, technology and the advantage of explanation.The full content of this semiconductor device patent application for example comprises invention, feature, attribute, structure, configuration, material, technology and advantage wherein said and explanation, is incorporated herein by reference.

In addition, memory transistor of the present invention and/or unit and the method for operating this transistor and/or unit can be implemented with many different configurations.For example, two or more transistorized floater areas can be shared to realize the memory cell of dual-port or multiport.About this point, referring to Figure 28, dual port memory cell 12a can comprise transistor 14a and 14b.Dual port memory array can comprise a plurality of dual port memory cell 12, and it for example disposes with the row and column matrix.The data mode that is limited by the charge carrier quantity in the common electrical float zone 18 is common for two transistor 14a and 14b.

Use corresponding independent word line 24, source line 26 and bit line 28, can read and write accessing operation to transistor 14a or 14b execution independently.In illustrative example, source line 26 is that transistor 14a and the 14b of memory cell 12a is total.The source region that it should be noted that transistor 14a and 14b can be connected to independent source line.

Referring to Figure 29, in exemplary layout, dual port memory cell 12a comprises P+ buoyancy aid node 18, the P-floater area under P-floater area under the grid 24m of its " connection " transistor 14a and the grid 24n of transistor 14b.Grid 24m and 24n are connected respectively to word line 24m and 24n.Source region 20a and 20b are connected to corresponding source line.Source region 22a and 22b are connected to thread cast-off.It should be noted that as mentioned above although instructions comprises the details at the N channel transistor, these inventions (and embodiment) are applicable to p channel transistor fully.In such embodiments, the majority carrier in the tagma 18 is an electronics, and minority carrier is the hole.

Claims (16)

1. integrated circuit (IC)-components comprises:

Semicondctor storage array comprises:

A plurality of semiconductor dynamic random access memory cell, with the arranged in matrix of row and column, each semiconductor dynamic random access memory cell comprises at least one transistor, it has:

Be connected to the source region of associated source line;

Be connected to the drain region of related bit line;

The tagma is arranged between source region and the drain region, and wherein the tagma is that electricity is floated; And

Grid, spaced apart and be capacitively coupled to the tagma with the tagma;

Wherein each memory cell comprises second data mode of second electric charge in the tagma of first data mode of first electric charge in the tagma of representing associated transistor and the described associated transistor of representative;

Wherein each row of semiconductor dynamic random access memory cell comprises the associated source line, and it is connected to the only semiconductor dynamic random access memory cell of associated line, wherein:

Be connected to the first source line with the first transistorized source region of going corresponding each memory cell of dynamic random access storage unit,

Be connected to the second source line with the second transistorized source region of going corresponding each memory cell of dynamic random access storage unit, and

Be connected to the 3rd source line with the transistorized source region of corresponding each memory cell of the third line of dynamic random access storage unit; And

Wherein, described first row of memory cell is all adjacent with described second and the third line of memory cell;

The described drain region of transistors share of the neighbor memory cell of the transistorized drain region of each memory cell of described first row of dynamic random access storage unit and described second row of dynamic random access storage unit.

2. the integrated circuit (IC)-components of claim 1, wherein, the transistorized drain region of each memory cell of described first row of dynamic random access storage unit is connected to bit line, and described bit line is identical with the bit line in the transistorized drain region of the neighbor memory cell of described second and the third line of being connected to dynamic random access storage unit.

3. the integrated circuit (IC)-components of claim 2, also comprise the control module that is used to generate control signal, wherein, each memory cell of described first row is to be applied to the transistorized grid of each memory cell of first row and the drain electrode that the control signal that will have second amplitude is applied to each memory cell of first row is programmed to first data mode by the control signal that will have first amplitude.

4. the integrated circuit (IC)-components of claim 3, wherein, the predetermined memory cell of first row is to be applied to the source electrode that control signal that the transistorized grid of predetermined memory cell, the control signal that will have the 4th amplitude be applied to the drain electrode of predetermined memory cell and will have the 5th amplitude is applied to the predetermined memory cell of this row by the control signal that will have the 3rd amplitude to be programmed to second data mode.

5. the integrated circuit (IC)-components of claim 4, wherein, the control signal that is applied to the transistorized grid of predetermined memory cell and will has the 6th amplitude by the control signal that will have the 3rd amplitude is applied to the drain electrode of predetermined memory cell, when predetermined memory cell was programmed to second data mode, the memory cell that do not select of first row was maintained in first data mode.

6. the integrated circuit (IC)-components of claim 5, wherein, all memory cells of first row are to read by the drain electrode that the control signal that the control signal that will have the 7th amplitude is applied to the transistorized grid of predetermined memory cell and will has the 8th amplitude is applied to predetermined memory cell.

7. the integrated circuit (IC)-components of claim 6, wherein, when the memory cell of first row was read, all memory cells of described second row were maintained in the illegal state.

8. the integrated circuit (IC)-components of claim 6, also comprise the control module that is used to generate control signal, wherein be applied to the transistorized grid of the memory cell of described second row by the control signal that will have the 9th amplitude, when the memory cell of first row was read, all memory cells of second row were maintained in the illegal state.

9. the integrated circuit (IC)-components of claim 1, wherein, the electrically floating body transistor of each memory cell is set at semiconductor region or semiconductor layer, and described semiconductor region or semiconductor layer are positioned on the insulation layer or insulation course of substrate.

10. the integrated circuit (IC)-components of claim 1, wherein, the electrically floating body transistor of each memory cell is the N channel transistor.

11. the integrated circuit (IC)-components of claim 1, wherein, the electrically floating body transistor of each memory cell is the P channel transistor.

12. a semicondctor storage array comprises:

A plurality of semiconductor dynamic random access memory cell, with the arranged in matrix of row and column, each semiconductor dynamic random access memory cell comprises at least one transistor, it has:

Be connected to the source region of associated source line;

Be connected to the drain region of related bit line;

The tagma is arranged between source region and the drain region, and wherein the tagma is that electricity is floated; And

Grid, spaced apart and be capacitively coupled to the tagma with the tagma;

Wherein each memory cell comprises first data mode of first electric charge in the tagma of representing associated transistor and represents second data mode of second electric charge in the tagma of associated transistor;

Wherein each row of semiconductor dynamic random access memory cell comprises (1) associated source line, and it is connected to the only semiconductor dynamic random access memory cell of associated line; And (2) different gate lines, be used for each semiconductor dynamic random access memory cell of associated line; Wherein,

Be connected to the first source line with the first transistorized source region of going corresponding each memory cell of dynamic random access storage unit,

Be connected to the second source line with the second transistorized source region of going corresponding each memory cell of dynamic random access storage unit, and

Be connected to the 3rd source line with the transistorized source region of corresponding each memory cell of the third line of dynamic random access storage unit; And

Wherein, described first row of memory cell is all adjacent with described second and the third line of memory cell;

The described drain region of transistors share of the neighbor memory cell of the transistorized drain region of each memory cell of described first row of dynamic random access storage unit and described second row of dynamic random access storage unit.

13. the semicondctor storage array of claim 12, wherein, the transistorized drain region of each memory cell of described first row of dynamic random access storage unit is connected to bit line, and described bit line is identical with the bit line in the transistorized drain region of the neighbor memory cell of described second and the third line of being connected to dynamic random access storage unit.

14. the semicondctor storage array of claim 13, wherein, the electrically floating body transistor of each memory cell is set at semiconductor region or semiconductor layer, and described semiconductor region or semiconductor layer are positioned on the insulation layer or insulation course of substrate.

15. the semicondctor storage array of claim 13, wherein, the electrically floating body transistor of each memory cell is the N channel transistor.

16. the semicondctor storage array of claim 13, wherein, the electrically floating body transistor of each memory cell is the P channel transistor.

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