CN100511196C - Data processing chip and memory device - Google Patents
Data processing chip and memory device Download PDFInfo
- Publication number
- CN100511196C CN100511196C CNB2004100155225A CN200410015522A CN100511196C CN 100511196 C CN100511196 C CN 100511196C CN B2004100155225 A CNB2004100155225 A CN B2004100155225A CN 200410015522 A CN200410015522 A CN 200410015522A CN 100511196 C CN100511196 C CN 100511196C
- Authority
- CN
- China
- Prior art keywords
- controller
- data
- data processing
- processing chip
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012545 processing Methods 0.000 title claims abstract description 58
- 238000013500 data storage Methods 0.000 claims abstract description 46
- 230000005540 biological transmission Effects 0.000 claims abstract description 38
- 210000000352 storage cell Anatomy 0.000 claims description 29
- 241000258963 Diplopoda Species 0.000 claims description 3
- 230000006870 function Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 238000012937 correction Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 230000008023 solidification Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000005294 ferromagnetic effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000005291 magnetic effect Effects 0.000 description 1
- 230000005055 memory storage Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000010977 unit operation Methods 0.000 description 1
Images
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The present invention discloses a data processing chip and mobile storage device using said chip. The described data processing chip includes microprocessor, DMA controller connected with microprocessor by means of bus, register, storage medium controller, storage medium bus interface unit, protocol implementation controller and data storage unit which can create data connection with the above-mentioned every unit by means of storage medium bus interface. The described data processing chip includes data storage medium and other function component for controlling data storage. The mobile storage device using said chip can raise reliability and stability of data transmission, and raise safety of data transmission.
Description
Technical field
The present invention relates to a kind of data processing chip, particularly relate to a kind of flash memory device that has the storage chip of data processing function and use this chip.
Background technology
The continuous development of semiconductor memory technologies is for having opened up new space in data mobile storage field., capacity little because of the semiconductor storage small product size is big, zero access, advantage such as easy to carry, not fragile have obtained the application of more and more popularizing.Especially be the flash memory devices of storage medium with flash memory (Flash Memory), also claim flash disk, become the mobile storage product of personal data of new generation more.
The critical piece of existing flash memory device comprises as 3 parts such as storage chip, controller chip and interface circuit of flash memory (Flash Memory) forms formation, and wherein storage chip is used for the storage of data; Controller chip is used to control the whole devices in the whole flash memory device, by the data manipulation of interface circuit and storage chip, realizes the data access of flash memory device; Be connected, carry out exchanges data and interface circuit provides this flash memory device and external data processing host to set up data.
Yet the storage chip of existing flash memory device and controller chip are two independently chips, and its many weak point is arranged.
One, storage chip and controller chip are installed in respectively on the printed circuit board (PCB), data between storage chip and the controller chip and to be electrically connected be to realize by the circuit on the printed circuit board (PCB), stability of data transmission and reliably must be more difficult to get assurance.
They are two years old, the flash memory device that storage chip and controller chip individual packages are made, the increase of its inner member quantity, make whole flash memory device volume reduce than difficult, not consistent with the requirement that flash memory device is portable, increased the complicacy that the circuit system meter establishes and the difficulty of SMT technology simultaneously.
They are three years old; it is unsafe that separate design is preserved for the data of whole device; though; existing flash memory device can increase the data encryption measure by set cipher modes such as user authentication information in the solidification software of controller; but this kind method reads the mode of the data in the storage chip for the control chip of changing flash memory device; the secure routine that solidification software in the control chip is set obviously is helpless to the data in the protection storage medium; thereby for adopting each self-separation; the flash memory device that independent storage chip and controller chip constitute adopts cipher mode to be still for the storage of data and has unsafe hidden danger.
They are four years old, the most flash memory chip that adopts of existing flash memory device, its with control chip between adopt serial mode to carry out data to be connected, making control chip send to the control command of flash chip, address and the data IO interface from flash memory chip in batches enters, handle by flash chip inside again, thereby reduced the speed of data processing.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of storage chip that has data storage safety and have data processing function.
For this reason, the technical scheme of technical solution problem of the present invention is: a kind of data processing chip that provides, comprise microprocessor, and as the controller of entire chip, the setting of the access of major control data, transmission and parameter; Dma controller is accepted the control of microprocessor, and data are carried out transmission fast; Data storage cell is used for the storage of data; Memory medium controller is used to control the read-write sequence of exterior storage medium.
Described dma controller is connected with microprocessor by bus, and described data storage cell is connected with memory medium controller, and described memory medium controller is connected with dma controller with microprocessor respectively.
Described data processing chip also comprises the storage medium Bus Interface Unit, and described storage medium Bus Interface Unit connects data storage cell and memory medium controller.
On this basis, another technical matters of solving of the present invention is to provide a kind of and has data storage safety, makes simple flash memory device.Comprise:
At least one data processing chip, be used to control and host computer system and described flash memory device between exchanges data; And external bus interface, be used to connect described data processing chip and described host computer system
Compared with prior art, data processing chip provided by the invention has data-handling capacity and storage capacity simultaneously, can also realize parallel input to the data operational order, improved the speed of data input and output, and by the dma controller that is provided with in it, realize the DMA transmission of data, further improved the speed of data transmission.
Compared with prior art, the data processing chip that flash memory device provided by the invention adopts control chip and storage chip to integrate, reliability of data transmission and stability have been increased, and the safety of data storage, in addition, flash memory device adopts one chip, simplifies outside hardware circuit design, reduces the volume of whole flash memory device simultaneously greatly.
Description of drawings
Fig. 1 is the functional-block diagram of the data processing chip realized of the present invention;
Fig. 2 is the flash memory device functional-block diagram that utilizes data processing chip shown in Figure 1 to make;
Fig. 3 is the synoptic diagram of system's critical piece of being connected with external host system of flash memory device.
Embodiment
Below in the mode of concrete enforcement data processing chip and the flash memory device that the present invention realizes is described, reaching explanation in conjunction with the accompanying drawings can be better understood.
See also Fig. 1, it is the functional-block diagram of data processing chip 20 of the present invention, in order better to realize understanding to data processing chip 20 of the present invention, now on principle, data process chip 20 is divided module, comprise microprocessor (MCU) 21, the dma controller 22 that is connected with microprocessor by bus, registers group 23, online ECC module 24, internal storage unit 25, agreement realizes controller 31, this data processing chip also comprises memory medium controller 30, storage medium Bus Interface Unit 26 and connected data storage cell 28, described memory medium controller 30 are connected with dma controller 22 with microprocessor 21 respectively.Described microprocessor 21 receives and the execution external command as the core of data processing chip of the present invention, controls and coordinate other each unit operations.
Described agreement realizes that controller 31 can be that usb protocol realizes that controller, IEEE1394 agreement realize that controller, Bluetooth protocol realization controller, infrared ray agreement realize that controller, PCMCIA agreement realize that controller, UWB agreement realize that controller, Zigbee agreement realize controller and/or local area network wireless agreement realization controller; Described agreement realizes that controller 31 can be an individualism, also can unite two into one with microprocessor 21, or can directly realize by microprocessor 21.
In data processing chip 20 of the present invention, described microprocessor 21 is connected with a storage inside module 25, wherein storage inside module 25 comprises ROM 251 and RAM 252 these two parts, wherein the main storage of ROM 251 provide microprocessor 21 operations, control entire chip operated system program and/or application program, then as the buffer memory of application program operation, described RAM can select for use but be not limited to media such as SRAM, DRAM, SDRAM, EEPROM, MRAM, FRAM RAM252.
Described microprocessor 21 is set up data by each unit of bus 292 and other and is connected, parameter to other each unit in the data process chip 20 is configured, comprise dma controller 22, register 23, online ECC module 24 and the control that realizes other each unit of data storage unit 28 by memory medium controller 30 and storage medium bus interface 26, and realize data manipulation according to the requirement of instruction.
Described dma controller 22 connects and controlled by microprocessor 21, by accepting the data quick storage of microprocessor 21 instruction realizations to data storage unit 28, it is mainly to set up the DMA data transmission channel by the parameter of calling relevant register that dma controller 22 carries out data transmission, finishes the quick transfer function of data of different DMA transport-types.Under dma controller 22 auxiliary storage, the speed of the data storage of 21 pairs of data storage unit 28 of microprocessor has great raising.
The register of the correlation parameter that described dma controller 22 calls comprises that the default parameter value of DMA control register, RAM address register, data storage cell counter register, data storage cell address register, data storage cell command register etc. finishes dissimilar DMA data transmission.Described related register all is arranged in the registers group 23, except that aforementioned related register, registers group 23 further comprises processor control register, processor status register, processor address register, dma state register, DMA counter register, external bus interface unit controls register, external bus interface location mode register, external bus interface element count register, ECC control register, ECC status register etc.
Described DMA data transmission includes but not limited to: externally realize between data and the data storage cell 28 realizing between data transmission, external data and the RAM 252 realizing data transmission between data transmission, RAM252 and the data storage cell 28, and to the data erase of data storage unit 28, the detailed introduction of relevant DMA data transmission technology is found in the Chinese patent application 03140023.X file.
Described online ECC module 24 mainly provides carries out coding and decoding to the data of inputoutput data storage unit 28, when microprocessor 21 or dma controller 22 according to external command (host computer system or host computer are sent to) when data are write to data storage cell 28, the online ECC module 24 ECC code of will encoding, and when from data storage cell 28 reading of data, 24 of online ECC modules are with the ECC code decoding, if produce the ECC check errors, online ECC module is then carried out online correction.Online ECC module adopts Hamming code (Hamming Code) or the online encoding and decoding of RS sign indicating number, finish an error correction to data, two error detection functions, this single bit error that entangles an inspection two mode can correction data, storer is not because of single mistake interruption of work, so its Mean Time Between Failures increases, in the correctness of guaranteeing data transmission and reliability while, improved the speed of data transmission.
Described online ECC module is carried out online error correction and is mainly realized by the major parameter ECC_EN that the ECC control register is set, its default value is 1, the online measuring ability of ECC is opened, the DMA data transmission procedure is carried out online detection, when microprocessor 21 ECC_EN parameter values are set to zero, ECC circuit 24 will stop to detect.
Described memory medium controller 30 is the read-write sequences that are used for controlling exterior storage medium, can but be not limited to flash media controller, SDRAM medium controller, DRAM medium controller, EPPROM medium controller, SRAM medium controller, FRAM medium controller, MRAM medium controller, MILLIPEDE medium controller etc., described memory medium controller 30 can be an individualism, also can unite two into one, or can directly realize by microprocessor 21 with microprocessor 21.
Described data storage cell 28 is main spaces of data storage, this data storage cell 28 is connected with memory medium controller 30 by storage medium Bus Interface Unit 26, data storage cell 28 mainly comprises control code translator 282, address register 284, address decoder 286, data buffer 287 and storage medium array 288.Described control code translator 282 connects storage bus interfaces unit 26 through control line 293, receives the operational order from microprocessor 21, and compiles; Described address register 284 connects storage bus interfaces unit 26 through address wire 295, receives the address from the data manipulation of microprocessor 21, deciphers through address decoder 286 again; Data buffer 287 connects storage bus interfaces unit 26 through data line 297, receives the data from bus, to writing storage medium array 288 and keeping in from the data of storage medium array 288.
Described storage medium Bus Interface Unit 26 is the passages that connect described data storage cell and memory medium controller 30, but the interface type serial line interface of described storage medium Bus Interface Unit 26, parallel interface, USB interface, IEEE1394 interface, I
2C interface, SPI interface etc.
Described storage medium array 288 is storage spaces of data processing chip 20 reality, storage medium adopts flash media (Flash Memory) in data processing chip of the present invention, and other available storage medium includes but not limited to SDRAM, DRAM, EPPROM, static RAM (SRAM), ferromagnetic random access memory/ferroelectric memory (FRAM), magnetic random access memory (MRAM), ultrahigh density storage chip (MILLIPEDE) etc.
In data processing chip 20 of the present invention, comprise microprocessor 21 and dma controller 22, thereby the data transmission of data processing chip of the present invention has two kinds of mode of operations, microprocessor model and DMA transmission mode, its default mode is a microprocessor model, under this pattern, required data and address bus is directly controlled by microprocessor 21, realizes the data manipulation to data storage unit 28.In the DMA transmission mode, required data and address bus realizes that by being subjected to dma controller 22 controls the data of dma controller 22 and data storage cell 28 are directly transmitted.
The switching of described two kinds of mode of operations is to realize by the relevant parameters that microprocessor 21 is provided with the DMA control register, this relevant parameters mainly comprises DMA_EN, DMA_DONE, DMA_TYPE, USB_EPT, USE_DEFAULT, and it is as follows respectively that its function and being provided with is described in detail:
Parameter DMA_EN is mainly used in switching operation modes, its default value is 0, the operator scheme of data processing chip 20 acquiescences promptly of the present invention, i.e. processor mode, all of data lines and address wire by 21 pairs of these data processing chips 1 of microprocessor are controlled, and data are operated; When its parameter value is set to 1, then switch to the DMA pattern, promptly control by the data line and the address wire of 22 pairs of these data processing chips 1 of dma controller, after data are finished the DMA transmission, described dma controller 22 is set to 0 once more with this parameter value, makes data processing chip be under the processor mode.
Parameter DMA_DONE is mainly used in the look-at-me that produces microprocessor 21 input ports, and its default value is 1.Described microprocessor 21 be provided with the DMA_EN parameter be 1 o'clock with its clear 0, make described microprocessor 21 not produce the look-at-me input, after dma controller 22 was finished the DMA data transmission, it was set to 1, promptly produce look-at-me notice microprocessor 21, data have been finished the DMA transmission.
The designation data process chip 20 of being mainly used in parameter USB_EPT realizes the DMA transmission, and its parameter value is 0 o'clock, and the expression data are imported from the outside, when its parameter value is 1, represents that then data export to the outside.
The parameter value of parameter USE_DEFAULT becomes at 1 o'clock from 0, and the register relevant with data DMA transmission obtains default value, and address, size of data that DMA transmits are carried out the initialization setting.
Parameter DMA_TYPE is mainly used in definition DMA data transmission, its data transmission can be polytype, for example: externally realize realizing between data transmission, external bus interface and the RAM 252 realizing between data transmission, RAM 252 and the data storage cell 28 data transmission or the like between bus interface and the data storage cell 28, also define the operation of some non-DMA data transmission that storage medium 288 is carried out simultaneously, for example: wipe, programme or other order.
In data processing chip 20 of the present invention, microprocessor 21 and dma controller 22 are sent to the instruction of data storage cell 28, comprise that control command, address and data directly enter in the data storage cell 28 each unit by control line 293, address wire 295 and data line 297 respectively and handle, realize parallel transmission between data storage cell 28 and microprocessor 21 and the dma controller 22, improve data effectively in microprocessor 21 (or dma controller 22) and data storage cell 28 transmitting speed.
In addition, described data processing chip realizes that by agreement controller 31 is connected external host system with external bus interface, provide external data to input to data processing chip 20 and port from data processing chip 20 output datas to the outside, the quantity of this part pin can use the character of interface to encapsulate according to predetermined data processing chip 20, to reduce the number of pin of data processing chip 20, agreement realizes controller 31 support usb protocol and/or IEEE1394 agreements as described, and the pin of then described data processing chip 20 should comprise the pin of supporting usb protocol and/or IEEE1394 agreement at least.
The mode of an optimization of data processing chip 20 of the present invention can be opened up the RAM252 in the corresponding storage space replacement internal storage unit 25 in data storage cell 28, in order to storage provide microprocessor 21 operation, control entire chip operated system program and/or application program, to reduce the quantity of data processing chip 20 internal elements.
See also Fig. 2, it is the primary clustering schematic block diagram that utilizes the flash memory device 200 that data processing chip 20 of the present invention makes, flash memory device 200 comprises external bus interface unit 40 and data processing chip 20, this external bus interface unit 40 is used for flash memory device 200 and sets up data with external host system and be connected, the port of the data input and output of described flash memory device 200 is provided, data processing chip 20 is used to realize the data of input flash memory device 200 are handled, and storage, and the instruction that receives external host system, provide data to external host system.
This flash memory device 200 solidifies the solidification software of realizing the interface standard functions and carrying out the data read-write capability by the RAM 252 at data processing chip 20, adopts as USB interface and/or the IEEE1394 interface is set up and the exchanges data of external host system with the external bus interface unit 40 of realizing this flash memory device 200.The required working power of described flash memory device 200 can be drawn from external host system by external bus interface unit 40, and flash memory device 200 also can adopt self-powered mode to power certainly.
The interface mode that the external bus interface unit 40 of flash memory device 200 is adopted is not limited to USB interface or IEEE1394 interface, the corresponding reservation done in the encapsulation of data processing chip 20, the external bus interface unit 40 of flash memory device 200 can use other interface, promptly can be selected from CF, SM, MMC, SD, MS, MD, X-D, pcmcia interface, can also comprise serial ATA, IDE/SCSI and HiperLAN, bluetooth, IrDA is infrared, HomeRF, IEEE802.11x, IEEE802.11a, 802.11b, 802.11d, 802.11.g, 802.15,802.16,802.3, RS232, RS485, USB_OTG, UWB, GPIO, the UART interface can also comprise GSM, GPRS, CDMA, 2.75G, in 3G interface and the parallel interface one or more; What adopt as external bus interface unit 40 is wave point, and then described mobile flash memory device 200 must adopt self-powered, described self-powered can be primary element, rechargeable battery or the like.
See also Fig. 3, be the principle that is connected with external host system 100 of flash memory device 200 of the present invention and the schematic block diagram of system's critical piece, host computer system 100 comprises console controller 110 in it, this host computer system 100 is carried out data manipulation by 110 pairs of flash memory devices that are connected with host computer system 100 200 of console controller, makes this flash memory device 200 become the external data storage device or the external data storage space of this host computer system 100.
Described host computer system 100 can be that handheld PC, PC, notebook computer, server, special machine or other possess the host computer system of host function.The flash memory device 200 that the present invention realizes also can be connected with other external unit, realizes the storage of data, described external unit can but to be not limited to be card reader, communication apparatus, digital camera, computer peripheral equipment or other specialized equipments.
The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (6)
1, a kind of data processing chip comprises:
Microprocessor (21), as the controller of entire chip, the setting of the access of major control data, transmission and parameter;
Dma controller (22) is accepted the control of microprocessor, and data are carried out transmission fast;
Data storage cell (28) is used for the storage of data;
Memory medium controller (30) is used to control the read-write sequence of exterior storage medium;
Described dma controller (22) is connected with microprocessor (21) by bus, described data storage cell (28) is connected with memory medium controller (30), and described memory medium controller (30) is connected with dma controller (22) with microprocessor (21) respectively.
2, data processing chip according to claim 1 is characterized in that, also comprises storage medium Bus Interface Unit (26), and described storage medium Bus Interface Unit (26) connects data storage cell (28) and memory medium controller (30).
3, data processing chip according to claim 1 is characterized in that, the storage media types of described data storage cell (28) includes but not limited to flash media, SDRAM, SDRAM, EPPROM, SRAM, FRAM, MRAM and/or MILLIPEDE.
4, data processing chip according to claim 1 is characterized in that, can work in processor mode and/or DMA pattern.
5, data processing chip according to claim 1, it is characterized in that, comprise that also agreement realizes controller (31), described agreement realizes that controller (31) can be that usb protocol realizes that controller, IEEE1394 agreement realize that controller, Bluetooth protocol realization controller, infrared ray agreement realize that controller, PCMCIA agreement realize that controller, UWB agreement realize that controller, Zigbee agreement realize controller and/or local area network wireless agreement realization controller.
6, a kind of application flash memory device of data processing chip according to claim 1 is characterized in that, at least one data processing chip (20), be used to control and host computer system and described flash memory device between exchanges data; With
External bus interface (40) is used to connect described data processing chip and described host computer system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100155225A CN100511196C (en) | 2004-02-29 | 2004-02-29 | Data processing chip and memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100155225A CN100511196C (en) | 2004-02-29 | 2004-02-29 | Data processing chip and memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1661582A CN1661582A (en) | 2005-08-31 |
| CN100511196C true CN100511196C (en) | 2009-07-08 |
Family
ID=35010908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100155225A Expired - Lifetime CN100511196C (en) | 2004-02-29 | 2004-02-29 | Data processing chip and memory device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100511196C (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101135867B (en) * | 2006-08-31 | 2010-10-06 | 珠海天威技术开发有限公司 | Data record method of intelligent chip |
| WO2009156977A1 (en) * | 2008-06-26 | 2009-12-30 | Sandisk Il Ltd. | Data storage device with multiple protocols for preloading data |
| CN102508802A (en) * | 2011-11-16 | 2012-06-20 | 刘大可 | Data writing method based on parallel random storages, data reading method based on same, data writing device based on same, data reading device based on same and system |
| CN102880429B (en) * | 2012-09-14 | 2015-12-02 | 北京万协通信息技术有限公司 | A kind of SD card and data access method |
| CN103227744A (en) * | 2013-04-27 | 2013-07-31 | 苏州超锐微电子有限公司 | Bridging chip for wireless module and wired network |
| CN103879152B (en) * | 2014-03-07 | 2015-10-14 | 珠海艾派克微电子有限公司 | For storing the box chip of imaging cartridge information, imaging cartridge and communication means |
| CN105224241A (en) * | 2014-06-23 | 2016-01-06 | 联想(北京)有限公司 | Mram memory, data-storage system and method for reading data |
| CN109240979A (en) * | 2018-08-13 | 2019-01-18 | 深圳市奥拓电子股份有限公司 | Data processing chip and LED display system |
-
2004
- 2004-02-29 CN CNB2004100155225A patent/CN100511196C/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| CN1661582A (en) | 2005-08-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP2006139556A (en) | Memory card and card controller for same | |
| TWI418991B (en) | Usb-attached-scsi flash-memory system with additional command, status, and control pipes to a smart-storage switch | |
| CN103838687A (en) | Storage device, computing system including same and data transferring method thereof | |
| TWI472927B (en) | Method for dispatching and transmitting data stream, memory controller and memory storage apparatus | |
| US20080065794A1 (en) | Chained DMA for Low-Power Extended USB Flash Device Without Polling | |
| US8812756B2 (en) | Method of dispatching and transmitting data streams, memory controller and storage apparatus | |
| CN100511196C (en) | Data processing chip and memory device | |
| EP1403814B1 (en) | Electronic apparatus, information processing apparatus, adapter apparatus, and information exchange system | |
| CN1312551C (en) | Portable secret computer | |
| CN105573947B (en) | A kind of SD/MMC card control methods based on APB buses | |
| TWI430104B (en) | Method for dispatching and transmitting data stream, memory controller and memory storage apparatus | |
| CN102945216B (en) | wireless data storage device and method | |
| CN101533372B (en) | Data accessing system | |
| CN103365815A (en) | SD card interface supporting IP implementation under SD mode | |
| CN102375698B (en) | Method for assigning and transmitting data strings, memory controller and memory storage device | |
| CN101916385B (en) | Memory card type bar code decoding device | |
| CN201859459U (en) | Bar code decoding device | |
| CN101882208B (en) | Bar code decoding chip and bar code decoding device based on virtual interface | |
| CN204028949U (en) | The general card reader/writer of a kind of combined type based on HID | |
| CN215495020U (en) | Private storage device with safety encryption chip | |
| CN201725348U (en) | Bar code decoding device based on USB interfaces | |
| CN101908132B (en) | Bar code decoding method and device | |
| CN1691195B (en) | Mobile memory device and method for improving data access speed | |
| CN108231131A (en) | A kind of eMMC test methods and device | |
| CN104598410A (en) | Computer board card for writing-free driver and development method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 518057 Guangdong city of Shenzhen province Nanshan District south road six, building 16, 18 Netac 19 Patentee after: NETAC TECHNOLOGY Co.,Ltd. Address before: 518057 Guangdong city of Shenzhen province Nanshan District Gao Xin Road Chinese Development Institute of science and technology incubator building, six floor Patentee before: Netac Technology Co.,Ltd. |
|
| CX01 | Expiry of patent term | ||
| CX01 | Expiry of patent term |
Granted publication date: 20090708 |