CN100508405C - Parallel decoding method and device for raising Turbo decoding speed - Google Patents
Parallel decoding method and device for raising Turbo decoding speed Download PDFInfo
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Abstract
A parallel decoding method for increasing speed of Turbo code decoder utilizes p numbers of small decoders working in parallel to realize p parallelism of decoding for increasing speed of decoder based on existed iterative decoding. The device for realizing the method consists of small decoders, external information storage, received signal storage and state controller.
Description
Technical field
The parallel decoding method and the code translator that improve the Turbo code decoding speed belong to Turbo code decoder technical field.
Background technology
Turbo code is a kind of chnnel coding near shannon limit, be based upon on the basis of convolution code, under the long situation of code length, can obtain error-correcting performance near shannon limit, and the complexity of decoding is not very high, if decoder can reach certain speed, satisfy in 3G and following 4G communication data transfer rate and the more and more higher requirement of speed, then can have application prospect widely.
Turbo code coding is Parallel Concatenated Convolutional Code in essence, establish its be encoded to (n, k), then code efficiency is k/n, it is by two sub-encoders and the encoder that interleaver is formed.The coding structure schematic diagram as shown in Figure 1.With 1/3 code check is example, and input is 1 bit, and output is 3 bits, comprises information bit X and check digit Y, Y ', and two check digit Y, Y ' are respectively without interleaver with through the output behind the interleaver coding.
One) a kind of interleaver that does not have read/write conflict.
For Turbo code parallel decoding scheme, each sub-decode block is decoding simultaneously separately, if adopt the scheme of random interleaving, so in the same moment, may read or write operation the diverse location of the sub-piece of same decoding, and for a storage organization RAM, the identical moment can only be carried out reading or writing of a position, has so just produced read/write conflict.Therefore, parallel decoding be realized, a kind of interleaver that does not have such read/write conflict will be designed.
According to the pertinent literature investigation, design philosophy is as follows:
Getting block length is W, and N is a code length, and then P=N/W is a degree of parallelism.According to the different situations of P and W adopt different interleaving schemes (require P＜=W), be described below:
I.P is an integer, and P and W prime number each other, then N is write as the matrix of P*W (the capable W row of P), then according to the sequential read of row, and every behavior W element, or P is capable.The table that interweaves like this is not conflict, and the element of same row carries out read-write operation simultaneously, but belongs to different RAM, has so just avoided conflict.As N=28, W=7, P=4, the table that interweaves is shown in Table 1.
Ii. when P be integer, but P and W establish the greatest common divisor that K is described P and W not each other during prime number, then N is write as the matrix of the capable W of P row, this matrix is divided into the K piece in the mode of the order of row, when the 0th of conversion, according to the sequential read of row, this piece is read as the matrix that each row has W element; When conversion I piece, the last I of this a piece element is mentioned this piece head in turn, according to the sequential read of row, this piece is read as each row matrix of W element then, I=1 wherein ..., K-1 obtains the table that interweaves thus; Obtain the table that interweaves thus; As N=64, W=8, P=8, the table that interweaves is shown in Table 2.Iii. when P is not integer, the decoding data afterbody is added 0, make new code length N satisfy P=N/W and become integer,, obtain the table that interweaves, after decoding, give up 0 of afterbody interpolation again according to top method when P is integer.
Table 1 N=28, the W=7 table that interweaves
| 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
| 8 | 9 | 10 | 11 | 12 | 13 | 14 | 15 |
| 16 | 17 | 18 | 19 | 20 | 21 | 22 | 23 |
| 24 | 25 | 26 | 27 | 28 | 29 | 30 | 31 |
| 32 | 33 | 34 | 35 | 36 | 37 | 38 | 39 |
| 40 | 41 | 42 | 43 | 44 | 45 | 46 | 47 |
| 48 | 49 | 50 | 51 | 52 | 53 | 54 | 55 |
| 56 | 57 | 58 | 59 | 60 | 61 | 62 | 63 |
Before interweaving
| 0 | 8 | 16 | 24 | 32 | 40 | 48 | 56 |
| 57 | 1 | 9 | 17 | 25 | 33 | 41 | 49 |
| 50 | 58 | 2 | 10 | 18 | 26 | 34 | 42 |
| 43 | 51 | 59 | 3 | 11 | 19 | 27 | 35 |
| 36 | 44 | 52 | 60 | 4 | 12 | 20 | 28 |
| 29 | 37 | 45 | 53 | 61 | 5 | 13 | 21 |
| 22 | 30 | 38 | 46 | 54 | 62 | 6 | 14 |
| 15 | 23 | 31 | 39 | 47 | 55 | 63 | 7 |
Table 2 N=64, the W=8 table that interweaves
Above method for designing can satisfy not conflict of parallel read-write, but randomness is obviously not enough.Relativeness between the adjacent sign indicating number is more fixing, and such as W at interval all, the randomness of the sign indicating number of adjacent and certain relation of being separated by is not enough, and decoding performance is bad.Make it to be applicable to the Turbo code decoder, also need to carry out randomization.The method of randomization has a lot, interweaves such as in going, in the ranks interweaves or go interior simultaneously and in the ranks interweave to reach such effect.Determining of final interleaving scheme is to realize that we finally adopt the mode that interweaves and interweave in the advanced every trade in the ranks by a large amount of emulation, and this also is the part that we invent.
Two) interative encode method
Turbo decoding is to adopt the method for iterative decoding to carry out, and the iteration theorem schematic diagram as shown in Figure 3.The concrete grammar principle is not described in detail at this because be mature technology.
Summary of the invention
The object of the present invention is to provide a kind of method and code translator that can improve Turbo code decoder speed.
The parallel decoding method of raising Turbo code decoder speed of the present invention is characterised in that: this method be utilize the P of concurrent working independent do not have the interleaver of read/write conflict to improve decoding speed based on the little decoder of Turbo code iterative decoding with when the parallel decoding, described interpretation method contains following steps successively:
Step 1: all memories and controller are carried out initialization;
Step 2: P the table that interweaves for a short time deposited in the little interleaver that P memory constitutes, and described P the table that interweaves for a short time obtains according to following steps:
When P is an integer, and P and W prime number each other, then N is write as the matrix of the capable W row of P, then according to the order read-write of row, every behavior W element, common P is capable, and wherein, block length is W, and N is a code length, P=N/W, described P represents degree of parallelism; Thus, obtain the table that interweaves;
When P is an integer, but P and W establish the greatest common divisor that K is described P and W not each other during prime number, then N is write as the matrix of the capable W of P row, this matrix is divided into the K piece in the mode of the order of row, when the 0th of conversion, according to the sequential read of row, this piece is read as the matrix that each row has W element; When conversion I piece, the last I of this a piece element is mentioned this piece head in turn, according to the sequential read of row, this piece is read as each row matrix of W element then, I=1 wherein ..., K-1 obtains the table that interweaves thus;
When P is not integer, the decoding data afterbody is added 0, make new code length N satisfy P=N/W and become integer, again according to top method when P is integer, obtain the table that interweaves, after decoding, give up 0 of afterbody interpolation;
Again interweaving, in the ranks interweave again in the described advanced every trade of table that interweaves, interweave in perhaps going simultaneously and in the ranks interweave, the table that interweaved greatly, each row of the above-mentioned table that interweaves greatly forms the little table that interweaves, and obtains the table that interweaves greatly that the read-write of parallel decoding does not conflict;
Step 3: a frame data to decode is sent into the RAM read-write controller;
Step 4: the iteration control device sends iteration signal to affiliated RAM read-write controller, and simultaneously, the iterations counter begins counting;
Step 5: described RAM read-write controller is under the iteration control signal controlling, read the P blocks of data from described receiving signal memory, send into P sub-decoder concurrently, from P storage interweaves the interleaver of showing, read the table that interweaves simultaneously, carry out the decoding of Turbo code segmentation stepping type;
Step 6: described each sub-decoder pushes away earlier in advance to each blocks of data of input, initial value with the state likelihood value that obtains forward recursion, in each piece, carry out the segmentation recursion then, at this moment, forward recursion and reverse recursion carry out simultaneously, carry out the calculating of likelihood ratio and external information in the time of forward recursion;
Step 7:P sub-decoder read after each iteration after received signal and the corresponding external information, and calculating is sent to the RAM read-write controller with external information and is write the external information memory through iterative decoding, reads for a described P sub-decoder to be used for next iteration;
Step 8: it sends the iteration end signal to described iterations counter iterations to iteration control completely afterwards, and a described P sub-decoder sends hard decision information.
The parallel decoding device of raising Turbo code decoder speed of the present invention is characterised in that: the RAM read-write controller, P sub-decoder, P receiving signal memory, P external information memory, P little interleaver, iteration control device and iterations counter, wherein, P=N/W, N are a frame data to decode code length, and W is a block length, P is a degree of parallelism, wherein:
The iteration control device, output iteration control signal;
The RAM read-write controller is provided with the iteration control signal input part, the received signal of data to decode and the input of external information;
P receiving signal memory, the read-write control signal of this memory links to each other with the corresponding signal output part of described RAM read-write controller with the input of write data, and the output of this memory links to each other with the respective input of described RAM read-write controller;
The iterations counter, the count pulse output of this counter links to each other with described RAM read-write controller respective input;
P external information memory, the extrinsic information data of this memory, address signal input link to each other with the corresponding output end of described RAM read-write controller;
P sub-decoder adopts programmable logic device, and the output and the address signal output of the data to decode that the P of the P of this a code translator data, address signal input and described RAM read-write controller is individual after interweaving link to each other; The hard decision signal output part of this P sub-decoder and external information output link to each other with described RAM read-write controller respective input;
P little interleaver all is made of memory, and the individual little interleaver of described P is with following step formation and store the table that interweaves:
When P is an integer, and P and W prime number each other, then N is write as the matrix of the capable W row of P, then according to the order read-write of row, every behavior W element, common P is capable, and wherein, block length is W, and N is a code length, P=N/W, described P represents degree of parallelism; Thus, obtain the table that interweaves;
When P is an integer, but P and W establish the greatest common divisor that K is described P and W not each other during prime number, then N is write as the matrix of the capable W of P row, this matrix is divided into the K piece in the mode of the order of row, when the 0th of conversion, according to the sequential read of row, this piece is read as the matrix that each row has W element; When conversion I piece, the last I of this a piece element is mentioned this piece head in turn, according to the sequential read of row, this piece is read as each row matrix of W element then, I=1 wherein ..., K-1 obtains the table that interweaves thus;
When P is not integer, the decoding data afterbody is added 0, make new code length N satisfy P=N/W and become integer, again according to top method when P is integer, obtain the table that interweaves, after decoding, give up 0 of afterbody interpolation;
Interweaving, in the ranks interweave in the described advanced every trade of table that interweaves, interweave in perhaps going simultaneously and in the ranks interweave again, each row of the above-mentioned table that interweaves greatly forms the little table that interweaves; For a short time the table that interweaves stored obtain P little interleaver.
This method can be implemented in various programmable logic devices, and concrete enforcement is to make the Turbo code decoder with the Virtex2px2vp70ff1704-5 chip of Xilinx company, and also the available dedicated integrated circuit is realized.
Description of drawings
Fig. 1 Turbo code coding structure figure.
The iterative decoding schematic diagram of Fig. 2 Turbo code.
Fig. 3 iterative decoding principle schematic.
The front and back state likelihood value of the adjacent position of using when this position code element is translated in curved arrow representative, corresponding position (or perhaps sequence number) before and after straight arrows refers to interweave.
Recursive process schematic diagram in Fig. 4 piece.
Transverse axis is represented code element, arranges in order, and each lattice is represented a section, and identical numeral number is represented operation simultaneously.
Recursion schematic diagram in Fig. 5 piece.
Fig. 6 decode procedure flow chart.
Fig. 7 code translator is realized block diagram.
Embodiment
Existing decoding algorithm is non-parallel, adopts the method for segmentation recursion, can only serial process to data to decode, and speed is slow, can't satisfy the requirement more and more higher to decoder speed.And our rule can improve decoding speed significantly, adopts the P degree of parallelism speed approximately can be improved P doubly.Certainly, the complexity of decoder increases, but does not increase P doubly, resulting relatively speed, and such cost can be born.
1. method proposed by the invention is characterised in that: it is interleaver and the parallel decoding method that a kind of utilization is applicable to parallel decoding, P the sub-piece of decoding decoding separately without interfering with each other independently simultaneously is equivalent to the interpretation method that P the parallel decoder of former nothing worked simultaneously.Its described interpretation method contains following steps successively:
1) decoding beginning, corresponding counter controller initialization.
2) a frame data to decode is divided into the P piece, as P sub-data to decode, information bit information and check digit information are stored in respectively among P the RAM.In the decode procedure of back, external information (comprise interweave and do not interweave) all will be stored in the sub-block RAM of corresponding decoding.
3) each sub-piece is deciphered according to the method for parallel iteration.Method for each sub-piece employing segmentation recursion is divided into m little section with sub-piece, and when carrying out forward recursion computing mode likelihood value and likelihood ratio to a certain section, the reverse recursion that carries out next section simultaneously calculates the reverse state likelihood value.The recursion of promptly carrying out reverse and forward direction in piece simultaneously is to improve throughput.In the process of forward recursion, calculate likelihood ratio and external information, and store among the corresponding RAM.Concrete iterative process is as follows: judge whether iterative process finishes, be to finish, the output decode results, change 5), otherwise carry out following iteration: when translating first yard, for storing external information and check digit and information bit than top grade memory, directly get final product during read and write with address signal, and for translating second sign indicating number, need by interleaver (specifically seeing 4)), thereby seek interweave before, corresponding address concerns memory is carried out correct read-write afterwards.Recursive process is as follows in the piece: for first section of each height piece, oppositely push away obtaining first section reverse recursion initial value earlier in advance, carry out reverse recursion to first section then and obtain reverse recursion state likelihood value, carry out oppositely pushing away in advance of next section simultaneously; Carry out forward recursion to one section then and calculate forward recursion state likelihood value and likelihood ratio and external information, simultaneously, carry out reverse recursion to second section and obtain reverse recursion state likelihood value, recursion according to this.That is to say that each constantly just begins except first section, all can have two reverse recursions (pushes away a formal recursion in advance) and a forward recursion process carrying out.The recursive process of this part as shown in Figure 4, what mark on the transverse axis represents for piecemeal, sequence number 1,2,3 expression execution in step identical are labeled as the operation of carrying out simultaneously.In each sub-piece, determining of the state likelihood value initial value of first section forward recursion: the forward recursion by last final stage obtains to last one likelihood value record, the state likelihood value initial value of final stage reverse recursion is obtained by last likelihood value record of the reverse recursion of first section of back one sub-piece, and its principle signal and process are as shown in Figure 5.
4) be applicable to the interleaver of parallel decoder.This interleaver must be able to guarantee in iterative process not conflict in parallel P the storage external information RAM read-write of while executable operations, must guarantee that promptly interleaver at random is to satisfy such requirement to P RAM had a data write respectively at every turn.
5) through after the iteration several times, judge that iterative decoding process finishes, parallel decode results is converted into the data of serial, output.
The main key technology method of decoder is as follows:
If a frame data length is N, the decoding degree of parallelism is P, is about to the data that a frame receives and is divided into P sub-piece, and every is carried out decoded operation simultaneously, and block size is W=N/P.Allow P and the W all be integer, if can not satisfy, can add 0 in the decoding data back, decoding does not get final product its output after finishing.Because the every decoding that can be independent of each other separately, then we can finish P decoding simultaneously in a decode cycle.
For the decoding of every blocks of data, adopt the segmentation recurrence method of former scheme, forward recursion computing mode likelihood value and reverse recursion computing mode likelihood value carry out simultaneously, calculate likelihood ratio and external information in the process of forward recursion simultaneously.
Note α is a forward recursion state likelihood value, and β is a reverse recursion state likelihood value, and decode procedure specifically describes as follows as shown in Figure 4 in the piece:
A piece is divided into several sections, adopt the method for " sliding shoe " between each section, promptly do from second section earlier and oppositely push away β in advance, obtain the comparatively accurate initial value of β of first section, be the reverse recursion β of first section then, the β that oppositely pushes away in advance that does second section simultaneously obtains initial value, then be the forward recursive α of first section, calculate likelihood ratio simultaneously, be the reverse recursion β of second section simultaneously, the β that oppositely pushes away in advance of the 3rd section obtains initial value ... so go on.Then each cycle, finish two reverse recursions, a forward recursive calculates likelihood value simultaneously.Segmentation is done and can be reduced memory space like this, and two sections parallel, and the 3rd section method that pushes away in advance then can improve throughput simultaneously.
Among Fig. 4, being code length laterally, being divided into the P piece, suppose each segment length and to push away length in advance identical, all is 32, and 1., 2., the 3. priority of express time, identical be designated the operation of carrying out simultaneously.
Below the realization of our object lesson.If a frame data length is code length is 4096, degree of parallelism P is 16, and then each sub-block length is W=4096/16=256.Require each piece to decipher independently simultaneously and independently.One blocks of data is divided into 8 sections deciphers, then each the segment data length in the piece is 256/8=32.
Because during forward recursion computing mode likelihood value, the initial value of first section α should come from last final stage, and during reverse recursion computing mode likelihood value, the initial value of the β of final stage should come from back one first section.The initial value that is to say this piece comes from other piece, therefore must push away obtaining the input of these initial values as another piece earlier in advance.Specifically pushing away scheme in advance is: when iteration begins each time, earlier final stage (length is 32) is carried out pushing away in advance of α, obtain the α value of last code element, as the initial preset value of first section α of next piece forward recursion.And first section reverse recursion of each piece is write down the initial value of the β of piece head as the β of the reverse recursion of last final stage when finishing.The recurrence relation schematic diagram of initial value as shown in Figure 5.
It is exactly Design of Interleaver and the realization that is applicable to this decoding architecture that the realization of parallel decoding also has a key technology.According to the basic skills of the Design of Interleaver of introducing in the background technology that does not have conflict, carry out randomization again: interweaving in the advanced every trade in the ranks interweaves again.
Be 64 with code length below, units chunk length is 8 the realization of interleaver to be described.
N=64, P=8, W=8, the greatest common divisor of W and P are 8, then row are write to be listed as and interweaving of reading show will carry out 8 cyclical-transformations according to the rule of introducing in the background technology.The table that interweaves that obtains on this basis is as shown in table 2.Because randomness is not enough, therefore also to do randomization, promptly remake in the row on this basis and in the ranks interweave, certainly, for the not conflict that guarantees to read and write, interweaving to guarantee to belong to column element the consistency of same row.Provide the method for a randomization below according to this code length: interweave in the advanced every trade, the interleaving mode that is adopted for each row is the same, such as
| 5 | 0 | 6 | 2 | 1 | 7 | 4 | 3 |
By after interweaving in the row, the table that interweaves becomes so:
| 40 | 0 | 48 | 16 | 8 | 56 | 32 | 24 |
| 33 | 57 | 41 | 9 | 1 | 49 | 25 | 17 |
| 26 | 50 | 34 | 2 | 58 | 42 | 18 | 10 |
| 19 | 43 | 27 | 59 | 51 | 35 | 11 | 3 |
| 12 | 36 | 20 | 52 | 44 | 28 | 4 | 60 |
| 5 | 29 | 13 | 45 | 37 | 21 | 61 | 53 |
| 62 | 22 | 6 | 38 | 30 | 14 | 54 | 46 |
| 55 | 15 | 63 | 31 | 23 | 7 | 47 | 39 |
The table that interweaves after interweaving in table 3 is capable
The table that interweaves that obtains is in the ranks interweaved again, adopt the mode of mould 4, just columns is with a kind of interlace mode divided by 4 congruences.
For example can adopt following interleaving scheme in the ranks:
Remainder is 0:3 0527146
Remainder is 1:5 1730642
Remainder is 2:1 4075263
Remainder is 3:2 7401536
Then as shown in table 4 through the table that interweaves that obtains after in the ranks interweaving
| 19 | 29 | 41 | 2 | 51 | 21 | 25 | 10 |
| 40 | 57 | 20 | 31 | 8 | 49 | 4 | 39 |
| 5 | 15 | 48 | 52 | 37 | 7 | 32 | 60 |
| 26 | 43 | 63 | 16 | 58 | 35 | 47 | 24 |
| 55 | 0 | 13 | 9 | 23 | 56 | 61 | 17 |
| 33 | 22 | 34 | 45 | 1 | 14 | 18 | 53 |
| 12 | 36 | 6 | 59 | 44 | 28 | 54 | 3 |
| 62 | 50 | 27 | 38 | 30 | 42 | 11 | 46 |
The table that interweaves after table 4 in the ranks interweaves
Certainly, for different code lengths, the pattern that in the ranks interweaves in the row can be different, determine by a large amount of emulation.More than be to be that example illustrates the Design of Interleaver process with code length 64.
In sum, decode procedure is as described below:
1) design is suitable for the interleaver of parallel decoding.
2) decoding beginning is to all status registers and relevant controller initialization.
3) frame data are divided into P sub-piece, carry out piecemeal processing, storage receiving data.
4) each piece pushes away earlier in advance, with the initial value of the state likelihood value that obtains forward direction and reverse recursion.
5) carry out the segmentation recursion in each piece, forward recursion and reverse recursion carry out simultaneously, calculate likelihood ratio and external information in the time of forward recursion.
6) iterative decoding, when iteration finished, information was declared in output firmly.
Degree of parallelism is 16 parallel decoding scheme, and under the condition of not considering work clock, the original scheme of throughput ratio has improved 16 times, and the resource that takies does not have intolerable raising, and therefore, such cost is an acceptable.
Below code translator is described:
Code translator is Turbo code decoder P sub-decoder the comprising parallel processing memory etc. of table (storage that comprise inner recursion state likelihood value memory, is applicable to parallel decoding interweave for a short time), receiving signal memory, external information memory, RAM read-write controller, iteration control device.
Sub-decoder is the device that carries out independent decoding simultaneously, upgrades the external information of each symbol according to the result of calculation of data to decode that receives and last iteration, comprises interweave for a short time memory etc. of table and state likelihood value of inner iteration control device and storage.P sub-decoder parallel processing data, a parallel processing P element in each clock cycle.
Receiving signal memory is used to store received signal, comprises 2*P RAM, is respectively applied for store bits of information and check digit.RAM is selected and deposited in to signal of every reception according to its position in frame.
The external information memory is used to store external information, comprises P RAM.For the first time external information is initial value 0 (not reading external information) during iteration, reads received signal and corresponding external information during each iteration, the external information of upgrading is write to be used for next iteration after treatment.Because the position of each external information of reading is identical with the position of received signal, so the organizational form of external information RAM and received signal RAM's is identical.
The RAM read-write controller mainly is to produce the read-write control signal of RAM and address signal etc.
The iteration control device mainly is to control iterative process.
P the table that interweaves for a short time is according to the above-mentioned principle design that interweaves, and is stored in the memory.
Claims (3)
1. improve the parallel decoding method of Turbo code decoding speed, it is characterized in that, this method be utilize the P of concurrent working independent do not have the interleaver of read/write conflict to improve decoding speed based on the little decoder of Turbo code iterative decoding with when the parallel decoding, described interpretation method contains following steps successively:
Step 1: all memories and controller are carried out initialization;
Step 2: P the table that interweaves for a short time deposited in the little interleaver that P memory constitutes, and described P the table that interweaves for a short time obtains according to following steps:
When P is an integer, and P and W prime number each other, then N is write as the matrix of the capable W row of P, then according to the order read-write of row, every behavior W element, common P is capable, and wherein, block length is W, and N is a code length, P=N/W, described P represents degree of parallelism; Thus, obtain the table that interweaves;
When P is an integer, but P and W establish the greatest common divisor that K is described P and W not each other during prime number, then N is write as the matrix of the capable W of P row, this matrix is divided into the K piece in the mode of the order of row, when the 0th of conversion, according to the sequential read of row, this piece is read as the matrix that each row has W element; When conversion I piece, the last I of this a piece element is mentioned this piece head in turn, according to the sequential read of row, this piece is read as each row matrix of W element then, I=1 wherein ..., K-1 obtains the table that interweaves thus;
When P is not integer, the decoding data afterbody is added 0, make new code length N satisfy P=N/W and become integer, again according to top method when P is integer, obtain the table that interweaves, after decoding, give up 0 of afterbody interpolation;
Again interweaving, in the ranks interweave again in the described advanced every trade of table that interweaves, interweave in perhaps going simultaneously and in the ranks interweave, the table that interweaved greatly, each row of the above-mentioned table that interweaves greatly forms the little table that interweaves, and obtains the table that interweaves greatly that the read-write of parallel decoding does not conflict;
Step 3: a frame data to decode is sent into the RAM read-write controller;
Step 4: the iteration control device sends iteration signal to affiliated RAM read-write controller, and simultaneously, the iterations counter begins counting;
Step 5: described RAM read-write controller is under the iteration control signal controlling, read the P blocks of data from described receiving signal memory, send into P sub-decoder concurrently, from P storage interweaves the interleaver of showing, read the table that interweaves simultaneously, carry out the decoding of Turbo code segmentation stepping type;
Step 6: described each sub-decoder pushes away earlier in advance to each blocks of data of input, initial value with the state likelihood value that obtains forward recursion, in each piece, carry out the segmentation recursion then, at this moment, forward recursion and reverse recursion carry out simultaneously, carry out the calculating of likelihood ratio and external information in the time of forward recursion;
Step 7:P sub-decoder read after each iteration after received signal and the corresponding external information, and calculating is sent to the RAM read-write controller with external information and is write the external information memory through iterative decoding, reads for a described P sub-decoder to be used for next iteration;
Step 8: it sends the iteration end signal to described iterations counter iterations to iteration control completely afterwards, and a described P sub-decoder sends hard decision information.
2. improve the code translator of Turbo code decoding speed, its feature mainly is: RAM read-write controller, P sub-decoder, P receiving signal memory, P external information memory, P little interleaver, iteration control device and iterations counter, wherein, P=N/W, N is a frame data to decode code length, W is a block length, and P is a degree of parallelism, wherein:
The iteration control device, output iteration control signal;
The RAM read-write controller is provided with the iteration control signal input part, the received signal of data to decode and the input of external information;
P receiving signal memory, the read-write control signal of this memory links to each other with the corresponding signal output part of described RAM read-write controller with the input of write data, and the output of this memory links to each other with the respective input of described RAM read-write controller;
The iterations counter, the count pulse output of this counter links to each other with described RAM read-write controller respective input;
P external information memory, the extrinsic information data of this memory, address signal input link to each other with the corresponding output end of described RAM read-write controller;
P sub-decoder adopts programmable logic device, and the output and the address signal output of the data to decode that the P of the P of this a code translator data, address signal input and described RAM read-write controller is individual after interweaving link to each other; The hard decision signal output part of this P sub-decoder and external information output link to each other with described RAM read-write controller respective input;
P little interleaver all is made of memory, and the individual little interleaver of described P is with following step formation and store the table that interweaves:
When P is an integer, and P and W prime number each other, then N is write as the matrix of the capable W row of P, then according to the order read-write of row, every behavior W element, common P is capable, and wherein, block length is W, and N is a code length, P=N/W, described P represents degree of parallelism; Thus, obtain the table that interweaves;
When P is an integer, but P and W establish the greatest common divisor that K is described P and W not each other during prime number, then N is write as the matrix of the capable W of P row, this matrix is divided into the K piece in the mode of the order of row, when the 0th of conversion, according to the sequential read of row, this piece is read as the matrix that each row has W element; When conversion I piece, the last I of this a piece element is mentioned this piece head in turn, according to the sequential read of row, this piece is read as each row matrix of W element then, I=1 wherein ..., K-1 obtains the table that interweaves thus;
When P is not integer, the decoding data afterbody is added 0, make new code length N satisfy P=N/W and become integer, again according to top method when P is integer, obtain the table that interweaves, after decoding, give up 0 of afterbody interpolation;
Interweaving, in the ranks interweave in the described advanced every trade of table that interweaves, interweave in perhaps going simultaneously and in the ranks interweave again, each row of the above-mentioned table that interweaves greatly forms the little table that interweaves; For a short time the table that interweaves stored obtain P little interleaver.
3. the code translator of raising Turbo code decoding speed according to claim 2 is characterized in that described Turbo code code translator has adopted the Virtex2p x2vp70ff1704-5 chip of xilinx company.
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| US8140932B2 (en) * | 2007-11-26 | 2012-03-20 | Motorola Mobility, Inc. | Data interleaving circuit and method for vectorized turbo decoder |
| CN101388674B (en) * | 2008-10-23 | 2011-06-15 | 华为技术有限公司 | Decoding method, decoder and Turbo code decoder |
| CN101777924B (en) * | 2010-01-11 | 2014-02-19 | 新邮通信设备有限公司 | Method and device for decoding Turbo codes |
| CN101777926B (en) * | 2010-01-12 | 2014-04-16 | 浙江大学 | General decoder of Turbo product code and method thereof |
| CN102324999B (en) * | 2011-05-16 | 2015-12-16 | 中兴通讯股份有限公司 | A kind of parallel calculating method of interleaving address and system |
| CN102957493B (en) * | 2011-08-18 | 2016-06-08 | 上海华为技术有限公司 | The processing method of interior interleaving address, recurrence Sequences processing method and relevant apparatus thereof |
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