CN100499132C

CN100499132C - High density semiconductor memory cell and memory array

Info

Publication number: CN100499132C
Application number: CNB2005100527171A
Authority: CN
Inventors: J·Z·彭
Original assignee: Kilopass Technology Inc
Current assignee: Synopsys Inc
Priority date: 2004-03-10
Filing date: 2005-03-10
Publication date: 2009-06-10
Anticipated expiration: 2025-03-10
Also published as: CN1694257A

Abstract

A programmable memory cell comprised of a transistor located at the crosspoint of a column bitline and a row wordline is disclosed. The transistor has its gate formed from the column bitline and its source connected to the row wordline. The memory cell is programmed by applying a voltage potential between the column bitline and the row wordline to produce a programmed p+ region to form a p-n diode in the substrate underlying the gate of the transistor. Further, the wordline is formed from a buried diffusion N+ layer while the column bitline is formed from a counterdoped polysilicon layer.

Description

High density semiconductor memory cell and memory array

Relevant application

The application is that the common unsettled U.S. Patent application sequence of submitting on January 26th, 2004 is No.10/765,802, title is the part continuation application of " HIGH DENSITY SEMICONDUCTOR MEMORY CELLAND MEMORY ARRAY USING A SINGLE TRANSISTOR AND HAVING VARIABLEGATE OXIDE BREAKDOWN ", and this application is that the common unsettled U.S. Patent Application Serial Number of submitting on October 1st, 2003 is No.10/677,613, title is the part continuation application of " HIGH DENSITY SEMICONDUCTOR MEMORY CELL AND MEMORY ARRAY USINGA SINGLE TRANSISTOR HAVING A BURIED N+CONNECTION ", above-mentioned application is that the common unsettled U.S. Patent Application Serial Number of submitting on May 30th, 2003 is No.10/448,505, title is No.10/133 for the common unsettled U.S. Patent Application Serial Number of " HIGH DENSITY SEMICONDUCTORMEMORY CELL AND MEMORY ARRAY USING A SINGLE TRANSISTOR " and submission on April 26th, 2002,704, title is the part continuation application of " HIGH DENSITY SEMICONDUCTOR MEMORY CELLAND MEMORY ARRAY USING A SINGLE TRANSISTOR ", has required the priority of above-mentioned all applications according to 35 USC § 120.

Technical field

The present invention relates to a kind of Nonvolatile programmable semiconductor memory, and relate more specifically to a kind of one-transistor memory cells of programming by the breakdown transistors gate oxide and the memory array that combines this unit.

Background technology

Nonvolatile memory still can keep the data of storing when removing power supply, it wishes in many dissimilar electronic devices very much.A kind of nonvolatile memory that can obtain type usually is programmable read only memory (" PROM "), it utilizes the word-line/bit-line crosspoint element such as fuse, anti-fuse and comes stored logic information such as the transistorized trapped charge devices of floating gate avalanche injection metal oxide semiconductor (" FAMOS ").

In people's such as Reisinger the United States Patent (USP) (patent No.: disclose the example that utilizes the puncture of silicon dioxide layer in the electric capacity to store a kind of prom cell of numerical data 6,215,140).The disclosed basic PROM of people such as Reisinger uses a series of combinations of capacitive oxide and junction diode as crosspoint element (term " crosspoint " refers to the crosspoint of bit line and word line).Intact electric capacity is represented logical value 0, and electrical breakdown electric capacity is represented logical value 1.The thickness of adjusting silicon dioxide layer obtains needed performance specification.The breakdown charge of silicon dioxide is about 10C/cm ²(enclosed pasture/cm ²).If to thickness is that the capacitor dielectric of 10nm adds 10 volts voltage (field intensity of acquisition is 10mV/cm), 1mA/cm will have an appointment ²Electric current flow.Under 10 volts, this will cause the plenty of time to be used for memory cell is programmed.Yet for the high power loss that reduces to occur when the electrical breakdown, more advantageously the dielectric design with electric capacity gets thinner.For example, having capacitor dielectric thickness is that 3 to 4nm memory unit can be in about 1.5V work.Under this voltage, capacitor dielectric still can not puncture, so 1.5V is enough to from the memory cell reading of data.Data are for example being stored under the 5V, and the unit bundle (cell strand) in the memory unit can be finished programming in about 1 millisecond in the case.In this case, every cm ²The energy loss that capacitor dielectric occurs be approximately 50 watts (10 coulombs * 5V).If the energy loss that requires is about 0.5W, 1 gigabit memory of programming then needs about 100 seconds.If permissible power consumption is higher, then finishing programming correspondingly just can be faster.

The nonvolatile memory of some type can programme and wipe repeatedly.Comprise the read-only semiconductor memory of the erasable programmable that is commonly referred to EPROM and be commonly referred to the read-only semiconductor memory of electrically erasable of EBPROM.Wipe eprom memory and eprom memory is programmed with ultraviolet light with various voltages; Eeprom memory is wiped and programmed and apply various voltages.The suitable structure that all with good grounds data on it to be stored of EPROM and EBPROM are charged and discharged, said structure is commonly referred to floating boom.Electric charge on the floating boom is set up the threshold voltage of device, i.e. V _T, when reading memory, read the data of above-mentioned electric charge to determine to be stored at this.Generally, all be to be devoted to reduce gate oxide stress in the memory cell of these types as far as possible.

The device of usually said metal-nitride-oxide-silicon (" MNOS ") device has at source electrode and the raceway groove in the silicon between draining, and is covered by the grid structure that comprises silicon dioxide layer, silicon nitride layer and aluminium lamination.Can be by apply suitable potential pulse MNOS device to grid at two threshold voltage attitude V _{TH (height)}And V _{TH (low)}Between switch, this switching causes electronics at oxide-nitride thing grid (V _{TH (height)}) in be captured, perhaps from oxide-oxide gate (V _{TH (low)}) in be expelled from.And, all be to be devoted to reduce gate oxide stress in the memory cell of these types as far as possible.

At people's such as Hoffman United States Patent (USP) (U.S. Patent number: disclose on the grid that utilizes a kind of gate control diode charge stored 4,037,243) and come the junction breakdown memory cell of

stored logic

0 and 1 value.Be formed on the p type electrode of gate control diode and the electric capacity stored charge on grid between the gate electrode by utilization.By utilizing the composite dielectrics in the electric capacity that replaces silicon dioxide to form by silicon dioxide and silicon nitride layer to strengthen charge storage.The erasing voltage that applies on the electrode of gate control diode makes oxide-nitride thing interface surface be filled with negative electrical charge, and this negative electrical charge still is held after erase operation is finished.Even should negative interface charge making gate control diode also can work under the knot pattern of induction having removed behind the erasing voltage.After this when reading gate control diode, its field induced junction that demonstrates raceway groove punctures, and saturation current flows.The field induced junction puncture voltage is lower than the metallurgical junction puncture voltage.Yet, to apply for the electrode of gate control diode to write voltage silicon dioxide/silicon nitride interface is filled with positive charge, this positive charge still is held after write operation is finished.After this when reading gate control diode, make it can be not breakdown because do not have raceway groove.Have only weak current to flow.Reading different electric currents flows and represents different logic states.

Improvement tendency in the various technologies that are used for preparing various types of non-volatile memory lags behind widely used technology, for example improvement of Xian Jin CMOS logic process.For example, in order to make particular source and the drain junction of seeing usually in the needed various special areas of circuit for producing high voltage and structure, triple-well, floating grid, ONO layer and the above-mentioned device, tend to use than the advanced CMOS logic process of standard such as the device technology of quickflashing EEPROM device and Duo 30% masks.Therefore, the technology of flash device is tended to fall behind for one to two generation than the advanced CMOS logic process of standard, and the cost of every wafer expensive about 30%.Therefore as another example, the technology of anti-fuse must be suitable for making various anti-fuse structures and high-tension circuit, tends to advanced CMOS logic process backwardness to than standard equally to two generations.

Generally, the preparation of the silicon dioxide that uses in such as electric capacity and transistor at Metal-oxide-silicon (MOS) device is careful especially.Need hig diligence guaranteeing to reach during manufacture the normal work period silicon dioxide layer not affected by force of integrated circuit subsequently, thereby obtain needed device property and in time stable.Disclose an example of careful degree during preparation in the U.S. Patent No. 5,241,200 of Kuroda, it discloses and has used diffusion layer and bypass to make charges accumulated discharge in the word line during waper fabrication process.Avoid the accumulation of this electric charge to guarantee can not add big electric field, thereby the transistor characteristic when preventing to use word line as its grating routing change and the degeneration and the puncture of gate insulating film to gate insulating film.

The example of the careful degree of being taked in circuit design for fear of being subjected to stress influence at the transistorized silicon dioxide layer of normal circuit duration of work is disclosed in people's such as Tamura U.S. Patent No. 6,249,472.People such as Tamura disclose has the anti-fuse circuit that anti-fuse is connected and connected with the n channel MOS transistor in another embodiment with the p channel MOS transistor in one embodiment.Do not need to prepare the common needed supplement film manufacturing process of anti-fuse circuit though prepare anti-fuse, people such as Tamura have shown other problem.When anti-fuse short circuit, the transistor of series connection just is exposed under the high pressure of the silicon dioxide layer that is enough to breakdown transistors.People such as Tamura disclose and have added another transistor to circuit and be exposed under the disruptive potential to avoid the first transistor.

Also there is shortcoming in the memory technology that above data demonstrates each prior art usually.

Description of drawings

Fig. 1 is the circuit diagram according to a part of memory array of the present invention.

Fig. 2 is the section layout figure of a part of memory array of representing of Fig. 1.

Fig. 3 is the profile corresponding to the integrated circuit structure of the partial memory array of Fig. 2.

Fig. 4 is the voltmeter of the memory cell work of presentation graphs 1-3.

Fig. 5 is the profile of the memory cell that has been programmed.

Fig. 6 is the schematic circuit diagram of the memory cell that has been programmed.

Fig. 7 is the profile of an experimental provision.

Fig. 8 is the figure of expression constant voltage stress to the ultra-thin gate oxide effect.

Fig. 9 is the figure in the I-E characteristic of expression ultra-thin gate oxide each stage of carrying out along with degeneration.

To be expression go up the breakdown time that planted in 63% minute of measuring, represent with semi-logarithmic scale and the graph of a relation of grid voltage for the n slot field-effect transistor (transoid) of various oxide thickness to Figure 10.

Figure 11 is the figure that is illustrated in the I-E characteristic that detects the n type device of measuring after the Continuous Breakdown incident.

Figure 12 is the section layout figure according to the partial memory array of optional embodiment of the present invention formation.

Figure 13 is corresponding to the partial memory array of Figure 12 profile along the integrated circuit structure of line A-A ' intercepting.

Figure 14 is corresponding to the partial memory array of Figure 12 profile along the integrated circuit structure of line B-B ' intercepting.

Figure 15 is the voltmeter of the memory cell work of presentation graphs 12-14.

Figure 16 is the profile of an embodiment of memory cell formed according to the present invention.

Figure 17 is the schematic circuit diagram of the memory cell of Figure 16.

Figure 18 is the voltmeter of the memory cell work of expression Figure 16.

Figure 19 is illustrated in the method for the memory cell that forms Figure 16, and nitrogen injects the top view layout of scope.

Figure 20-23 illustrates the profile of a method of the memory cell that is used to form Figure 16.

Figure 24-25 illustrates the profile of the optional method of the memory cell that is used to form Figure 16.

Figure 26-27 illustrates the profile of the optional method that is used to form memory cell of the present invention.

Figure 28 illustrates the top view and the profile of optional embodiment of the present invention.

Figure 28 A is the optional embodiment that makes minimized Figure 28 of spacing of polysilicon bit line.

Figure 29 illustrates the worksheet of the embodiment of Figure 28.

Figure 30 illustrates top view and the profile of another optional embodiment of the present invention.

Figure 31 illustrates top view and the profile of another the optional embodiment of the present invention with N type polysilicon doping.

Figure 32 illustrates the worksheet of the embodiment of Figure 31.

Figure 33 is the schematic diagram of the memory array of Figure 28.

Embodiment

By setting up the leakage current level of memory cell until puncturing (soft breakdown or hard breakdown) for the ultra-thin dielectric stress application, use has the semiconductor memory cell that is structured in gate oxide data storage elements on every side and comes stored information.Read memory cell by sensing by the electric current that the unit draws.The ultra-thin dielectric that is fit to is the about 10-50 that uses in transistor

Thick or thinner high-quality gate oxide, it can be obtained by current available advanced CMOS logic process usually.This oxide usually by deposit, by being combined to form from the oxide growth of silicon active area or by they some.Other dielectric that is fit to comprises oxide-nitride thing-complex oxide, compound oxides etc.

In the following description, provide a large amount of details, so that the thorough to the embodiment of the invention to be provided.Yet those skilled in the relevant art will recognize, under the condition of neither one or a plurality of details, or adopt other method, assembly, material etc. also can implement the present invention.In other words, for fear of obscuring some aspect of the present invention, there are not detailed illustrate or illustrate known structure, material or operation.

" embodiment " that whole specification is mentioned or " embodiment " refer to concrete parts, structure or the characteristic described in conjunction with this embodiment and are contained among at least one embodiment of the present invention.Therefore, " in one embodiment " or the phrases such as " in one embodiment " that occurs everywhere in whole specification needn't all refer to same embodiment.And, can make up concrete parts, structure or feature in one or more embodiments in any suitable manner.

The present invention relates to by nonvolatile memory designs inventor exploitation and that the gate oxide based on other type to the assignee identical with the present invention of assigning punctures.The title of submitting to September 18 calendar year 2001 is the U.S. Patent Application Serial Number No.09/955 of " SEMICONDUCTOR MEMORY CELL AND MEMORY ARRAYUSING A BREAKDOWN PHENOMENA IN AN ULTRA-THIN DIELECTRIC ", 641, the title of submitting to December 17 calendar year 2001 is the U.S. Patent Application Serial Number No.10/024 of " SEMICONDUCTOR MEMORY CELL AND MEMORY ARRAY USING ABREAKDOWN PHENOMENA IN AN ULTRA-THIN DIELECTRIC ", 327, the title of submitting to October 17 calendar year 2001 is the U.S. Patent Application Serial Number No.09/982 of " SMARTCARD HAVING NON-VOLATILE MEMORY FORMED FROM LOGIC PROCESS ", 034 and the title submitted to October 17 calendar year 2001 be the U.S. Patent Application Serial Number No.09/982 of " REPROGRAMMABLE NON-VOLATILE OXIDE MEMORY FORMED FROMLOGIC PROCESS ", example has been shown in 314, its each all be merged in here as a reference.Yet in each above-mentioned memory cell, cell size is big relatively.The invention provides much smaller cell size, can realize higher density thus.

Fig. 1 illustrates the example of memory array formed according to the present invention 100.Memory array 100 is that 3 row multiply by the arrays of 4 row, yet is appreciated that this array can be size arbitrarily.Memory array 100 comprises 12 memory cells 102, its each comprise MOS transistor 104.For example, at the first row R ₁With the first row C ₁The memory cell 102 at crosspoint place comprise MOS transistor 104, its grid is connected to alignment C ₁(being also referred to as " bit line " or " row bit line " here), its source electrode is connected to line R ₁(being also referred to as " word line " or " row word line " here), and its drain electrode maintenance is connected to the drain electrode of contiguous memory cell 102 with floating.Alternatively, will see that owing to there is not electric current to pass through drain electrode, so using shallow trench isolation to isolate from (STI) under the situation of two memory cells, the drain electrode of adjacent devices need not to be connected as following.

To see as following, during programming step, big relatively voltage will be applied to the grid of the transistor 102 of choosing row (via bit line C _x, wherein x=1-M, and M is total columns), with the gate oxide of breakdown transistors 12.In one embodiment, the memory cell of other shown in Fig. 1 102 is also by at row bit line C _xWith row word line R _yThe same transistor 102 at crosspoint place form, wherein y=1-N, and N is total columns.

Transistor 102 is favourable as the data storage elements in the memory array 100 of Fig. 1, because can use many conventional cmos technology to make transistor, only utilizes the polysilicon depositing step one time, does not add any masks and be not required to be it.By contrast, " floating boom " type flash memory needs two polysilicon layers at least.And along with the development of technology now, transistorized size can be made very for a short time.For example, existing 0.18 micron, 0.13 micron and the technology of littler live width will increase the density of flash memory greatly.

Although only show 4 * 3 memory array 100, in fact when for example using 0.13 advanced μ m CMOS logic process to prepare, the sort memory array comprises an about gigabit magnitude or more memory cell.Along with the CMOS logic process further improves, bigger memory will be realized.In fact memory array 100 is organized into byte and page or leaf and redundant row (not shown), and it can carry out in the mode of any hope.Many suitable memory organization structures are well known in the art.

Fig. 2 shows local layout Figure 200 of a part of memory array 100, and Fig. 3 has represented the section of illustrative MOS integrated circuit 300, illustrates and memory cell 102 corresponding its primary structure aspects that formed by transistor 104 according to the layout of Fig. 2.The layout of Fig. 2 is suitable for advanced CMOS logic process.Term MOS is generally understood as and is suitable for any grid material, comprises polysilicon and other good conductor and the various dissimilar gate dielectric of doping, be not limited to silicon dioxide, and this term uses so at this.For example, dielectric can be the dielectric of any kind, and such as oxide or nitride, it behind the voltage that has applied a period of time hard breakdown or soft breakdown will take place.In one embodiment, (0.25 μ m technology is to have used about 50 dusts

0.18 μ m technology is 0.13 μ m technology is 0.09 μ m technology is

) thick heat growth gate oxidation silicon.

Preferably, memory array 100 adopts grid mode layout, wherein such as C ₁, C ₂, C ₃And C ₄Alignment with such as R ₁, R ₂, R ₃And R ₄Line and the diffusion source region and the drain region quadrature of transistor 104.In the following ways, in p trap active area 302, be formed on line R ₁With alignment C ₁The transistor 104 at crosspoint place.

Form ultra-thin gate oxide layer 304 by deposit or thermal oxidation.Deposit and doped polysilicon layer then, it is to use to comprise and is used for row bit line C ₁, C ₂, C ₃And C ₄The grid mask of figure come composition, it is also as the grid 310 of transistor 104.Alternatively, the row bit line can be the isolating construction that is connected to transistorized grid 310 by the row bit line segment.Form various source regions and drain region by common process step (injection, interval and n+ source/drain electrode are injected), formed n+ source region 306 and n+ drain region 308.Importantly, should be noted in the discussion above that be used for transistor 104 polysilicon gate 310 not should with n+ source/drain region crossover.Therefore, do not adopt the lightly doped drain structure.As described below, by not making polysilicon gate 310 and n+ source/drain region crossover or approaching, during programming, polysilicon gate will be not can be directly and n+ source/drain region short circuit.

And, be formed into the contact (being also referred to as capable word line segments) in n+ source/drain region 306, with line R _yConnect.Line R _yBy wanting etched metal deposit to form subsequently.And, deposit interlayer dielectric (not shown) on polysilicon layer.Therefore, with metal line R _yThe contact through hole that is connected to n+ source region 306 is formed in the interlayer dielectric.

Now, explain the work of memory array 100 with reference to the illustrative voltages shown in the figure 4.Will be understood that voltage is illustrative, in different application, maybe when using different technologies, may use different voltage.During programming, each memory cell in the memory array 100 is exposed to one of four kinds of possible program voltage combinations, and it is shown on the row 401,403,405 and 407 of Fig. 4.Reading voltage is shown on row 409,411,413 and 415.Suppose that selection memory unit 102 is used for programming and memory cell 102 is positioned at R ₁And C ₁Crosspoint place.The memory cell of selecting 102 is called the row that is in selection and the row (" SR/SC ") of selection are located.Shown in row 401, the word line R that is selecting ₁On voltage (be expressed as V _{Word line}Or " voltage on the word line ") be 0 volt, at bit line C ₁On voltage (be expressed as V _{Bit line}Or " voltage on the bit line ") be program voltage (Vpp), be 8 volts in this case.Therefore, the grid of transistor 104 (bit line C ₁) and source electrode (the word line R of transistor 104 ₁) voltage at two ends is 8 volts.The gate oxide 304 of transistor 104 is designed to puncture under this potential difference, and it is to this memory cell programming.During programming, voltage potential has punctured gate oxide, and causes leakage current to flow in the substrate of below through gate oxide, and major part is connected to the N+ source/drain collected on ground.And its result is, formed n+ district 501 (see figure 5)s that are programmed in the n+ source region 306 of transistor 104 and the p trap 302 between the n+ drain region 308.

The accurate amplitude that is appreciated that the voltage that applies depends on the thickness and the other factors of gate oxide.Therefore, for example, for 0.13 micrometre CMOS process, gate oxide is thinner usually, thus need be between the bit line of word line of selecting and selection lower voltage difference.In one embodiment, when using 0.13 micrometre CMOS process, bit line C ₁Has 4.5 volts voltage, unselected bit line R with unselected word line ₁Has the voltage between 0 and 1.2 volt.

At R ₁And C ₁During for the row and column selected, consider influence, for example R to the memory cell 102 at the place, crosspoint of the row that is positioned at selection and unselected row (" SR/UC ") ₁And C ₂Shown on the row 405, word line R ₁On voltage be 0 volt, unselected bit line C ₂On voltage be 0 or float.This causes the low relatively potential difference in gate oxide 304 two ends of transistor 104, and it is not enough to puncture the gate oxide of the transistor of locating in the crosspoint 104.Under these conditions, memory cell 102 is not programmed.

At R ₁And C ₁During for the row and column selected, consider influence, for example R to the memory cell 102 at the place, crosspoint of the row that are positioned at selection and unselected row (" UR/SC ") ₂And C ₁Shown on the row 403, unselected word line R ₂On voltage for floating or V _Pp, bit line C ₁On voltage be V _Pp(in this example being 8 volts).This causes the low relatively potential difference in gate oxide 304 two ends of transistor 104.Under these conditions, memory cell 102 is not programmed.

At R ₁And C ₁During for the row and column selected, consider influence, for example R to the memory cell 102 at the place, crosspoint that is positioned at unselected row and unselected row (" UR/UC ") ₂And C ₂Shown on the row 407, unselected word line R ₂On voltage for floating or V _Pp, unselected bit line C ₂On voltage be 0 volt or float.This causes the negative potential difference of grid 304 and N+ source/drain electrode two ends of transistor 104.Because the N+ source/drain electrode is positive and grid is born, so will can not pass through below grid at voltage higher in source/drain electrode, result's memory cell 102 does not under these conditions programme.And the voltage on unselected word line will be biased to intermediate voltage, such as 2V to 6V, in case stop element is programmed.Yet programming unit will cause the leakage current from the bit line selected to unselected word line.If unselected bit line is for floating, then leakage current will charge to it, and it causes, and voltage rises in the bit line.By with unselected word line R _xBe biased to V _PpTherefore, we can prevent this leakage, and can reduce by the charging interval to the bit line selected of programming unit.

Realize by puncture gate oxide 304 after, changed the physical property of unit 102 to memory cell 102 programmings.Forward Fig. 5 to, the transistor 104 of memory cell 102 has been programmed.During programming, below the grid of transistor 104, form the n+ district 501 that is programmed.Along with electric current (during programming process) passes gate oxide 304 and is deposited in (p trap 302) in the substrate, formed the n+ district 501 of this programming.

Although in Fig. 3, be difficult to see clearly, as the above mentioned, the polysilicon gate 310 of transistor 104 not should with the vertical crossover in n+ source/drain region 306 with 308.In fact, for example by using CMOS LDD wall, in the short circuit that laterally separates between grid 310 and n+ source region 306 and the n+ drain region 308 during should being enough to prevent to programme.As shown in Figure 3, this lateral separation is expressed as lateral separation D.In one embodiment, this lateral separation D is between 0.02 micron to 0.08 micron, as stipulating by the LDD dielectric spacer in the CMOS logical device.By not making polysilicon gate and n+ source/drain region crossover or approaching, during programming, polysilicon gate will be not can be directly and n+ source/drain region short circuit.What replace is to have formed the n+ district 501 of programming.And, can adopt other method to avoid short circuit between grid 310 and n+ district 306 and 308.Only give one example, after the etching of grid polycrystalline, can make by the oxidation of polycrystalline gate lateral wall and to make thicklyer near the gate oxide of n+ district 306 and 308.Should be appreciated that other method also is suitable.

Can in Fig. 6, see the memory cell that is programmed among Fig. 5 with the form of signal.The result that memory cell is programmed has formed two gate control diodes 601 and 603.

Gate control diode

601 and 603 prevents that electric current is from word line R _yFlow to bit line C _xYet, because positive gate bias can be brought out the n+ transoid, so during read operation, allow electric current from bit line C _xFlow to word line R _y, it can produce the connection in N+ source/drain region.

Read memory array 100 in the following manner.To read to select voltage V _RD(for example 1.8 volts) are added on the row bit line (" SC ") of selection, on 0 volt the capable word line of reading to select voltage to be added in selection (" SR ").Notice that these voltages are used for typical 0.18 micrometre CMOS process.Usually, lower voltage will be used for less more advanced CMOS technology.For example, for 0.13 micrometre CMOS process, it can be about 1.2 volts that reading on the row bit line of selecting selected voltage.

Suppose R ₁And C ₁Be that row and column (" SC/SR ") and the memory cell of selecting at the place, crosspoint is programmed.Shown on the row 409, via bit line C ₁1.8 volts (reading to select voltage) are added to the grid of transistor 104, via word line R ₁Be added to source electrode with 0 volt.This causes electric current from bit line C ₁, pass the gate oxide of transistor 104, and to pass ground connection be zero word line R ₁Flow out.By detecting the electric current on the bit line, can conclude whether memory cell 102 is programmed.If memory cell 102 is not programmed, then will there be electric current to flow, its expression memory cell is not programmed.

At R ₁And C ₁When being used for row and column that read operation selects, consider influence, for example R to the memory cell 102 at the place, crosspoint of the row that are positioned at selection and unselected row (" UR/SC ") ₂And C ₁Shown on the line 411,1.8 volts of bit line C that are added in selection ₁On, source electrode is via unselected word line R ₂Remain and float or V _RDDo not have voltage potential at transistorized two ends and do not have electric current to flow, its expression memory cell is not programmed.By with unselected word line R ₂Be biased to V _RD, can reduce the time of the bit line of selecting being charged by programmed unit.This is because if unselected word line is in to be floated, and then by the position of selecting its charging will be spent some times by programmed unit.

At R ₁And C ₁When being used for row and column that read operation selects, consider influence, for example R to the memory cell 102 at the place, crosspoint of the row (" SR/UC ") that is positioned at unselected row and selection ₁And C ₂Shown on the

line

413,0 volt is added in unselected bit line C ₂On, 0 volt of selected word line R ₁Be added on the source electrode.Do not have voltage potential at transistorized two ends and do not have electric current to flow, its expression memory cell is not programmed.

At R ₁And C ₁When being used for row and column that read operation selects, consider influence, for example R to the memory cell 102 at the place, crosspoint that is positioned at unselected row and unselected row (" UR/UC ") ₂And C ₂Shown on the

line

415,0 volt is added in unselected bit line C ₂On, source electrode is via unselected word line R ₂Remain and float or V _RDEven for former programmed unit, this programmed cells effect is similar to back-biased diode, thus do not have electric current from unselected word line (1.8V) to unselected bit line (0V), it represents that this memory cell is not programmed.

Therefore, as above seen during the read cycle, not having electric current to be positioned to have the memory cell at the place, crosspoint of unselected row or unselected row to draw.Notice that unselected word line can keep floating.This embodiment will tend to reduce the leakage current that passes word line, and allow to use less word line driver, save lsi space thus.

In addition, in alternate embodiments, thereby unselected word line or from the word line selected via before programmed unit or be charged to V via word line driver _PpSituation under, in order to increase n+ source/drain junction puncture voltage and to reduce junction leakage, can use the n+ ion of high-energy, low dosage to inject.Injection can be that the Standard N+electrostatic discharge (ESD) protection from conventional cmos technology injects or other existing implantation step, therefore still remains in the standard CMOS logic process.But, in other embodiments, can add special implantation step and optimize injection.

In Figure 12-14, marked optional embodiment of the present invention.Figure 15 illustrates the condition of work table of this optional embodiment.In the optional embodiment of Figure 12, row word line R ₁And R ₂Form by the metal deposit shown in the embodiment among Fig. 2.Instead, go word line R ₁And R ₂And all usually capable word line R _Y, all form by the n+ layer of burying that forms in the substrate.The n+ layer of therefore, burying has replaced above-mentioned metal word lines.Just because of this, just need not connect capable word line R _YMetal Contact to N+ source region 306.In general, this just allows storage array more highdensity integrated.

For the sake of clarity, should be noted that the capable word line R that shows formation Figure 12 ₁And R ₂Buried N+layer, and N+ source region 306 and n+ drain region 308 are not shown in the top view of Figure 12.

Figure 13 is the profile along the silicon substrate of the line A-A ' intercepting of Figure 12.Buried N+layer 1301 is formed on the below in N+ source region 306 and N+ drain region 308 just.In fact, N+ source region 306 electrically contacts with the N+ layer 1301 of burying.The n+ layer 1301 of therefore, burying has replaced the metal line R of Fig. 2 _yIn addition, n+ drain region 308 also contacts with the N+ layer 1301 of burying.

Figure 14 shows along the profile of the substrate of the line B-B ' intercepting of Figure 12.In this embodiment, shallow trench isolation is used for separating and the sequestering memory unit from (" STI ") 1401.Show and under the surface of substrate, bury n+ layer 1301, but still separated from 1401 by shallow trench isolation.

What the n+ layer 1301 that formation is buried will need to add shelters and implantation step.In one embodiment, in order to limit the thickness of diffusion layer in the deep submicron process, arsenic can replace phosphorus as dopant.Before or after thin gate oxide layer and/or polysilicon deposit formation, can use high energy ion to inject and form the n+ layer 1301 of burying.Alternatively, the n+ layer 1301 that can use the epitaxial deposition technique deposit to bury.And for compatible mutually with the CMOS logic process, lightly doped P type injects and logic NMOS threshold voltage V _tInject identical.

Compare with the embodiment shown in Fig. 2, owing to can realize less critical dimension with respect to the design of metal and contact through hole with lithography step, therefore the n+ layer 1301 of the burying size that can reduce memory array reaches 50% or more.

At last, Figure 15 shows the condition of work table of the embodiment of Figure 12-14.Gate-oxide thicknesses program voltage V for 32 dusts _PpBe approximately 8-9 volt, or be the 5-6 volt for the gate oxide program voltage of 20 dusts.Usually, V _DDBe input/output voltage and the magnitude that is about 3.3 volts or 2.5 volts.0.18 V during micron technology _CCSupply voltage be generally 1.8 volts, be 1.2 volts during 0.13 micron technology.Just as you've seen, in order to form programming and read functions, the voltage of use can have a scope.Notice that equally 405 and 407 (for the unselected row) of being expert at are located, at row bit line V _{Bit line}On voltage less than 0.5 volt.If unselected row bit line (in other words is V greater than 0.5 volt _t), will have through the gross leak electric current of programming unit along the previous programming unit of common column bit line.By with V _{Bit line}Be limited to V _tBelow, can reduce or eliminate this leakage current.

Various having studies show that of the oxide breakdown that carries out in the environment that is different from the memory cell 102 shown in the array 100 is used to puncture ultra-thin gate oxide and sets up the controlled suitable voltage level of puncture.When ultra-thin gate oxide is subjected to the stress of voltage induced, occur in the gate oxide puncturing.Really cutter system is not clear though cause the gate oxide intrinsic breakdown, and breakdown process is the progressive process by soft breakdown (" SBD ") stage to hard breakdown (" the HBD ") stage.A kind of puncture reason is considered to the defect oxide position.These defective locations can the unit work and cause puncture, or can trap-charge and cause local high electric field and electric current thus, and the positive feedback condition that causes thermal runaway.Cause that the improvement manufacturing process of less defect oxide has reduced the appearance of this type puncture.Another reason that punctures is considered to be in each position electronics and hole capture, even in the zero defect oxide, it also can cause thermal runaway.

People such as Rasras have carried out the carrier separation experiment, and it shows that under positive gate bias the ionization by collision of the electronics in the substrate is the main source of substrate hole current.Mahmoud?Rasras，Ingrid?De?Wolf，Guido?Groeseneken，Robin?Degraeve，Hermane.Maes，Substrate?Hole?Current?Origin?after?Oxide?Breakdown，IEDM00-537，2000。Relate to therein in the scheme of raceway groove transoid ultrathin oxide has been carried out the Constant Pressure Stress experiment, show that SBD and HBD may be used to store data, the time of standing stress by control gate oxide memory element just can obtain required SBD and HBD degree.Fig. 7 illustrates the constructed profile of this experimental provision of expression.The influence of Constant Pressure Stress to ultra-thin gate oxide has been shown in the chart of Fig. 8, and wherein the x axle is the time in second, and the y axle is the electric current of the ampere expression of logarithmic form.Fig. 8 is illustrated in the grid and the substrate hole current of soft breakdown and hard breakdown fore-and-aft survey under the Constant Pressure Stress.For time of 12.5 seconds roughly, total current substantial constant and being mainly as passing through I _gThe electronic current of measuring.Think to leak and result from the leakage current (" SILC ") of Fowordlineer-Nordhein (" FN ") tunnelling and stress induction.Located at about 12.5 seconds, observe jump big in the substrate hole current of measurement, it is the signal of soft breakdown (" SBD ") beginning.From about 12.5 seconds to about 19 seconds, keep constant basically in this new level place total current, in substrate current though some fluctuations are arranged.Located at about 19 seconds, electronic current and substrate hole current in the two big jump show the beginning of hard breakdown (" HBD ").Fig. 8 illustrates the time of standing stress by control gate oxide memory element, can obtain the degree of desirable SBD or HBD.

People such as Sune have studied the back SBD conduction in the ultra-thin silicon dioxide film.Jordi?Sune，Enrique?Miranda，Post?Soft?Breakdown?conduction?in?SiO2?GateOxide，IEDM?00-533，2000。Figure 9 illustrates each stage in current-voltage (" the I-V ") characteristic that ultra-thin gate oxide carries out along with degeneration, wherein the x axle is the voltage with voltmeter, and the y axle is the electric current of the logarithmic form represented with ampere.Fig. 9 illustrates the voltage that can use wide region to the programming of gate oxide memory element with can use SBD or HBD comes stored information in the gate oxide memory element.Comprise that also showing the several backs that develop from SBD to HBD punctures the I-V characteristic.Voltage amplitude in SBD and HBD place and the amount of leakage current that produces under these two intermediate case between extreme and about 2.5 volts to 6 volts scope is roughly linear.

The voltage that people such as Wu have studied ultrathin oxide depends on the relation that voltage quickens.E.Y.Wuet?al.，Voltage-Dependent?Voltage-Acceleration?of?OxideBreakdown?for?Ultra-Thin?Oxides，IEDM?00-541，2000。Figure 10 is that the breakdown time of 63% distribution place is to the chart of gate voltage under the semilog coordinate of the n channel fet (transoid) that measured oxide thickness changes from 2.3nm to 5.0nm.Distributing generally speaking is consistent and is linear, and represents that this process is controlled.

People such as Miranda have measured and have had 3nm oxide thickness and 6.4 * 10 after detecting the Continuous Breakdown incident ^-5Cm ²The I-V characteristic of the nMOSFET device of area.Miranda?et?al.，“Analytic?Modeling?of?Leakage?Current?Through?MultipleBreakdown?Paths?in?SiO ₂?Films”，IEEE?39 ^th?Annual?InternationalReliability?Physics?Symposium，Orlando，FL，2001，pp?367-379。Figure 11 represents these results corresponding to linear zone, and wherein " N " is the conducting channel number.These results are very linear, show that path is resistive basically.

In the above-described embodiment, n type lightly doped drain (NLDD) injects and is blocked usually, to avoid making grid and source/drain electrode N+ spread crossover (referring to Fig. 3 and space D).This has just generated backward diode between the diffusion of the word line N+S/D in programming unit and the bit line polysilicon gate.This causes in unselected word line (word line of floating by the situation of the bit line of selecting at the Vpp place through programming unit charging under, be biased to Vdd or higher) to the leakage current minimizing between the non-selected bit line (setover or float for 0 volt).

In the structure shown in Fig. 1-6 and the 12-15, near gate oxide breakdown point near the grid edge of word line N+ diffusion region (referring to Fig. 5).Relatively low from word line N+ diffusion region to the punch through voltage of oxide breakdown point, so backward diode does not have effect to preventing the leakage current from unselected word line to non-selected bit line.Owing to some reasons, this is undesirable.

Therefore, according to the present invention, make near the gate oxide ratio of the N+ diffusion region of floating easier to be breakdown near the gate oxide of word line N+ diffusion region.And this can realize by many methods, wherein describe two independently methods: (1) makes near the N+ diffusion region of floating gate oxide than near the gate oxide the word line N+ diffusion region thinner (below illustrate be used for the whole bag of tricks realized with two specific embodiments); Or (2) are by near float the gate oxide N+ diffusion region of implant damage, so that the easier puncture of gate oxide.Be appreciated that the present invention mainly is devoted in the N+ diffusion region of floating lower puncture voltage to be arranged, and any manufacturing with this end in view existing or exploitation in the future or structure are all within the scope of the invention.

In one embodiment, as referring to Figure 16,, can make thinlyyer the gate oxide of N+ source (diffusion) district one side of floating (possibility 1) for the grid edge of mobile gate oxide breakaway poing away from place, word line N+ diffusion region.The N+ diffusion region of floating connects two adjacent on same word line unit.Alternatively, gate oxide can be made thinlyyer (possibility 2) near the gate electrode side the word line N+ district.Notice that the present invention can be easy to expand to the PMOS device, wherein the PMOS device is formed on the inside of N trap.

Use the memory cell of this different gate oxide MOS device to have the following advantages:

1. preferably betide source region one side of floating of grid usually by the programming unit of oxide breakdown.

2. this provides firm backward diode between drain electrode of programming unit (word line contact) and polysilicon gate (bit line).

3. compare with uniform gate oxide unit, improved the backward diode punch through voltage thus greatly, wherein the gate oxide puncture can appear near drain side (causing the low punch through voltage of backward diode).

4. this program voltage will reduce (dropping to 3.5-5V), because the source side gate-oxide thicknesses is than thin many of standard gate oxide, it generally needs 6 to 6.5V to programme.

Figure 17 illustrates the equivalent circuit diagram of different oxide 1T memory cells.Figure 18 illustrates the cell operation bias voltage of an embodiment.There are several technology to can be used for forming above-mentioned different gate oxide, below describe wherein two kinds.

Possibility 1: on a side of grid, use nitrogen (N2) to inject (other injection kind that maybe can reduce silicon oxidation speed) to generate different gate-oxide thicknesses.Yet the different gate oxide of Chan Shenging is not self aligned by this method.

Shown in Figure 19 and 20, after P trap and raceway groove Vt injection, the nitrogen that uses photomask to select in the silicon area that will grow than thin gate oxide injects.

Next forward Figure 21 to, remove the back and inject photomask, carry out the gate oxidation pre-wash step, and carry out general gate oxidation on non-nitrogen injection region, to grow 20

(for the technology of 0.13 μ m class).Simultaneously, the silicon area that injects at nitrogen will grow 10 to 15

Thin gate oxide.

Forward Figure 22 to, after gate polysilicon deposit and polysilicon gate etching, then carry out NLDD injection and N+S/D and inject.At last, as shown in the figure, be formed on the source and leak NMOS memory cell with different gate oxide thickness.

At last, forward Figure 23 to, after the contact that arrives word line diffusion (word line) and polysilicon bit line (bit line) is connected, form memory cell with different gate oxide nmos device.

In optional method (possibility 2), on drain side, use isotropic etching, then carry out oxidation.The different gate oxide that produces by said method is self aligned.Particularly, as shown in figure 24, after the gate polysilicon etching, use photoresist to cover source side, and carry out isotropic etching (being generally wet etching) on drain electrode (word line) side gate oxide, to produce undercutting (undercut).

Next, as shown in figure 25, remove photoresist and carry out oxidation step, therefore on drain electrode (word line) side, make thicker gate oxide to fill the undercutting grid.Then carrying out conventional NLDD injection, sept deposit, spacer-etch and S/D injects.

More than two kinds of methods to have described with respect to transistor source be that the basis makes the thickness of gate oxide different with drain electrode with the position.Do like this is that gate oxide in order to make the more approaching N+ of floating diffusion region has lower puncture voltage.The other method that realizes same task is to inject the gate oxide that damages the more approaching N+ of floating diffusion region by for example heavy ion.

Particularly, other method is the heavy ion that injects such as As+, optionally damages gate oxide, so that the general gate oxide of its oxide breakdown voltage ratio is lower.This also is a self-registered technology.For example, as shown in figure 26, after the gate polysilicon etching, use photoresist to cover drain side.Then, to the source side of floating carry out angled (15～60 degree, 2 to or 4 inject to rotation) As+ injects.As shown in figure 27, next step is to remove photoresist and carry out conventional LDD injection, sept deposit, spacer-etch and S/D injection.

Bus the above embodiments, the N+ layer embodiment that buries of Figure 12-15 needs special (and often being complicated) injection technology.In order to eliminate and the contacting of word line, use to inject to connect below surface channel, to produce the N+ layer of burying.The variable gate oxide puncture embodiment of Figure 16-27 need add with special processing step and make variable G _Ox

Among the optional embodiment more shown in Figure 28, use surperficial N+ to spread to replace the N+ layer of burying deeply.Notice that the term diffusion of using refers to and comprises by the doped region that injects or diffusion technology forms herein.Can use standard CMOS process flow process to make this embodiment with an additional masking and implantation step.Behind the oxide breakdown, can then form the PN junction diode.

As shown in figure 28, with regard to surperficial N+ word line replaced traditional N trap, transistor AND gate PMOS transistor was similar now.Yet notice, N+ word line 2801 by shallow trench isolation from isolating.Form surface level N+ word line 2801 in the surface of substrate (by diffusion or injection).For example, can before gate oxidation, carry out As+ (or any other n type dopant) diffusion.Alternatively, if use to inject, before or after the gate oxidation or even the polysilicon gate deposit after, can inject As+, with formation N+ word line 2801.

After in substrate, forming N+ word line 2801 and finishing gate oxidation technology, on gate oxide, form polysilicon layer.Then routinely the etching polysilicon layer to form bit line 2803.Then, such as for example also forming attached (just unnecessary) P+S/D district 2805 by use autoregistration implantation step.As the part of this injection, inject the polysilicon layer that forms transistor gate and become P+ type polysilicon.This realization and standard CMOS logic process compatibility, and saved additional mask and implantation step.Yet this realization also can cause unnecessary attached P+ source/drain electrode doping.

Should be noted that N+ word line 2801 should be darker than P+S/D district 2805, to guarantee the satisfactory electrical conductivity of N+ word line 2801.Yet in order to prevent to pass the low punch through leakage of shallow trench isolation from (STI) between the adjacent bit lines, the N+ word line can not be too dark.

Reduce to minimum for the influence that makes attached P+ source/N+ connection that drain electrode doping obstruction is buried, the interval between the adjacent polysilicon lines can make as far as possible for a short time.By doping like this, lightly doped drain (LDD) wall is with closer to each other, to minimize effectively or even to eliminate P+ source/drain electrode and inject.Such example is shown among Figure 28 A.Yet as shown in figure 33, the N+ word line periodically contacts with memory array such as per 64 row.

The working condition of memory array is illustrated in the table of Figure 29.Program voltage (Vpp) is a voltage necessary between bit line and word line, so that be enough to break-through or electrical breakdown gate oxide.Because program voltage is poor between voltage (Vwp) on the word line and the voltage (Vbp) on the bit line, so the various combinations of voltage can be distributed between bit line and the word line.

In one embodiment, for G _Ox=32

(0.18 μ m technology), Vpp=|Vwp-Vbp|=7～10V, or for G _Ox=20

(0.13 μ m technology) is 5～7V.In one embodiment, Vwp=0～Vpp and Vwp can be set to Vdd expediently.Vbp can-Vpp～+ scope of Vpp in.Vrd reads voltage, and it is between Vcc to Vdd.For 0.18 μ m technology, Vcc=1.8V, and be 1.2V for 0.13 μ m technology.Vdd is I/O voltage (3.3V or 2.5V).

Shown in Figure 30 one optional embodiment.In this embodiment, do not form source region and drain region.Before the polysilicon etching, under the situation of the CMOS technology that has for the selection of P+ polysilicon or N+ polysilicon mix (the injection doping during such as deposit or after polysilicon deposit and the doping), realize this embodiment probably.In this case, the care about P+S/D doping obstruction N+ word line no longer is problem.This will obtain device architecture as shown in figure 30.Therefore, in this embodiment, this structure only is an intersection polysilicon bit line above the word line of burying.Roughly the same shown in operation principle and Figure 29.

Above thought can be amplified the embodiment of N+ polysilicon/gate oxide/P+ word line at an easy rate.In such an embodiment, only the type of mixing is put upside down, had the capable array that is formed in the N trap.Particularly, as shown in figure 31, at first in substrate, form N trap 3101.Then, will be incorporated into such as the p type dopant of boron in the N trap to form P+ word line 3103.Can before or after the gate oxidation or even after the polysilicon deposit, carry out the p type and mix.

After in substrate, forming P+ word line 3103 and finishing gate oxidation technology, on gate oxide, form polysilicon layer.Then, routinely the etching polysilicon layer to form bit line 3105.Then, by using the autoregistration implantation step, form N+S/D district 3107 such as for example.As the part of this injection, the polysilicon layer that forms the transistor canopy utmost point also is injected into and becomes N+ type polysilicon.

Should be noted that P+ word line 3101 should be darker than N+S/D district 3107, to guarantee the satisfactory electrical conductivity of P+ word line 3103.Yet in order to prevent to pass the low punch through leakage of shallow trench isolation from (STI) between the adjacent bit lines, the P+ word line can not be too dark.

And, in this embodiment, need not form source region and drain region.Before the polysilicon etching, under the situation of the CMOS technology of mix having (during or the injection after the polysilicon deposit mix), realize this embodiment probably such as the polysilicon deposit for the selection of N+ polysilicon.In this case, the care of relevant N+S/D doping obstruction P+ word line no longer is problem.

The memory array working condition is shown in the table of Figure 32.Program voltage Vpp can separate between bit line and word line.For

(0.18 μ m technology), Vpp=|Vbp-Vwp|=7～10V, or for

(0.13 μ m) is 5～7V.Vbp can-Vpp～+ scope of Vpp in, and Vwp can be in the scope of 0～Vpp, or is set to Vdd expediently.Vrd reads voltage, and it is between Vcc to Vdd.Vdd is the I/O voltage of 3.3V or 2.5V.For 0.18 μ m technology, Vcc=1.8V, and be 1.2V for 0.13 μ m technology.

Embodiment shown in Figure 28-32 provides favourable characteristic.For example:

(1) uses and only to have an additional buried N+or the standard CMOS process of P+ mask and injection, can construct the anti-fuse memory element array of gate oxidation that constitutes by the unit that is of a size of 4F^2 (wherein F is a minimum feature size).

(2) unit is by the structure construction of P+ polysilicon/Gox/N+ word line/P trap or N+ polysilicon/Gox/P+ word line/N trap/P substrate.Can isolate the diffusion word line of burying by standard STI or other partition method.

(3) construct bit line and word line by the polysilicon lines of contra-doping and the diffusing lines of burying.

(4) by Vpp being added in gate oxide two ends, unit, can optionally programme to cell array with two kinds of polarity.After programming Gox punctures, between the polysilicon and the diffusing lines of burying, form the P-N junction diode.

(5) by positive voltage being added to the P end of PN junction diode, can optionally read programmed unit, thereby make the diode forward biasing form current sensor.

(6) program voltage Vpp can distribute between bit line and word line, thereby can reduce the program voltage on bit line or the word line.

Notice, the transistor that uses in the memory cell described herein, most cases is for generally to have for example low logic voltage transistor of superthin grid oxide thickness, and this thickness is about 50 for 0.25 μ m technology

Magnitude, or be about 20 for 0.13 μ m

Magnitude.The voltage at this ultra-thin gate oxide two ends may be temporarily high a lot of than Vcc when programming, it typically is 2.5 volts for the integrated circuit with 0.25 μ m technology manufacturing, are 1.2 volts for the integrated circuit with 0.13 μ m technology manufacturing.This ultrathin oxide can tolerate up to 4 or 5 volts when the remarkable degeneration that does not have transistor performance usually.

Description of the invention described here and its application are illustrative, are not to limit the scope of the invention.Can carry out variation and the modification of embodiment disclosed herein, the actual alternative of the various elements of embodiment and product of equal value are known for those of ordinary skills.For example, the various voltages that propose in each example only are illustrative, because people select accurate voltage that some differences are arranged in a voltage range, and under any circumstance voltage is all relevant with device property.Terms rows word line and row bit line are used for being described in the type of the normally used line of memory, but some memories can have other call.And various doping types can transoid, so that above-mentioned n channel transistor can replace with the p channel transistor.In this case, the p channel transistor will form in big n trap, and can use the p+ layer of burying.Under the condition that does not depart from the scope of the present invention with spirit, can carry out these and other distortion and modification to embodiment disclosed herein.

Claims

1. a programmable memory cell is formed in the p N-type semiconductor N substrate, and is used for having the memory array of row bit line and row word line, and this memory cell comprises:

Transistor has the semiconductor region that the 2nd p+ of grid that p+ mixes, the gate dielectric between above this grid and the described substrate and contiguous this grid mixes; And

The semiconductor region that wherein transistorized the 2nd p+ mixes one of is connected in the described capable word line, and wherein said capable word line forms by the n type district at the near surface of described Semiconductor substrate.

2. memory cell as claimed in claim 1, wherein said grid is by forming one of in the described row bit line.

3. memory cell as claimed in claim 1, wherein when described memory cell has been programmed, described memory cell further is included in the doped region that is programmed that forms in the described substrate in the channel region.

4. a programmable memory cell is formed in the n type trap, and is used in the memory array with row bit line and row word line, and this memory cell comprises:

Transistor has the semiconductor region that the 2nd n+ of grid that n+ mixes, the gate dielectric between above this grid and the substrate and contiguous this grid mixes; And

The semiconductor region that wherein transistorized the 2nd n+ mixes one of is connected in the described capable word line, and wherein said capable word line forms by the p type district at the near surface of described n type trap.

5. memory cell as claimed in claim 4, wherein said grid is by forming one of in the described row bit line.

6. memory cell as claimed in claim 4, wherein when described memory cell has been programmed, described memory cell further is included in the doped region that is programmed that forms in the described substrate in the channel region.

7. memory cell as claimed in claim 4, wherein said n type trap is replaced by n type substrate.