CN100490541C

CN100490541C - Method for reducing phase-locked-loop shake in video-com application

Info

Publication number: CN100490541C
Application number: CNB200510098309XA
Authority: CN
Inventors: 朱昌志; 黄文艺
Original assignee: HONGXIN SCIENCE AND TECHNOLOGY Co Ltd
Current assignee: HONGXIN SCIENCE AND TECHNOLOGY Co Ltd; Terawins Inc
Priority date: 2005-09-07
Filing date: 2005-09-07
Publication date: 2009-05-20
Anticipated expiration: 2025-09-07
Also published as: CN1731862A

Abstract

The invention provides a method for decreasing the shake of a simulated phase-locked loop in the video application filed. The HSync/Csync is replaced with a fake Hsync signal to be locked in the phase-locked loop during the vertical cover period, so that the fake HSync signal with a fixed period can only be seen as a wire locked touch signal by the simulated phase-locked loop, without COAST signal at the same time. Besides, the fake HSync is vernierly regulated to be assorted with the front edge of the outside HSync/Csync, thereby decreasing the shake of the phase-locked loop minimally.

Description

Reduce the method for phase-locked-loop shake in the video signal application

Technical field

The relevant analog video of the present invention is used, and refers in particular to and reduce analog pll circuit (Phase-lock loop, the method for PLL) rocking in video signal analog digital transformation applications.

Background technology

It is popular everywhere that the analog video signal application remains, use line locking (line-lock) analog pll circuit (Phase-lock loop, PLL) and the trace lines cycle (H-Sync cycle) uses low data clock news (clock) of rocking are recovered, analog video is very important for catching.

Traditional method is to use H-Sync (horizontal synchronization), from the input of RGB (RGB) video signal stream, or from CSync (the synthetic Sync of voltage cutting, take from YPbPr (aberration terminal) video signal component) send into analog pll circuit, and during the use vertical blanking as COAST (momentum gliding) signal of PLL, keep the speed of phase-locked loop.

But HSync or Csync do not keep the identical cycle usually during vertical blanking, even by means of the COAST signal, the Zhong Xun that analog pll circuit produced is decay or accumulation a little still.

Summary of the invention

The object of the present invention is to provide a kind of method that reduces phase-locked-loop shake in the video signal application.

A kind of method that reduces phase-locked-loop shake in the video signal application, it is characterized in that: except a phase-locked loop and, also comprise a vertical synchronization VSync separator, one green synchronously/brightness synchronous cutting device and the synchronous HSync square of a dummy level, with the momentum gliding COAST signal that receives a video signal, vertical sync separator and a PLL_Clk signal of phase-locked loop, in order to produce the horizontal-drive signal Fake_HSync of a series of vacations, this phase-locked loop of input during momentum gliding COAST signal.

Beneficial effect of the present invention is: the HSync with vacation during vertical blanking replaces HSync/CSync, so the HSync that analog pll circuit will only be seen the fixed cycle need not the COAST signal simultaneously as the triggering signal that line locks.And false HSync is tailored into the HSync/Csync leading edge that cooperates the outside and rocking of PLL minimized.

The present invention will be more clear by following explanation conjunction with figs., and the purpose of accompanying drawing is only representing and most preferred embodiment of the present invention is described.

Description of drawings

The clock news that Fig. 1 demonstrates the conversion of prior art analog digital produce calcspar, and wherein analog pll circuit (PLL) does not have the COAST function.

Fig. 2 demonstrates the imaging distortion result of PLL among Fig. 1.

The clock news that Fig. 3 demonstrates the conversion of prior art analog digital produce calcspar, and wherein analog pll circuit (PLL) has the COAST function.

Fig. 4 demonstrates the imaging distortion result of PLL among Fig. 3.

The PLL clock news that Fig. 5 demonstrates analog digital conversion of the present invention produce calcspar.

Fig. 6 demonstrates the graphic result of PLL among Fig. 5.

Fig. 7 demonstrates several CSync, the VSync of separation and the COAST signal that is produced.

Fig. 8 demonstrates the present invention and how to monitor last false HSync.

Fig. 9,10,11 demonstrate how to finely tune false HSync.

Embodiment

What is meant by line locking PLL?

The video data of analog video input does not have clock news data, and when video image is wanted thread-changing and when will be changed picture but there is synchronous (Sync) data can notify video signal seizure/display unit.

Several aspects of data are as follows synchronously:

1, synchronous RGB (RGB) input that separates: have vertical synchronization (VSync) and horizontal synchronization (HSync).

2, synthetic synchronous RGB imports: only tool synthesizes (Csync) synchronously, and it incorporates VSync into HSync.

3, green (Sync_On_Green synchronously, SOG) (back both produces synchronous spike on the brightness channel in the aberration terminal input of the S-terminal input of the video signal of RGB input or YC separation or YPbPr, be called brightness (SOY) synchronously): must synchronous spike self simulation video signal be told with voltage cutting, produce the CSync signal then.

How does line locking PLL work and rocks?

The analog PLL of line locking is followed the trail of the cycle triggering signal, and HSync for example, and plan a divisor makes each time that HSync triggers, and PLL produces the Zhong Xun with the divisor similar number.

As long as HSync keeps the identical cycle, analog PLL will produce the Zhong Xun that does not accurately rock.

But HSync can not keep the identical cycle, and problem is:

1, because the voltage quasi position of IC input buffering pin, the edge of HSync may change a little, especially when the HSync signal slowly rise/when descending.Even use Shi Mite to touch input buffering pin (Schmitt Trigger Input Pad), improvement or limited.

2, when the synchronous mode of non-separation, the HSync among the Csync may disappearance or doubling frequency or is offset about VSync, and some PLL does not have the COAST function.

Even 3 most of analog PLL have the COAST function, but HSync still decay a little during COAST.

The objective of the invention is to solve second problem and the 3rd problem.

Sync and clock news calcspar

Some analog PLL does not have the COAST function.The clock news that Fig. 1 demonstrates prior art analog digital conversion produce calcspar, and wherein PLL does not have the COAST function, and this kind PLL can not support CSync (synthetic Sync), interrogate too slow because it recovers the PLL clock after during vertical blanking.Its imaging distortion the results are shown in Fig. 2.

Some other PLL has the COAST function, and as shown in Figure 3, this kind PLL is if recover very soon, i.e. no problem.But if PLL decay clock news are very fast, and recover slowly, then it will have a little distortion, as shown in Figure 4.

The present invention is shown in Fig. 5, wherein adds one " simulation HSync " square.Except for not support the PLL of COAST function to produce the HSync of a vacation, the present invention also has a fine setting mechanism to reduce the variation in HSync cycle.Its image is distortion not, as shown in Figure 6.

VSync separates

The purpose that VSync separates is for taking out VSync and produce the COAST signal from the Csync signal.With reference to figure 7, demonstrate several CSync, the VSync of separation and the COAST signal that is produced.

The VSync that is taken out is used for notifying the new picture of display unit to want in, and also can be used for measuring the cycle of vertical synchronization, and the COAST signal that is taken out can be used for PLL (if it has the COAST function), to keep identical PLL output speed.

But the analog PLL that has does not have the COAST function, makes it spend a period of time vibration clock news and is returned to normal clock news speed, even can't recover, because upset by the vertical blanking signal of Csync.Therefore the present invention produces the HSync replaced C Sync of a vacation during COAST.

Produce the false HSync and the HSync of emulation

Usage counter of the present invention (digit is the cycle of the line locking clock (PLL_Clk among Fig. 5) that PLL produced) is to take out the high/low width of the Csync during the non-COAST, so periodically produce the similar signal (Fake_HSync) of a HSync and continue to stimulate PLL during COAST.When CSync was during non-COAST, this Fake_HSync and original normal HSync (or CSync) had identical clock news number.

At first with reference to figure 5, the last edge of Csync is in order to produce a Fake_HSync_Select signal from the COAST signal of vertical sync separator synchronously.

Secondly, even it has identical count value in order to tracking, but the Zhong Xun (PLL_Clk among Fig. 5) that Fake_HSync still relies upon PLL to be exported.In case PLL decay will influence the Fake_HSync skew a bit, so we can not guarantee that last false HSync pulse meeting and extraneous Csync coincide, during terminal during jumping out COAST (as shown in Figure 8).So need a compensation logic smooth-going by COAST outlet sequence energy, this can reach by monitoring last Fake_HSync.With reference to figure 8, when last Fake_HSync is slow a bit (for example slow 1/4 cycle), then as expectedly produce next HSync pulse; When last Fake_HSync slowly when too many (for example slow surpassed 1/4 cycle), then omit last Fake_HSync.Two sections of the HSync of (COAST=0) and vacation when merging the HSync normal cycle, the so just HSync that can obtain simulating.

The fine setting of false HSync

Some PLL has built-in COAST function.Its effect is just like Fake_HSync when activating COAST to suppose to have inner trigger impulse again, and still in the COAST valid period, PLL is regardless of any Csync signal, and this will make PLL decay a little, produce bigger phase place and rock.For above-mentioned Fake_HSync, there is another kind of method can be finely tuned and reduce and rock.

This method is carried out when producing next Fake_HSync pulse, design " 1T " reach "+1T " clock news window (T is the clock news cycle) to monitor that extraneous Csync has leading edge and is shifted? if do not have, then produce next false HSync pulse in an identical manner; If displacement is arranged, see that then it falls into " 1T " or "+1T " clock news window, increase+1 clock news cycle or-1 clock news cycle and adjust next Fake_HSync counter, then recover the original cycle thereafter.

Among Fig. 9, when clock news decayed considerably lessly, its figure showed and need not fine setting, because rock very for a short time, can not influence the operation of PLL.

Among Figure 10, when Zhong Xun was fast slightly, its figure showed that the clock news will reduce 1T (1 clock news cycle).Among Figure 11, when Zhong Xun was slow slightly, its figure showed that the clock news will increase 1T (1 clock news cycle).

Spirit of the present invention and scope are decided by the patent protection scope, are not subject to the foregoing description.

Claims

One kind reduce video signal use in the method for phase-locked-loop shake, it is characterized in that: except using a phase-locked loop, also comprise use a vertical synchronization VSync separator, one green synchronously/brightness synchronous cutting device and the synchronous HSync square of a dummy level, with the momentum gliding COAST signal that receives a video signal, vertical sync separator and a PLL_Clk signal of phase-locked loop, in order to produce the horizontal-drive signal Fake_HSync of a series of vacations, this phase-locked loop of input during momentum gliding COAST signal.
2. the method for claim 1, it is characterized in that: described PLL_Clk signal is in order to follow the trail of the high/low width of a synthetic synchronous Csync signal in this video signal during non-COAST signal, so periodically produce this Fake_HSync signal, identical with a horizontal synchronization HSync signal in this video signal, during the COAST signal, continue to stimulate this phase-locked loop.
3. the method for claim 1 is characterized in that: monitor last Fake_HSync signal, when this last Fake_HSync signal slow be lower than predetermined cycle during mark, produce next horizontal synchronization HSync signal as scheduled; When this last Fake_HSync signal slow surpass this during mark in predetermined cycle, omit last Fake_HSync signal.
4. method as claimed in claim 3 is characterized in that: described predetermined cycle mark was 1/4 cycle.
5. method as claimed in claim 2, it is characterized in that: described Fake_HSync signal is monitored with one " 1T " clock news window and "+1T " clock news window, wherein T is the clock news cycle, whether has the phenomenon of leading edge displacement to observe extraneous synthetic synchronous Csync signal, if do not have, then produce next Fake_HSync signal in an identical manner; If displacement is arranged, see that then it falls into " 1T " or "+1T " clock news window, increase+1 clock news cycle or-1 clock news cycle and adjust next Fake_HSync, then recover the original cycle thereafter.