CN100472496C - Data transfer device - Google Patents
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- CN100472496C CN100472496C CNB200510091984XA CN200510091984A CN100472496C CN 100472496 C CN100472496 C CN 100472496C CN B200510091984X A CNB200510091984X A CN B200510091984XA CN 200510091984 A CN200510091984 A CN 200510091984A CN 100472496 C CN100472496 C CN 100472496C
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Abstract
A data transfer device, which comprises an input/output reception buffer (15), an input/output transmission buffer (14), a write data buffer (13), a read data buffer (12), a control information table (11a), a write data storing process section (17), a write data transmission section (34), a read data buffer storing process section (33), an input/output transmission buffer storing process section (18) and a control section (16) that executes an access control for controlling the access to the memory by the write data transmission section(34) and the read data buffer storing process section (33) based on a control information table (11). Thereby, a configuration optimum for both protocols of the memory bus and the input/output bus is obtained and the out-of-order execution is also achievable.
Description
Technical field
The present invention relates to a kind of technology that data transmission in for example bus bridge etc. is realized control.
Background technology
Recently, adopted and met for example I/O (I/O) device of the high-speed communication standard of gigabyte Ethernet and fiber channel.In order to keep synchronous therewith, signal conditioning package also needs to improve the data transmission performance in the bus bridge of for example realizing the data transmission between I/O bus and the memory bus.
Figure 14 schematically shows the structure of conventional bus bridge; And Figure 15 schematically shows the structure of the signal conditioning package that is equipped with bus bridge.Signal conditioning package 100 shown in Figure 15 comprises CPU (central processing unit) (CPU) 21-1 and 21-2, system controller 23-1 and 23-2, bus bridge 20-1 and 20-2, crossbar switch 24, storer 22-1,22-2,22-3 and 22-4 and I/O device 25.
CPU 21-1, storer 22-1 and 22-2 and crossbar switch 24 are connected to system controller 23-1; Equally, CPU 21-2, storer 22-3 and 22-4 and crossbar switch 24 are connected respectively to system controller 23-2.
Two I/O devices 25 are connected respectively to bus bridge 20-1 and 20-2 by I/O bus 26; And described bus bridge 20-1 and 20-2 are connected respectively to crossbar switch 24 by memory bus 27.
In other words, each system controller 23-1 and 23-2 are connected respectively to bus bridge 20-1,20-2 by crossbar switch 24, so that can communicate by letter betwixt.
The back, the reference number for the expression bus bridge when needs are specified one of a plurality of bus bridges, will use reference number 20-1 and 20-2; And when to represent to appoint-during bus bridge, then use reference number 20.
As shown in figure 14, between the I/O bus 26 and memory bus 27 that bus bridge (memory I/O bus bridge) 20 is arranged between I/O device 25 and the crossbar switch 24, and carry out the configuration of this mode, make and between described I/O bus 26 and memory bus 27, transmit data that wherein I/O bus 26 and memory bus 27 have the clock frequency and the data length of the data that the agreement that differs from one another for example will transmit.
In the signal conditioning package 100 that is equipped with conventional bus bridge 20, memory bus 27 comprises: write data signal line 27b sends write data and the request (address) that is used for writing to 22-4 at storer 22-1 data by this write data signal line 27b; And reading data signal line 27a, send the read data of from storer 22-1 and 22-4, reading by this reading data signal line 27a.In addition, I/O bus 26 comprises the I/O received signal line 26a and the I/O transmission signal wire 26b that is used for sending to I/O device 25 data that is used for receiving from I/O device 25 data.
As shown in figure 14, conventional bus bridge 20 comprises transmission buffer 201, reception buffer 202 and control information table 203.
Transmission buffer 201 is used for the data that interim storage is read from storer 22-1 to 22-4, reads to carry out direct memory access (DMA) (DMA).I/O is sent signal wire 26b and reading data signal line 27a is connected to transmission buffer 201, so that can communicate by letter betwixt, and carry out such configuration, make by reading data signal line 27a will from storer 22-1 to the data storage of 22-4 in transmission buffer 201, and send to I/O device 25 by the read data that I/O transmission signal wire 27b will be stored in transmission buffer 201.
Reception buffer 202 be used for interim storage will write store 22-1 to the data of 22-4, write to carry out DMA.I/O received signal line 26a and write data signal line 27b are connected to reception buffer 202, so that can communicate by letter betwixt.And carry out such configuration, making will be from the data storage of I/O device 25 in reception buffer 202; And according to the control information that is stored in the control information table 203, the data that will be stored in the reception buffer 202 by write data signal line 27b send to storer 22-1 to 22-4 as write data.
In other words, as shown in figure 14, in conventional bus bridge 20, memory bus 27 and I/O bus 26 shared transmission buffer 201 and reception buffers 202.In addition, memory bus 27 is carried out such configuration, make to send request and data by same write data signal line 27b.In memory bus 27, request is handled as identical bag with data.If handle a plurality of memory requests simultaneously, then sequentially carry out corresponding the processing.
Transmission buffer 201 and reception buffer 202 are carried out such setting, make and store and sense data in the mode of first in first out (FIFO).
Control information table 203 is used to control the access to 22-4 to storer 22-1.Control information table 203 is used for realizing sending request, read the read data that is stored in transmission buffer 201, being stored in the control of the write data etc. of reception buffer 202 to storer 22-1 to the 22-4 transmission to 22-4 to storer 22-1.
As mentioned above, people expect to strengthen the performance of the data transmission in the conventional bus bridge 20.For example, open (KoKai) number 2000-132503 of Japan special permission discloses a kind of data transmission device, and the interface board that wherein comprises target is provided with a plurality of reception buffers, so that originators (initiator) deal with data effectively.
Yet, in conventional bus bridge 20, carry out such configuration, make each circuit transmission buffer 201 and reception buffer 202 all are set with as circuit arrangement, thereby caused and be difficult to transmission buffer 201 and reception buffer 202 are configured to for all optimized defective of the agreement of memory bus 27 and I/O bus 26.
In addition, following defective has economically also appearred.For example, in I/O bus 26 or memory bus 27, when the agreement of Change Example such as bus clock or data length, conventional bus bridge 20 can not locate to deal with described change.Thereby, will change whole bus bridge 20 into new bus bridge.
In addition, usually in the processor unit of for example CPU, use a kind of known technology, the wherein order of describing in the not consideration program and instruction (unordered execution) in the executive routine is so that realize high speed processing.
Simultaneously, there is a kind of known technology, wherein in bus bridge 20, regards different bags as by address portion in the bag that will send to memory bus 27 and data division, and these bags are handled and sent.
Yet, in conventional bus bridge 20, I/O transmission buffer 201 and I/O reception buffer 202 are carried out such setting, feasible mode with FIFO reads and writes data.Thereby, can not realize unordered execution by the technology that address portion and data division are handled as different bags.
In addition, in conventional bus bridge 20, problem below existing: promptly, (wherein a hypothesis I/O bus 26 physically is virtual in the pseudo channel function is connected with a plurality of channels) can not realize overload (overtaking) control of wrapping when realizing the pseudo channel function.
Summary of the invention
Consider that the problems referred to above design the present invention.Thereby, an object of the present invention is to provide a kind of data transmission device and a kind of signal conditioning package, it has for all optimized configuration of the agreement of memory bus and input/output bus, and can carry out unordered execution (out-of-order execution).
Therefore, according to a kind of data transmission device of the present invention, be used between memory bus and input/output bus, transmitting data, wherein connect this memory bus by this way, make its can with the communicating by letter of the storer that is equipped with request signal line, write data signal line and reading data signal line in, request, write data and read data are transmitted as bag respectively; Described input/output bus is equipped with and sends signal wire and received signal line, to send data and this receptions data respectively as the bag that comprises the transmission address that sends data and these transmission data and the bag that comprises the receiver address of reception data and these reception data sends to input/output device or from this input/output device reception by sending signal wire and received signal line, described data transmission device comprises: the I/O reception buffer, can store these reception data that receive from this input/output device by this received signal line; The I/O transmission buffer can be stored these transmission data that are sent to this input/output device by this transmission signal wire; Write data buffer can be stored and will be sent to this write data of this storer by this write data signal line; Read data can be stored by this reading data signal line and this read data of receiving from this storer; The control information table has a plurality of corresponding to the access of this storer and the clauses and subclauses (entry) that form; Write data buffer stores processor parts will be stored in this reception data storage in this I/O reception buffer in this write data buffer; The write data transmit block by this write data signal line, is sent to this storer with these reception data that are stored in this write data buffer as write data; Read data stores processor parts will be stored in this read data from this read data that this storer receives; I/O transmission buffer stores processor parts read the read data that is stored in this read data, and these data are stored in this I/O transmission buffer as the transmission address of these transmission data with these transmission data; And control assembly, control the access of being undertaken by this write data transmit block and this read data memory unit to this storer according to this control information table.
Can carry out such configuration, make when writing processing with from this input/output device during to these memory transfer data, this write data transmit block sends this write data by this write data signal line, and write data are to be divided into the storage access capacity and to form by being stored in these reception data in this write data buffer.
In addition, can carry out such configuration, make this control information table between request and stored position information (wherein storing the write data corresponding), set up corresponding relation with the request in the write data buffer, and it is managed, when when this memory bus sends these data, this control assembly utilizes serial ID to read this stored position information that is written to the clauses and subclauses of this control information table from the write data impact damper as pointer, and extracts this write data according to this stored position information from this write data buffer.
In addition, can carry out such configuration, make when carry out from this storer to this input/output device read to handle the time, when the total amount of data of a plurality of read datas in being stored in this read data satisfies the condition that sends the bag size, these I/O transmission buffer stores processor parts are read the read data that is stored in this read data, these data are sent data as this, and be stored in this I/O transmission buffer with the transmission address of these transmission data.
In addition, can carry out such configuration, make this control information table between relevant with this request at least serial ID and stored position information, set up corresponding relation about the memory location of read data (it is corresponding to the request in the read data), and it is managed, when when this memory bus receives this read data, this control assembly utilizes this serial ID to read this stored position information that is written to the clauses and subclauses of this control information table from described read data as this pointer, and according to this stored position information this read data is stored in this read data.
In addition, can carry out such configuration, make this control information table in same field, store this stored position information of described read data and this stored position information of write data impact damper, and storage is used for writing the identifying information of handling and reading to handle according to the request difference.
As mentioned above, according to the present invention, will obtain a following effect and advantage at least:
(1) strengthened the performance of data transmission;
(2) obtained the configuration that the agreement to memory bus and input/output bus all is fit to;
(3) even when carrying out the pseudo channel function, also can realize the overload control of wrapping;
(4) in memory bus, can carry out the unordered execution of read data.
Description of drawings
Fig. 1 schematically shows the structure of the bus bridge (data transmission device) as first embodiment of the invention;
Fig. 2 schematically shows the structure of the signal conditioning package that is equipped with bus bridge;
Fig. 3 is the precedence diagram that the processing when transmitting write data in as the bus bridge of first embodiment of the invention is described;
Fig. 4 is the precedence diagram that the processing when transmitting read data in as the bus bridge of first embodiment of the invention is described;
Fig. 5 schematically shows the structure as the bus bridge of second embodiment of the invention;
Fig. 6 shows the example according to the structure of the control information table in the bus bridge of second embodiment of the invention;
Fig. 7 shows the data stream when transmitting read data in as the bus bridge of second embodiment of the invention;
Fig. 8 shows the example as the structure of the control information table in the bus bridge of third embodiment of the invention;
Fig. 9 shows the data stream when transmitting write data in as the bus bridge of second embodiment of the invention;
Figure 10 is the precedence diagram that the processing when transmitting write data in as the bus bridge of third embodiment of the invention is described;
Figure 11 schematically shows the structure as the bus bridge of fourth embodiment of the invention;
Figure 12 shows the example as the structure of the control information table in the bus bridge of fourth embodiment of the invention;
Figure 13 shows the data stream when transmitting read data and write data in according to the bus bridge of fourth embodiment of the invention;
Figure 14 schematically shows the structure of conventional bus bridge; And
Figure 15 schematically shows the structure of the signal conditioning package that is equipped with the conventional bus bridge.
Embodiment
Below, embodiments of the invention will be described.
(A) explanation of first embodiment
Fig. 1 schematically shows the structure of the bus bridge (data transmission device) as first embodiment of the invention; And Fig. 2 schematically shows the structure of the signal conditioning package that is equipped with bus bridge.
As shown in Figure 2, signal conditioning package 1 comprises CPU (CPU (central processing unit)) 21-1 and 21-2, system controller 23-1 and 23-2, storer 22-1,22-2,22-3 and 22-4, crossbar switch 24, I/O device 25 and bus bridge 10a-1 and 10a-2.
CPU 21-1 and 21-2 operation OS (operating system) and application program, thus realize various operational processes.
System controller 23-1 and 23-2 are used for CPU management 21-1 and 21-2, storer 22-1 send and receive to the data between 22-4, I/O device 25 etc.System controller 23-1 is connected to CPU 21-1, storer 22-1 and 22-2 and crossbar switch 24, so that can communicate by letter betwixt, and carry out the configuration of this mode, make the data between its CPU management 21-1, storer 22-1 and 22-2 and the crossbar switch 24 send and receive.
Equally, system controller 23-2 is connected to CPU 21-2, storer 22-3 and 22-4 and crossbar switch 24, so that can communicate by letter betwixt, and carry out the configuration of this mode, make the data between its CPU management 21-2, storer 22-3 and 22-4 and the crossbar switch 24 send and receive.
Storer 22-1 is used for storage employed data, instruction etc. when CPU 21-1 and the 21-2 executable operations to 22-4.The back for the reference number of expression storer, when needs are specified storer in a plurality of storeies, uses reference number 22-1 to 22-4.Yet, when specifying arbitrary storer, use reference number 22.
I/O (I/O) device 25 is the various electronic installations that are installed on the signal conditioning package 1 of for example hard disk, scanner etc., and is connected respectively to bus bridge 10a-1 and 10a-2 by I/O bus (input/output bus) 31, so that can communicate by letter betwixt.
As shown in Figure 1, memory bus 30 comprises reading data signal line 30a, write data signal line 36b and request signal line 30c; And bus bridge 10a-1 and 10a-2 are connected to storer 22 by crossbar switch 24, so that can communicate with one another.Carry out such configuration, make in reading data signal line 30a, to receive read data respectively, in write data signal line 30b, send write data and in request signal line 30c, send the request (address) that (packet format) wrapped in conduct.The back will provide the explanation about request, write data and read data.
In the present embodiment, carry out such configuration, make under situation about not receiving, send eight requests continuously from bus bridge 10a-1 and 10a-2 respectively from any response of storer 22; And, the data length (storage access size) of a bag of read data and write data is fixed as 128 bytes.
I/O bus 31 connects I/O device 25 and bus bridge 10a-1 and 10a-2, so that can communicate with one another, and comprises that I/O received signal line (received signal line) 31a and I/O send signal wire (transmission signal wire) 31b.I/O received signal line (received signal line) 31a is used for receiving data (reception data) from I/O device 25.I/O sends signal wire (transmission signal wire) 31b and is used for sending data (transmission data) to I/O device 25.Carry out such configuration, make that physically two different signal wires are used for receiving and sending data., carry out such configuration herein, feasible transmission and the reception that realizes full duplex.
In addition, I/O is sent signal wire 31b carry out such configuration, it is sent data as the bag that comprises the transmission address that sends data and send data.31a carries out such configuration to I/O received signal line, makes it will receive data and receives as the bag that comprises the receiver address that receives data and receive data.In addition, the data length that sends signal wire 31b reception data that send and receive and the bag that sends data by I/O received signal line 31a and I/O is a length variable, and maximal value is the 4K byte.
Subsequently, in first embodiment,, when specifying one of a plurality of bus bridges, use reference number 10a-1 and 10a-2 for the reference number that is used to represent bus bridge; And in the time will representing arbitrary bus bridge, then use reference number 10a.
As shown in Figure 1, the bus bridge 10a of first embodiment comprises read data 12, write data buffer 13, I/O transmission buffer (I/O transmission buffer) 14, I/O reception buffer (I/O reception buffer) 15, control assembly 16, control information table 11a, receive data processor (write data buffer stores processor parts) 17, I/O transmission buffer stores processor parts (I/O transmission buffer stores processor parts) 18, bus 19a, 19b, 19c and 19d, read data stores processor parts 33 and write data transmit block 34.
The data that I/O reception buffer (I/O reception buffer) 15 interim storages receive from I/O device 25.I/O received signal line 31a and bus 19a are connected to I/O reception buffer 15, so that can communicate with one another; And carry out such configuration, make that storage receives data (reception data) from the I/O that I/O device 25 receives in I/O reception buffer 15.In I/O reception buffer 15, carry out such configuration, make that storing and read I/O in the mode of FIFO (first in first out) receives data.
In addition, in the bus bridge 10a of first embodiment, carry out such configuration, make to realize the pseudo channel function, wherein, physically an I/O bus 31 is treated to hypothesis, and it virtually is connected with many channels.For realizing the pseudo channel function, be the pointer of each pseudo channel setting about the read and write of I/O reception buffer 15.
Receive data processor 17 and receive data, and handle the bag that is stored in the I/O reception buffer 15 from I/O bus 31.Especially, carry out the setting of this mode to receiving data processor 17, make its extraction write I/O reception buffer 15 bag, judge the bag that extracts is read request or write request, the header of the bag that will receive is divided into storage access size (being 128 bytes in the present embodiment) and to the information (control information) of control assembly 16 transmission necessity in control information table 11a, to store data.
In addition, receive the I/O that data processor (write data buffer stores processor parts) 17 will be stored in the I/O reception buffer 15 and receive data storage in write data buffer 13.Carry out the configuration of this mode to receiving data processor 17, make its when carry out with write data send to memory bus 30 write processing (writing transaction) time, reading I/O from I/O reception buffer 15 and receive data, I/O is received data be divided into the data division beyond header portion and the header portion and data division write the write data buffer 13, is dummy status up to write data buffer 13 for full state or I/O reception buffer 15.
The write data that write data buffer 13 storage will send by write data signal line 30b is with in the writing data into memory 22.Write data buffer 13 is connected to write data signal line 30b and bus 19a, so that can communicate with one another, and carries out such configuration, makes by receiving data processor 17 storage write datas.
Write data transmit block 34 is carried out such configuration, make and send request (detailed description will be made in the back) at the write data that is sent to memory bus 30 from control assembly 16, when permission sends write data (will describe in detail thereafter) from memory bus 30, generation is the write data of 128 bytes of the size of data of a bag, and sends the write data that produces by memory bus 30b.
The read data that read data 12 storages receive from storer 22 by reading data signal line 30a.Read data 12 is carried out such configuration, make when control assembly 16 sends back with the read request that illustrates, guarantee zone in advance corresponding to read data length to be received, and as the response to read request, the read data that storage receives from storer 22 in the zone of guaranteeing.Thereby, can prevent overflowing of the read data 12 that causes by read data.
Read data 12 is carried out such configuration, make and in control information table 11a, store the pointer that points to the zone of guaranteeing corresponding to the read request that sends.
Read data stores processor parts 33 will be stored in the read data 12 from the read data that storer 22 receives by reading data signal line 30a.Read data stores processor parts 33 are carried out the configuration of this mode, make the pointer of its inquiry control information table 11a, and the read data that receives is stored in this memory location with the memory location that obtains the read data that points to the reception in the read data 12.
I/O transmission buffer stores processor parts (I/O transmission buffer stores processor parts) 18 are read the read data that is stored in the read data 12, and with these data as sending data, be stored in the I/O transmission buffer 14 with header (transmission address) about these transmission data.
I/O transmission buffer stores processor parts 18 are used for when having stored the read data of the capacity (sending the condition of bag size) that reaches a bag that sends by I/O bus 31 in read data 12, promptly, when satisfying the condition that sends the bag size, read the read data that is stored in a bag in the read data 12, and with these data as sending data, be stored in the I/O transmission buffer 14 with the transmission address of these transmission data.
I/O transmission buffer (I/O transmission buffer) 14 storages send the transmission data that signal wire 31b is sent to I/O device 25 by I/O.I/O transmission buffer 14 is carried out such configuration, make its mode store and read read data with FIFO.In addition, I/O transmission buffer 14 is connected to I/O sends signal wire 31b and bus 19c, so that can communicate with one another.
Control information table 11a has eight clauses and subclauses (field), and management sends to the request of memory bus 30.These clauses and subclauses to control information table 11a are carried out such configuration, make when from control assembly 16 when memory bus 30 sends request, control assembly 16 is registered control informations; And, when the data transmission finished by memory bus 30, control assembly 16 this control informations of deletion.
Herein, the control information that is stored in the clauses and subclauses of control information table 11a for example comprises, points to the pointer as the zone of guaranteeing to the response of the read request that sends and by read data 12.
Will be when transmitting write data according to the explanation of the order shown in Fig. 3, the processing in the bus bridge 10a of the first embodiment of the present invention that conduct makes up according to foregoing.
In bus bridge 10a, (receive data when data being received from the I/O that I/O device 25 sends by I/O bus 31 (I/O received signal line 31a), when bag write data) sends to bus bridge 10a (with reference to the arrow A among the figure 3 10), the bag that receives from I/O bus 31 is written into I/O reception buffer 15.
Then, receive data processor 17 and from I/O reception buffer 15, extract the bag that writes I/O reception buffer 15, and when the bag that extracts is write data, extract header and data are divided into 128 bytes, and control assembly 16 is registered necessary information (control information) in the control information table.
In addition, receive the data division that data processor 17 will write the bag of I/O reception buffer 15 and write write data buffer 13.
Carry out such configuration, make when realizing the pseudo channel function, in I/O reception buffer 15, prepare read pointer and write pointer, and at first handle bag with higher priority for each pseudo channel.
Then, when sending data transmission permission bag from storer 22 (memory bus 30) (with reference to the arrow A the figure 3 60), write data transmit block 34 just sends to write data storer 22 (with reference to the arrow A among the figure 3 70).
Below, will be when transmitting read data, as the processing among the bus bridge 10a of the first embodiment of the present invention according to order explanation shown in Figure 4.(receive data when data being received from the I/O that I/O device 25 sends by I/O bus 31 (I/O received signal line 31a), when bag read request) sends to bus bridge 10a (with reference to the arrow B among the figure 4 10), in bus bridge 10a, the bag that receives from I/O bus 31 is written into I/O reception buffer 15.
Receive data processor 17 and from I/O reception buffer 15, extract the bag that writes I/O reception buffer 15.When the bag that extracts is read request, receive data processor 17 and extract its headers, and be divided into 128 bytes respectively, and to the required information of control information table registration control assembly 16.
When realizing the pseudo channel function, carry out such setting, make and in I/O reception buffer 15, prepare read pointer and write pointer for each pseudo channel; And at first handle bag with higher priority.
During the read data of a bag in having reached I/O bus 31 in the read data 12, I/O transmission buffer stores processor parts 18 extract read data from read data 12, and data are write I/O transmission buffer 14.
When credit allows to send read data (with reference to the arrow B among the figure 4 50), I/O transmission buffer 14 sends read data bag (I/O sends signal wire 31b) (with reference to the arrow B among the figure 4 60) to I/O bus 31.
As mentioned above, the bus bridge 10a according to first embodiment of the invention comprises read data 12, write data buffer 13, I/O transmission buffer 14 and I/O reception buffer 15.Thereby memory bus 30 and I/O bus 31 have special-purpose impact damper respectively, thereby can adopt the buffer sizes and the pointer control method of two kinds of agreements that are suitable for memory bus 30 and I/O bus 31.
In addition, even when any the agreement etc. in memory bus 30 and the I/O bus 31 changes, have only needs to change in read data 12, write data buffer 13, I/O transmission buffer 14 and the I/O reception buffer 15 in order to can handle the agreement of change.Thereby this structure has dirigibility, versatility and good economic effect.
In addition, when realizing the pseudo channel function, the overload control that bus bridge 10a can wrap.
In addition, memory bus 30 comprises request signal line 30c, write data signal line 30b and reading data signal line 30a, and by these signal wires, carries out the transmission and the reception of data with the form of each bag.Thereby, when bus bridge 10a of the present invention being applied to large scale system with a plurality of system controller 23-1 of being used for controlling CPU21-1 and 21-2 and storer 22 and 23-2, after control assembly 16 sends request and after the destination reception notification of data, send reality with processed data to system controller 23-1 and 23-2, thereby improved the performance of data transmission.
(B) explanation of second embodiment
Fig. 5 schematically shows the structure as the bus bridge 10b of second embodiment of the invention.Fig. 6 shows the example as the structure of the control information table among the bus bridge 10b of second embodiment of the invention.
Identical with the situation of the bus bridge 10a of first embodiment, between the I/O of signal conditioning package 1 device 25 and crossbar switch 24 (with reference to figure 2), will be arranged between I/O bus 31 and the memory bus 30 as the bus bridge 10b (10b-1 and 10b-2) of second embodiment.Bus bridge 10b is carried out the configuration of this mode, make it carry out the transmission data between I/O bus 31 and memory bus 30, wherein I/O bus 31 and memory bus 30 have the clock frequency of the data that the agreement that differs from one another for example will transmit betwixt and data length etc.
As shown in Figure 5, the bus bridge 10b of second embodiment comprises the control information table 11b among the bus bridge 10a of first embodiment, and its other parts make up in the mode identical with the bus bridge 10a of first embodiment.In the drawings, identical with above-mentioned reference number reference number is represented identical or identical in fact part; Thereby omit its detailed description.
In the bus bridge 10b of second embodiment, carry out such configuration, make to each read request in control assembly 16 read requests (maximum eight) that send, that carrying out is provided with unique serial ID respectively, and manage each read request by these serial IDs.
In addition, in the bus bridge 10b of second embodiment, the read data that receives from memory bus 30 also has above-mentioned serial ID the header portion of its bag.In addition, in the bus bridge 10b of second embodiment, the read data that comes from memory bus 30 does not always arrive according to the order that sends request from control assembly 16.But carry out such configuration, make and sequentially receive the data (unordered execution) of having finished processing by CPU21 or memory bus 30 by memory bus 30, and read data stores processor parts 33 are according to serial ID during with reference to control information table 11b, the read data that the precalculated position storage in read data 12 receives from memory bus 30.
As shown in Figure 6, in each clauses and subclauses of eight clauses and subclauses, control table 11b is by serial ID, storage address and read data pointer value (the RD buffer pointer value as the control information and the generation that corresponds to each other; Stored position information) constitutes.In other words, control information table 11b manage at least correspond to each other serial ID that produce, relevant with request and about in the read data 12 with the stored position information of the memory location of the read data of asking to be correlated with.
The read data pointer value be expression when control assembly 16 when memory bus 30 sends read requests, point to and guarantee in advance in order to the pointer value of storage corresponding to the zone of the read data of read request reception.The write pointer of read data 12 is carried out the configuration of this mode, it is not only moved in the mode that increases progressively, and the control and treatment random value, thereby can carry out unordered execution.
Read data stores processor parts 33 are carried out the configuration of this mode, make when receiving read data, utilization is attached to the serial ID inquiry control information table 11b of read data, so that from clauses and subclauses, read the pointer value of read data 12 corresponding to serial ID, and the memory location of definite read data.
In other words, the bus bridge 10b to second embodiment carries out such configuration, feasible each clauses and subclauses of utilizing among the serial ID specified control table 11b relevant with each clauses and subclauses.In example shown in Figure 5, for constituting eight serial IDs that clauses and subclauses distribute natural number 1-8 to represent respectively of control table 11b.
Determine the clauses and subclauses in control table 11b, used according to serial ID.
In addition, the bus bridge 10b of second embodiment is also carried out such configuration, make when having received the read data of a bag in read data 12, I/O transmission buffer stores processor parts 18 are sent to I/O transmission buffer 14 with these data.
Fig. 7 shows the data stream when transmission read data in as the bus bridge 10b of the second embodiment of the present invention.
In the bus bridge 10b of second embodiment, will write I/O reception buffer 15 from the bag that I/O bus 31 receives; And receive data processor 17 and extract the bag that writes I/O reception buffer 15.Herein, when the bag that extracts is read request, receives data processor 17 header is divided into 128 bytes respectively, and realize stored counts the data length of read data.
According to the stored counts that receives data processor 17, control assembly 16 is registered the pointer value of the read data 12 in the storage area of guaranteeing in advance according to read data length in control information table 11b, and as other necessary informations of the control information in the clauses and subclauses of representing by serial ID.
When from memory bus 30 reception read datas, read data stores processor parts 33 are divided into header portion and data division with read data, and obtain serial ID from header portion.Read data stores processor parts 33 are inquired about control information table 11b according to serial ID, and obtain the pointer value (stored position information) of the read data of the clauses and subclauses of being represented by serial ID.
In addition, read data stores processor parts 33 utilize the read data pointer value that obtains as write pointer, and read data is write in the position of being pointed to by pointer value in the read data 12.
When in read data 12, receiving the read data of the capacity (sending the condition of bag size) that reaches a bag that sends via I/O bus 31, I/O transmission buffer stores processor parts 18 read the read data that is stored in a bag in the read data 12, and with these data as sending data, be stored in the I/O transmission buffer 14 with the transmission address of these transmission data.
Then, when credit allowed to send read data, the bus bridge 10b of second embodiment just sent the bag of read data to I/O bus 31.
As mentioned above, according to bus bridge 10b, can obtain the work effect identical with the first above-mentioned embodiment as second embodiment of the invention.In addition, also can obtain following effect.Promptly, serial ID is attached to the read request that sends from control assembly 16, and control information table 11b management correspond to each other the serial ID (it is relevant with request) that produces and about in the read data 12 with the stored position information of the memory location of asking corresponding read data.Thereby, even not according to the order (unordered) of read request when memory bus 30 receives read datas, read data stores processor parts 33 also can be inquired about control information table 11b according to the serial ID of the read data that is attached to reception, to obtain the memory location of read data.Thereby, in read data 12, can be according to the sequential storage read data of the read request that receives from I/O bus 31.
In other words, in the bus bridge 10b of second embodiment, can in memory bus 30, realize the unordered execution of read data.
In addition, in control information table 11b, store the pointer value of read data 12 according to each serial ID.Thereby, can be with correct sequential storage data in read data 12, and need not according to the order that receives read data from memory bus 30.
And, eliminated order dependent by the read data of memory bus 30 transmission.Thereby, eliminated the waiting status that causes by the sequence limit of reading data signal line 30a.Therefore, strengthened the effective throughput of memory bus 30.
(C) explanation of the 3rd embodiment
Fig. 8 shows the example as the structure of the control information table among the bus bridge 10c of third embodiment of the invention.
Identical with the mode of the bus bridge 10a of first embodiment, between the I/O of signal conditioning package 1 device 25 and crossbar switch 24 (with reference to figure 2), be arranged between I/O bus 31 and the memory bus 30 as the bus bridge 10c (10c-1,10c-2) of third embodiment of the invention; And carry out the configuration of this mode, make and between I/O bus 31 and memory bus 30, realize data transmission, wherein I/O bus 31 and memory bus 30 have the agreement that differs from one another, for example the clock frequency of the data that will transmit betwixt and data length etc.
The bus bridge 10c of the 3rd embodiment comprises control information table 11c, and it has replaced the control information table 11b of the bus bridge of second embodiment (with reference to figure 5).Other part then disposes in the mode identical with the bus bridge 10b of second embodiment.
In the bus bridge 10c of the 3rd embodiment, the read pointer of write data buffer 13 is carried out the configuration of this mode, it is not only moved to increase progressively form, and be controlled as the processing random value, thereby can extract data from write data buffer 13 randomly; Thereby, can be with consistent from the data sending request of memory bus 30.
In addition, in the bus bridge 10c of the 3rd embodiment, identical with the mode of read request among the bus bridge 10b of second embodiment, carry out such configuration, make and distribute unique serial ID respectively for the write request of carrying out, send by control assembly 16 (maximum eight); And utilize serial ID to manage each request.
In the bus bridge 10c of the 3rd embodiment, identical with the mode of read request among the bus bridge 10b of second embodiment, the write data that sends to memory bus 30 also has above-mentioned serial ID at its header portion.In addition, the bus bridge 10c to the 3rd embodiment carries out such configuration, feasible will being input to the control assembly 16 from data transmission permission and the data retransmission requests that memory bus 30 sends.
As shown in Figure 8, control table 11c has eight clauses and subclauses; Each clauses and subclauses is by serial ID, storage address and write data buffer pointer value (the WD buffer pointer value as the control information and the generation that corresponds to each other; Stored position information) constitutes.In other words, control information table 11c manage at least correspond to each other produce, with the inter-related serial ID of request and about in the write data buffer 13 with the stored position information of the memory location of the corresponding write data of request.
The write data buffer pointer value is to receive the information (positional information, pointer value) that data processor 17 is used to specify the position of the data division (write data) that storage is relevant with the write request bag in the write data buffer 13, wherein receive the write request bag, and be stored in the I/O reception buffer 15 from I/O bus 30 (I/O received signal line 31a); And when storing write data in write data buffer 13, data processor 17 determining the write data buffer pointer value when receiving.
In the bus bridge 10c of the 3rd embodiment, identical with the mode of the control information table 11b of second embodiment, also each clauses and subclauses of control table 11c are carried out the configuration of this mode, it is specified by the serial ID relevant with each clauses and subclauses.In example shown in Figure 8, the serial ID that distributes natural number 1-8 to represent for each clauses and subclauses in eight clauses and subclauses that constitute control table 11b.
And control table 11c is carried out such configuration, make it utilize serial ID to determine clauses and subclauses to be used.
In addition, bus bridge 10c to the 3rd embodiment carries out such setting, make for receive and write request bag that be stored in I/O reception buffer 15 from I/O bus 30 (I/O received signal line 31a), receive data processor 17 data division (write data) is stored in the write data buffer 13, and the memory location (write data buffer pointer value) of write data buffer 13 is stored among the control information table 11c.
Write data transmit block 34 is carried out the configuration of this mode, make its utilization be attached to the serial ID inquiry control information table 11c of write request, the pointer value that reads write data buffer 13 from the clauses and subclauses corresponding to serial ID to be determining the memory location of write data in write data buffer 13, and sends the write data that is stored in this memory location to memory bus 30 (write data signal line 30b).
Fig. 9 shows the data stream when transmission write data in as the bus bridge 10c of third embodiment of the invention.
In the bus bridge 10c of the 3rd embodiment, will write I/O reception buffer 15 from the bag that I/O bus 31 receives, and reception data processor 17 extracts the bag that writes I/O reception buffer 15.Herein, when the bag that extracts is write request, receives data processor 17 header is divided into 128 bytes respectively, the data length of read data is carried out stored counts, and in write data buffer 13, store data division (write data).
For example, when when memory bus 30 sends write data, the data that control assembly 16 receives from memory bus 30 send permission and the data retransmission requests obtains serial ID, and according to this serial ID inquiry control information table 11c, and obtain write data buffer pointer value (memory location) corresponding to this serial ID.
Write data transmit block 34 utilizes the write data buffer pointer value of obtaining as read pointer, read in the write data of storing in the position of pointing to by pointer value in the write data buffer 13, write data and header are merged, and data are sent to memory bus 30 (reading data signal line 30a).
Will according to order shown in Figure 10 explanation press that foregoing makes up, as the processing of the transmission of the write data among the bus bridge 10c of third embodiment of the invention.Precedence diagram shown in Figure 10 has illustrated the data transmission of carrying out by the memory bus 30 of 22 of the bus bridge 10c of the 3rd embodiment and storeies.
Write data transmit block 34 utilizes pointer value as read pointer, reads write data from write data buffer 13, and by write data signal line 30b write data is sent to storer 22 from bus bridge 10c
(with reference to the arrow C among Figure 10 30).
When storer 22 can't be received write data for some reason, storer 22 sent data retransmission requests (with reference to the arrow C among Figure 10 40) to bus bridge 10c.Write data transmit block 34 is attached to the pointer value of obtaining write data buffer 13 in the clauses and subclauses that the serial ID of data retransmission requests represents again from control information table 11c.And storer 22 utilizes this pointer value as read pointer, reads write data from write data buffer 13, and again write data is sent to storer 22 (with reference to the arrow C Figure 10 50) from bus bridge 10c by write data signal line 30b.
When storer 22 successfully received correct write data, storer 22 sent data to bus bridge 10c and finishes notice (with reference to the arrow C among Figure 10 60).And in bus bridge 10c, finish notice, discharge data buffer 13 and control information table 11c, and end process according to data transmission.
As mentioned above, according to bus bridge 10c, can obtain the work effect identical with the first above-mentioned embodiment as third embodiment of the invention.In addition, also can obtain following effect.That is, serial ID is attached to the write request that sends from control assembly 16; And control information table 11c management correspond to each other the serial ID (it is relevant with request) that produces and about in the write data buffer 13 with the stored position information of the memory location of asking corresponding write data.Thereby, for example, send permission even fail to send data from memory bus 30 according to the order of sending write request from control assembly 16, also can be by sending data retransmission requests, inquire about control information table 11c and make write data transmit block 34 send the serial ID of permitting and being attached to data retransmission requests according to the data that receive, to obtain the memory location of write data, the order of permission or data retransmission requests be read and be sent with the data from memory bus 30 to this write data can from write data buffer 13 transmissions from write data buffer 13.
In other words, in the bus bridge 10c of the 3rd embodiment, can utilize serial ID and extract write datas from write data buffer 13 randomly, thereby can utilize serial ID in memory bus 30, to realize retransmitting function and unordered execution.
In addition, in control information table 11c, request (serial ID) corresponding each other generation with write data.Thereby,, can prevent that write data is read out by from control information table 11c, deleting clauses and subclauses.Thereby, when making a mistake, need not by reading out deleted data.
(D) explanation of the 4th embodiment
Figure 11 schematically shows the structure as the bus bridge 10d of fourth embodiment of the invention.
Identical with the mode of the bus bridge 10a of first embodiment, between the I/O of signal conditioning package 1 device 25 and crossbar switch 24 (with reference to figure 2), be arranged between I/O bus 31 and the memory bus 30 as the bus bridge 10d (10c-1,10c-2) of fourth embodiment of the invention.Bus bridge 10d is carried out the configuration of this mode, make and between I/O bus 31 and memory bus 30, carry out data transmission, wherein I/O bus 31 and memory bus 30 have the agreement that differs from one another, for example the clock frequency of the data that will transmit betwixt and data length etc.
As shown in figure 11, the bus bridge 10d of the 4th embodiment comprises control information table 10d, and it has replaced the control information table 11a of the bus bridge 10a among first embodiment.And the other parts of bus bridge 10d are with the structural arrangements identical with the bus bridge 10a of first embodiment.In the drawings, identical with above-mentioned reference number reference number is represented identical or identical in fact part.Thereby, omit its detailed description.
Control information table 11d has the function of the control information table 11c of the control information table 11b of the bus bridge 10b among second embodiment and the bus bridge 10c among the 3rd embodiment.
Figure 12 shows the example as the structure of the control information table 11d among the bus bridge 10d of fourth embodiment of the invention.
As shown in figure 12, control information table 11d comprises eight clauses and subclauses.Each clauses and subclauses comprises as the serial ID of control information and corresponding generation each other, storage address, write data buffer pointer value or read data pointer value (WD/RD buffer pointer value; Stored position information) and identification bit (identifying information).
The identification bit is that the transaction that is used to distinguish relevant is about read request (reading to handle) or about the identifying information of write request (writing processing).For example, will be registered as " 1 " about the transaction of read request; And will be registered as " 0 " about the transaction of write request.
In other words, control information table 11d manages at least and asks relevant serial ID, about in the write data buffer 13 with the stored position information of memory location of the corresponding write data of request, perhaps about in the read data 12 with the stored position information of memory location of the corresponding read data of request, and be associated with therebetween identification bit.
Figure 13 shows the data stream when transmission read data and write data in as the bus bridge 10d of fourth embodiment of the invention.Figure 13 show in the bus bridge 10b of second embodiment, transmit read data (with reference to figure 7) and in the bus bridge 10c of the 3rd embodiment, transmit write data (with reference to figure 9) the two in conjunction with the time data stream.
In the bus bridge 10d of the 4th embodiment, will write I/O reception buffer 15 from the bag that I/O bus 31 receives; And receive data processor 17 and extract the bag that writes the I/O reception buffer.
Herein, when the bag that extracts is read request, receives data processor 17 header is divided into 128 bytes respectively, and the data length of read data is carried out stored counts.
According to the stored counts that receives data processor 17, control assembly 16 is registered the pointer value of pointing to storage area and as other necessary informations of control information in control information table 11d, wherein this storage area is according to the read data length in the clauses and subclauses of being represented by the serial ID among the control information table 11d, guarantees in advance in read data 12; And, with the identification bit " 1 " of registration expression transaction for reading when serial ID is related.
On the other hand, when the bag that extracts is write request, receives data processor 17 header is divided into 128 bytes respectively, the data length of write data is carried out stored counts, and in write data buffer 13, store data division (write data).
According to the stored counts that receives data processor 17, in the clauses and subclauses that control assembly 16 is represented by serial ID in control information table 11d, registration pointer value (it points to the write data memory location in write data buffer 13), and as other necessary informations of control information.At this moment, control assembly 16 is the identification bit " 0 " that writes according to serial ID registration expression transaction.
In bus bridge 10d as fourth embodiment of the invention, control assembly 16 obtains serial ID from the read data that memory bus 30 receives or in the header of data transmission permission/data retransmission requests, according to serial ID inquiry control information table 11, and according to the identification bit decision processing relevant with serial ID is processing or the processing about writing about reading.
When the processing relevant with serial ID is during about the processing of reading, handle according to flow performing shown in Figure 7.And when the processing relevant with serial ID be during about the processing that writes, then handle according to flow performing shown in Figure 9.
As mentioned above, according to bus bridge 10d, can obtain the work effect identical with first to the 3rd above-mentioned embodiment as fourth embodiment of the invention.In addition, also can obtain following work effect.That is, in the transaction of reading and writing, can shared control information table 11d; Thereby, can reduce circuit scale, installing space etc.
(E) other
The present invention is not limited to the foregoing description; But can in the scope of spirit of the present invention, carry out various modifications.
For example, in the various embodiments described above, each control information table 11a, 11b, 11c and 11d comprise eight clauses and subclauses.Yet the present invention is not limited to this.The control information table can comprise seven or still less or nine or more clauses and subclauses.
In addition, in the above-described embodiments, the example of embodiments of the invention is provided, has been provided with among bus bridge 10a, 10b, 10c and the 10d two comprising the signal conditioning package 1 that has two CPU21-1 and 21-2, two system controller 23-1 and 23-2, four storer 22-1 to 22-4 and four I/O devices 25.Yet the present invention is not limited to foregoing.The present invention can comprise CPU21, system controller 23, storer 22, I/O device 25 and bus bridge 10a, 10b, 10c, the 10d beyond the above-mentioned quantity.Can in the scope of spirit of the present invention, carry out various modifications and realize the present invention.
When disclosing embodiments of the invention, those skilled in the art can realize and make the present invention.
The present invention can be applicable in the data transmission that has each other between two buses of different agreements.
Claims (6)
1. data transmission device, be used between memory bus (30) and input/output bus (31), transmitting data, wherein connect this memory bus (30) by this way, make its can with request signal line (30c) is equipped with, to ask in the communicating by letter of the storer of write data signal line (30b) and reading data signal line (30a), write data and read data transmit as bag respectively, described input/output bus (31) is equipped with and sends signal wire (31b) and received signal line (31a), to send data respectively and receive that data send to input/output device as bag that comprises the transmission address that sends data and these transmissions data and the bag that comprises the receiver address that receives data and these reception data or from this input/output device reception, described data transmission device comprises by described transmission signal wire (31b) and received signal line (31a):
I/O reception buffer (15), it can store the reception data that receive from this input/output device by this received signal line (31a);
I/O transmission buffer (14), it can store the transmission data that send to this input/output device by this transmission signal wire (31b);
Write data buffer (13), it can store the write data for the treatment of to send to by this write data signal line (30b) this storer;
Read data (12), it can store the read data that receives from this storer by this reading data signal line (30a);
The control information table, it has corresponding to the access of this storer and a plurality of clauses and subclauses that form;
Write data buffer stores processor parts (17), it will be stored in reception data storage in this I/O reception buffer (15) in this write data buffer (13);
Write data transmit block (34), it is by this write data signal line (30b), and the reception data that will be stored in this write data buffer (13) send to this storer as write data;
Read data stores processor parts (33), it will be stored in this read data (12) from the read data that this storer receives;
I/O transmission buffer stores processor parts (18), it reads the read data that is stored in this read data (12), and with these data as sending data, be stored in this I/O transmission buffer (14) with the transmission address of these transmission data; And
Control assembly (16), the access that it is carried out this storer by this write data transmit block (34) and this read data memory unit (33) according to this control information table control.
2. data transmission device as claimed in claim 1, wherein,
When writing processing with from this input/output device during to these memory transfer data,
This write data transmit block (34) sends write data by this write data signal line (30b), and write data are to be divided into the storage access capacity and to form by being stored in reception data in this write data buffer (13).
3. data transmission device as claimed in claim 2, wherein
This control information table is set up corresponding relation at the serial ID relevant with request with in this write data buffer (13) between the stored position information of storage corresponding to the write data of this request at least, and it is managed,
When this memory bus (30) sends data, this control assembly (16) utilizes this serial ID to read the stored position information of writing the clauses and subclauses of this control information table from write data impact damper (13) as pointer, and extracts write data according to this stored position information from this write data buffer (13).
4. as any one the described data transmission device in the claim 1 to 3, wherein
When reading to handle with from this storer during to these input/output device transmission data,
When the total amount of data of a plurality of read datas in being stored in this read data (12) satisfies the condition that sends the bag size, these I/O transmission buffer stores processor parts (18) are read the read data that is stored in this read data (12), and with these data as sending data, be stored in this I/O transmission buffer (14) with the transmission address of these transmission data.
5. data transmission device as claimed in claim 4, wherein
This control information table is at least with relevant this serial ID of request with about setting up corresponding relation between the stored position information corresponding to the memory location of the read data of this request in this read data (12), and it is managed,
When from this memory bus (30) reception read data, this control assembly (16) utilizes this serial ID to read the stored position information of writing the clauses and subclauses of this control information table from described read data (12) as pointer, and according to this stored position information this read data is stored in this read data (12).
6. data transmission device as claimed in claim 5, wherein this control information table is stored the stored position information of described read data (12) and the stored position information of write data impact damper (13) in same field, and storage is used for writing the identifying information of handling and reading to handle corresponding to this request difference.
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| JP6992295B2 (en) * | 2017-07-11 | 2022-01-13 | 富士フイルムビジネスイノベーション株式会社 | Electronic device |
| JP7012520B2 (en) * | 2017-11-29 | 2022-01-28 | ラピスセミコンダクタ株式会社 | Data writing method and storage device |
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