CN100471271C - Image processing architecture - Google Patents
Image processing architecture Download PDFInfo
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- CN100471271C CN100471271C CN 200510113459 CN200510113459A CN100471271C CN 100471271 C CN100471271 C CN 100471271C CN 200510113459 CN200510113459 CN 200510113459 CN 200510113459 A CN200510113459 A CN 200510113459A CN 100471271 C CN100471271 C CN 100471271C
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Abstract
The invention is a video processing structure, at least comprising plural buses, plural codecs and plural independent memories, where these buses provide different access paths, the video data before and after compression are stored into or drawn from different memories through these different access paths, and these codecs can process video data of the same video source at the same time.
Description
Technical field
The invention relates to a kind of image processing architecture, and particularly relevant with a kind of framework that can carry out image processing fast.
Background technology
Image is transmitted in the epoch that present network popularizes and becomes more and more important, yet image is the storage volume and the transfer resource of consumption calculations machine completely, especially in the transmission of network, big image data needs a large amount of time to carry out the image transmission, and has often taken a large amount of network bandwidth resources.Therefore the technology that must pressuredly contract is compressed these data fast and significantly.Chang Yong compress technique has JPEG, GIF, half-tone or the like aspect static image traditionally, and then there are MPEG-2, MPEG-4, WMV or the like in the dynamic image aspect.
Consult and Figure 1 shows that the system architecture diagram that carries out the image transmission traditionally and receiving when.Be connected with a network 110 by network controller 104.And when carrying out image when transmission, at first by image capture unit 101 picture 102 capture, be sent to after image volumes/decoder 107 makees image and compress processing by bus 100 again, then deposit to internal memory 108 by Memory Controller Hub 106 by bus 100 once more.Give an order by central processing unit 103 at last compression image is later gone out via the Network Transmission that is connected.
And when carrying out the image reception, the image data that transmits by the network receiving remote at first, and via after 107 decodings of image volume/decoder, temporary to internal memory 108 by bus 100 by Memory Controller Hub 106, read and be presented at LCD screen 109 by display controller 105 at last.
Yet the transmission of traditional image suffers from following problem with reception processing procedure regular meeting.For example only use single volume/decoder traditionally, can't resolve image data to height and do real-time volume/decoding.And the image data behind volume/decoding of volume/decoder or coding and other data of system are shared a memory device, and regular meeting causes whole system usefulness variation because of the memory access frequency range is not enough.On the other hand, all aforementioned components and other perimeter component only depend on unified bus to transmit, and also restriction can be for the frequency range of image transmission indirectly.Fluency when above-mentioned shortcoming regular meeting causes transmission or show image.
Therefore, be badly in need of having a kind of high resolution image processing framework that can address the above problem and can handle.
Summary of the invention
Therefore, main purpose of the present invention is providing a kind of image processing architecture exactly, in order to solve the problem of frequency range deficiency.
Another object of the present invention is that a kind of image processing architecture that can in time encode and decipher is being provided.
A further object of the present invention is that a kind of framework that can carry out image processing fast is being provided.
According to a first aspect of the invention, provide a kind of image processing architecture, comprised at least: three-bus at least, in order to different access paths to be provided; At least two volume/decoders couple these buses, in order to raw video data are encoded or the image data behind the coding is deciphered; And at least two internal memories, be respectively first and second internal memory, coupling bus, the wherein first memory storage raw video data and decoding back image data, and the image data behind second memory storage coding.
According to a second aspect of the invention, provide a kind of image processing system, in order to first image data is converted to one second image data, this image processing system comprises at least: a processor; One first code device; One second code device; One first storage device; One second storage device; One first bus is connected in described processor, first code device, second code device, first storage device and second storage device; One second bus is connected in described processor, first code device, second code device and first storage device; And one the 3rd bus, be connected in described first code device, second code device, first storage device and second storage device; Wherein, described processor is stored to first image data in first storage device via first bus, first code device and second code device are encoded to second image data via second bus with first image data, and processor is stored in second image data in second storage device via the 3rd bus.
According to a third aspect of the present invention, provide a kind of image processing system, in order to first image data is converted to one second image data, this image processing system comprises at least: a processor; One first code translator; One second code translator; One first storage device; One second storage device; One first bus is connected in described processor, first code translator, second code translator, first storage device and second storage device; One second bus is connected in described processor, first code translator, second code translator and first storage device; And one the 3rd bus, be connected in described first code translator, second code translator, first storage device and second storage device; Wherein, described processor is stored to first image data in second storage device via first bus, first code translator and second code translator are decoded as second image data via the 3rd bus with first image data, and processor is stored to second image data in first storage device via second bus.
According to above-mentioned purpose, image processing architecture of the present invention comprises a plurality of buses, a plurality of volume/decoder and a plurality of independent memory.Wherein, provide different access paths, make that the image data before and after the compression is deposited in the different internal memories via different access paths respectively, avoid because of the conflict of image data access path by a plurality of buses, and the lag when causing image to play.And the image data of same picture can be divided into several parts, and transfers to different volume/decoders respectively and handle simultaneously, bears so as to the processing that reduces indivedual volume/decoders, and increases image processing speed.
Description of drawings
Figure 1 shows that the system architecture diagram that carries out the image transmission traditionally and receiving when.
Figure 2 shows that image processing architecture schematic diagram of the present invention.
Fig. 3 A is depicted as and utilizes a preferred embodiment of the present invention to carry out the schematic diagram of image compression coding.
Fig. 3 B is depicted as and utilizes a preferred embodiment of the present invention to carry out the schematic diagram that image decompresses and deciphers.Description of reference numerals
100,200a, 200b, 200c, 300a, 300b and 300c bus
101,201 and 301 image capture units
102,202 and 302 computer pictures
104,204 and 304 network controllers
105,205 and 305 display controllers
106,206a, 206b, 306a and 306b Memory Controller Hub
107,307a and 307b image volume/decoder
108,208a and 208b internal memory
The 308a main storage
308b image internal memory
109,209 and 309 LCD screen
110,210,310 networks
Embodiment
Consult and Figure 2 shows that image processing architecture of the present invention.According to framework of the present invention, for the requirement that solves frequency range and carry out coding and decoding in real time, therefore adopt at least three buses, be respectively the first bus 200a, the second bus 200b and the 3rd bus 200c connect the assembly in this framework, and a plurality of volume/decoders, be respectively first to N volume/decoder, carry out the coding and the decoding of image, cooperate plural at least controller (for example first Memory Controller Hub 206a and the second Memory Controller Hub 206b) to control at least two storage devices (for example first internal memory 208a and the second internal memory 208b) simultaneously, to store image data and other data respectively.So as to the frequency range deficiency under the solution conventional architectures and the problem of bus collision, so that accelerate image processing (coding or decoding) speed.In addition, image processing architecture of the present invention can pass through a network controller 204 (a for example Ethernet controller) and is connected with a network 210.And the computer picture 202 that image capture unit 201 is desired to handle in order to acquisition.Central processing unit 203 is in order to the transmission and the reception of control image.Display controller 205 (a for example LCD controller) then is presented at display for example on the LCD screen 209 in order to the control image.
Consult Fig. 3 A and be depicted as the embodiment that according to the present invention image processing architecture carries out image compression coding.Image processing architecture in the present embodiment comprises: three bus 300a, 300b and 300c connect perimeter component, two volume/decoder 307a and 307b carry out the coding and the decoding of image, cooperate two (first and second) Memory Controller Hub 306a and 306b to control internal memory 308a and 308b simultaneously, to store the image data after other data and volume/decoder 307a and the 307b volume/decoding respectively.Wherein internal memory 308a is coupled to bus 300a and 300b by the first Memory Controller Hub 306a, and internal memory 308b then is coupled to bus 300a and 300c by the second Memory Controller Hub 306b.
According to present embodiment, when carrying out the image compression coding processing, the image archives that come via Network Transmission, or via image capture unit 301 (being to be connected to bus 300a and 300b in the present embodiment) from an image person (a for example computer screen 302) institute's picked image archives, via path 1, by bus 300b, these image archives are temporary to main storage 308a by the first Memory Controller Hub 306a.
Then, volume/decoder 307a and 307b can follow path 2,, handle to carry out image compression coding by taking out stored pending image archives among the main storage 308a via bus 300b.Because the compressed encoding that the present invention adopts two volume/decoder 307a and 307b to carry out image is simultaneously handled, therefore can promote the speed of image processing.Its processing method for example, can become two parts with same picture segmentation, respectively its corresponding image data is transferred to volume/decoder 307a and 307b handles simultaneously.
And the image data after the compressed encoding process can be followed path 3, and via bus 300c, the image archives after by the second Memory Controller Hub 306b this being handled are stored among the image internal memory 308b.Because the image archives after the present invention handles are stored among the image internal memory 308b in addition, are not to be stored among the main storage 308a, therefore can avoid clashing with the path of accessing main memory 308a.And in the compressed encoding processing procedure, can promptly follow path 4, come to compare the function of reaching dynamic comparation and assessment (Motion Estimation) with the last image data that is stored among the image internal memory 308b via bus 300c.Give an order by central processing unit 303 at last,, follow path 5, be sent to the network controller 304 that is coupled to bus 300a, to be uploaded to network 310 with there being compression image data later in the image internal memory 308b.
Consult Fig. 3 B and be depicted as the embodiment that image processing architecture carries out image decompression decoding according to the present invention.According to present embodiment, when carrying out image decompression decoding processing, compressed image data later via network 310 by network controller 304 transmission, meeting is via path 1, be bus 300a, deposit among the image internal memory 308b by the second Memory Controller Hub 306b.
Then, volume/decoder 307a and 307b can follow path 2,, handle to carry out image decompression decoding by taking out stored image data to be decoded among the image internal memory 308b via bus 300c.Similar, because the decompression decoding that the present invention adopts two volume/decoder 307a and 307b to carry out image is simultaneously handled, therefore can promote the speed of image processing.
And the image data after the decoding that decompresses is handled can be followed path 3, and via bus 300b, the image archives after by the first Memory Controller Hub 306a this being handled are stored among the main storage 308a.Give an order by central processing unit 303 at last, with the image data that exists after decompressing in the main storage 308a, follow path 4, promptly send the LCD controller 305 that is coupled to bus 300a and 300b to, and export LCD screen 309 to via bus 300b.
Because the image archives after decompressing are stored among the main storage 308a, and the image archives after the compression are stored among the image internal memory 308b.In other words, when the image after decompressing showed, image data was to grasp from main storage 308a, i.e. path 4 (bus 300b) among Fig. 3 b.Therefore can't compress the access path of back image data with access, promptly the path 3 (bus 300c) among Fig. 3 A clashes, the fluency in the time of also can keeping image to broadcast.
It should be noted that, the above only is a preferred embodiment of the present invention, in other embodiments, each perimeter component, for example Memory Controller Hub, image capture unit, network controller etc. are not limited to only can be coupled to aforesaid specific bus, in other words, can be according to different design architectures, change and bus between the relation that couples.In addition, for accelerating image processing speed, also can same picture segmentation be become several parts by increasing the number of volume/decoder, and respectively the corresponding image data are transferred to different volume/decoders and handle simultaneously, reduce the processing burden of indivedual volume/decoders.
Say that to sum up image processing architecture of the present invention comprises a plurality of buses, a plurality of volume/decoder and a plurality of independent memory.According to framework of the present invention, the image data of same picture can be divided into several parts, and transfers to different volume/decoders respectively and handle simultaneously, so as to reducing the processing burden of indivedual volume/decoders, and increase image processing speed, reach the purpose that can handle in real time.And on the other hand, utilize a plurality of buses and a plurality of independent memory, allow the image data of compression front and back deposit in the different internal memories via different access paths respectively, therefore, can avoid because of the conflict of image data access path, and the lag when causing image to play, also can stagger volumes/decoder and central processing unit while access conflict the increase processing speed.
Though the present invention with a preferred embodiment openly as above, right its is not in order to limit the present invention, anyly be familiar with this operator, without departing from the spirit and scope of the present invention, when doing various changes and modification, for example in the present invention, the transmission end of image can not used volume/decoder and only used encoder, and receiving terminal can only use decoder.Therefore protection scope of the present invention should be with being as the criterion that claims were defined.
Claims (16)
1. image processing architecture comprises at least:
At least three-bus is in order to provide different access paths;
At least two volume/decoders couple these buses, in order to raw video data are encoded or the image data behind the coding is deciphered; And
At least two internal memories are respectively first and second internal memory, coupling bus, the wherein first memory storage raw video data and decoding back image data, and the image data behind second memory storage coding.
2. framework as claimed in claim 1 is characterized in that, described raw video data and decoding back image data follow same bus to be stored in first internal memory.
3. framework as claimed in claim 1 is characterized in that, the image data behind image data after the described decoding and the coding follows different bus to be stored to respectively in first and second internal memory.
4. framework as claimed in claim 1 is characterized in that, comprises that also two Memory Controller Hub control above-mentioned at least two internal memories respectively.
5. framework as claimed in claim 1 is characterized in that, also comprises a network controller, the coupling bus, in order to connecting a network, in order to upload or received code after image data.
6. framework as claimed in claim 5 is characterized in that, described upload or received code after image data follow same bus to carry out.
7. framework as claimed in claim 1 is characterized in that, also comprises an image capture unit, and the coupling bus is in order to capture an image data and it is stored in first internal memory.
8. framework as claimed in claim 1 is characterized in that, also comprises a display controller, and the coupling bus is in order to take out the image data after deciphering from first internal memory.
9. framework as claimed in claim 1 is characterized in that, the image data after the described decoding follows different buses to be stored in first internal memory, or takes out from first internal memory.
10. image processing system, in order to first image data is converted to one second image data, this image processing system comprises at least:
One processor;
One first code device;
One second code device;
One first storage device;
One second storage device;
One first bus is connected in described processor, first code device, second code device, first storage device and second storage device;
One second bus is connected in described processor, first code device, second code device and first storage device; And
One the 3rd bus is connected in described first code device, second code device, first storage device and second storage device;
Wherein, described processor is stored to first image data in first storage device via first bus, first code device and second code device are encoded to second image data via second bus with first image data, and processor is stored in second image data in second storage device via the 3rd bus.
11. image processing system as claimed in claim 10 is characterized in that, also comprises a network controller, wherein this processor transfers to this network controller via first bus with second image data.
12. image processing system as claimed in claim 10 is characterized in that, also comprises:
One first controller is in order to control above-mentioned first storage device; And
One second controller is in order to control above-mentioned second storage device.
13. image processing system as claimed in claim 10 is characterized in that, also comprises an image capture unit, in order to capture above-mentioned first image data.
14. an image processing system, in order to first image data is converted to one second image data, this image processing system comprises at least:
One processor;
One first code translator;
One second code translator;
One first storage device;
One second storage device;
One first bus is connected in described processor, first code translator, second code translator, first storage device and second storage device;
One second bus is connected in described processor, first code translator, second code translator and first storage device; And
One the 3rd bus is connected in described first code translator, second code translator, first storage device and second storage device;
Wherein, described processor is stored to first image data in second storage device via first bus, first code translator and second code translator are decoded as second image data via the 3rd bus with first image data, and processor is stored to second image data in first storage device via second bus.
15. image processing system as claimed in claim 14 is characterized in that, also comprises a network controller, this network controller is obtained above-mentioned first image data by a network.
16. image processing system as claimed in claim 14 is characterized in that, also comprises:
One first controller is in order to control above-mentioned first storage device; And
One second controller is in order to control above-mentioned second storage device.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200510113459 CN100471271C (en) | 2005-10-13 | 2005-10-13 | Image processing architecture |
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200510113459 CN100471271C (en) | 2005-10-13 | 2005-10-13 | Image processing architecture |
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| CN1949874A CN1949874A (en) | 2007-04-18 |
| CN100471271C true CN100471271C (en) | 2009-03-18 |
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| CN 200510113459 Expired - Fee Related CN100471271C (en) | 2005-10-13 | 2005-10-13 | Image processing architecture |
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