CN100428631C - Method for reducing analog-digital converter capacitance mismatch error based on capacitance match - Google Patents

Abstract

The present invention relates to a method for reducing an analog-digital converter capacitance mismatch error based on capacitance match. The present invention belongs to the technical field of integrated circuit design. Firstly, in the four work capacitors defining a medium circuit of an analog-digital converter, two top plates of the capacitors C< 1 > and C< 2 > are together connected to the positive input end of an operational amplifier, and two top plates of the capacitors C< 3 > and C< 4 > are together connected to the negative input end of the operational amplifier, wherein C< 1 > and C< 3 > are a first pair of difference work capacitor; C< 2 > and C< 4 > are a second pair of difference work capacitor, and the two pairs of difference work capacitors are respectively a difference sampling capacitor or a difference feedback capacitor of a grade circuit. The size of the four work capacitors are compared, so that two pairs of new difference work capacitors are formed, and the pair of difference work capacitors with the minor sum of capacitance values are used as the difference feedback capacitors of the grade circuit. The method has the advantages that the power consumption of the circuit is not increased, and the work speed of the analog-digital converter is not reduced. After capacitance match is finished, periodic repeating measurement and calibration do not need.

Description

A kind of method of the reduction analog to digital converter capacitance mismatch error based on capacitance pairing

Technical field

The present invention relates to a kind of method of the reduction analog to digital converter capacitance mismatch error based on capacitance pairing, be particularly related to a kind of by electric capacity being selected pairing reduce the capacitance mismatch error, thereby improve the method for precision of A/D converter, belong to the integrated circuit (IC) design technical field.

Background technology

In streamline and circulating analog to digital converter (hereinafter to be referred as ADC) based on switched capacitor technique, the switched capacitor stage circuit is a basic component units, and it has determined the performance of whole ADC to the performance of signal processing.Typical switched capacitor stage circuit is generally two-phase work, i.e. sampling mutually and amplification mutually.Fig. 1 has provided the operation principle of typical 1.5 level circuit, and wherein, Fig. 1 (a) has provided the circuit of level circuit in sampling mutually and linked situation, and Fig. 1 (b) has provided the circuit of level circuit in amplifying mutually and linked situation.Contrast Fig. 1, the course of work of level circuit can specifically describe and be: in the sampling phase, differential capacitance is to (C ₁, C ₃) and (C ₂, C ₄) base plate all be connected to differential input signal (V _Ip, V _In), and top board all is connected to the differential input end of operational transconductance amplifier OP, and simultaneously, the differential input end of OP interconnects, difference output end also interconnects, and promptly this moment, it was in reset mode, under this circuit connection state, (C ₁, C ₃) and (C ₂, C ₄) on differential voltage follow the tracks of (V _Ip, V _In) variation, in sampling phase finish time, the differential input end of OP disconnects mutually, difference output end disconnects (C mutually ₁, C ₃) and (C ₂, C ₄) base plate and (V _Ip, V _In) also disconnect (C ₁, C ₃) and (C ₂, C ₄) finish (V _Ip, V _In) sampling, simultaneously, 1.5 analog to digital conversion circuit U1 are to this (V constantly _Ip, V _In) carry out analog-to-digital conversion, obtain b1b0 as a result; Amplifying phase, (C ₁, C ₃) base plate at b ₁b ₀Control under switch to differential reference voltage (V _Rp, V _Rn), (V _Rn, V _Rp) or two capacitor bottom plate directly connect (C ₂, C ₄) base plate switch to the difference output end of OP, at this moment, C ₁～C ₄The electric charge that constitutes a fully differential with OP shifts amplifier circuit, wherein, and (C ₂, C ₄) as the difference feedback capacitance of circuit, relatively claim (C ₁, C ₃) be the difference sampling capacitance.This amplifier circuit is by (C ₁, C ₃) and (C ₂, C ₄) between electric charge shift finally to finish the input signal of being sampled amplified and result amplified and reference signal are carried out the function of subtraction, the difference output (V of amplifier circuit _Op, V _On) i.e. the output of conduct grade circuit.

In the course of work of aforementioned level circuit, if (C in will amplifying mutually ₁, C ₃) the differential voltage that base plate connect with D (V _Rp-V _Rn) represent (V then _Ip, V _In) and b ₁b ₀As shown in table 1 with the relation of D:

Table 1

In ideal conditions, the DC current gain of establishing OP is unlimited, i.e. A ₀Trend towards ∞, and electric capacity there is not mismatch, i.e. C ₁=C ₂=C ₃=C ₄, then desirable level circuit output voltage is:

V _o＝V _op-V _on＝2(V _ip-V _in)-D(V _rp-V _in) (1)

In actual chips, the DC current gain of OP can not accomplish infinitely, and, owing to make C ₁～C ₄Between can have certain mismatch, therefore, an actual level circuit output voltage is:

$V_o=V_{\mathrm{op}}-V_{\mathrm{on}}$

$=\frac{(2+{\mathrm{\&epsiv;}}_1)(V_{\mathrm{ip}}-V_{\mathrm{in}})-(1+{\mathrm{\&epsiv;}}_1)D(V_{\mathrm{rp}}-V_{\mathrm{rn}})}{1+\frac{2+\mathrm{\&beta;}}{A_0}}+\mathrm{\&Delta;}{V}_o---\left(2\right)$

Wherein,

β is defined as the input parasitic capacitance of amplifier OP and mutual capacitance (as C ₁) ratio, its value is generally less than 1;

ε ₁Be defined as the level circuit gain error that capacitance mismatch brings, its value is:

${\mathrm{\&epsiv;}}_1=\frac{(C_1+C_3)-(C_2+C_4)}{C_1+C_3}---\left(3\right)$

Δ V _oThe error that other non-ideal factors cause in the indication circuit and, these non-ideal factors comprise operational amplifier offset, the electric charge of switch injects and clock feed-through effect, and the high-order term of capacitance mismatch etc., wherein, operational amplifier offset only brings DC deviation to ADC, and can not destroy its linearity.

By the aforementioned formula of formula (2) as can be known, the error of level circuit is made of the error that amplifier finite gain error, other non-ideal factors of capacitance mismatch sum of errors bring.For realizing the high accuracy design, must take certain measure to reduce these errors.For amplifier finite gain error, generally can solve, as adopting cascade technology, gain bootstrap technology, multilevel hierarchy etc. by the method that improves the amplifier gain; The error of bringing for other non-ideal factors, it mainly injects relevant with clock feed-through effect with the electric charge of switch, can reduce by base plate Sampling techniques and fully differential structure, in the ADC that surpasses 12 designs, also can introduce the clock voltage bootstrap technique and come the conducting resistance of linearisation input switch to inject error further to reduce electric charge; For the capacitance mismatch error, existing calibration steps mainly is to adopt error self calibration technology, perhaps adopts the capacitance error averaging.

With respect to other two errors, the processing of capacitance mismatch error is difficulty comparatively, and also there is shortcoming separately in existing calibration steps.For example, for error self calibration technology, its shortcoming is to need to increase complicated capacitance error usually to measure and calibration circuit, and, in order to resist the influence that operational environment changes, need carry out periodic duplicate measurements and calibration, this can influence the continuity of circuit operate as normal, or further increases the complexity of self-calibration circuit; And for example, for the capacitance error averaging, its shortcoming is all to need 2 samplings and amplifieroperation for conversion each time, therefore will be slower than the 2 typical grade circuit of working mutually on conversion speed.

Summary of the invention

The objective of the invention is to propose a kind of method of the reduction analog to digital converter capacitance mismatch error based on capacitance pairing, it depends on the principle of the mismatch between two feedback capacity sums and two the sampling capacitance sums based on the capacitance mismatch error of differential levels circuit, the employing simple processing of circuit technology of trying one's best, 4 mutual capacitances in the level circuit are compared pairing, thereby form difference sampling capacitance and difference feedback capacitance selectively, to reduce the capacitance mismatch error of grade circuit, optimize the conversion accuracy of ADC.

The method that the present invention proposes based on the reduction analog to digital converter capacitance mismatch error of capacitance pairing, this method may further comprise the steps:

(1) in 4 mutual capacitances of definition analog to digital converter middle rank circuit, the electric capacity that two top boards are connected to the operational amplifier positive input terminal jointly is C ₁And C ₂, the electric capacity that two top boards are connected to the operational amplifier negative input end jointly is C ₃And C ₄, C wherein ₁And C ₃Be first pair of difference mutual capacitance, C ₂And C ₄Be second pair of difference mutual capacitance, these two pairs of difference mutual capacitances are respectively the difference sampling capacitance or the difference feedback capacitance of grade circuit;

(2) if size of more above-mentioned four mutual capacitances is (C ₁+ C ₃)-(C ₂+ C ₄) absolute value greater than (C ₁+ C ₄)-(C ₂+ C ₃) absolute value, then make C ₁And C ₄Pairing becomes first pair of difference mutual capacitance, C ₂And C ₃Pairing becomes second pair of difference mutual capacitance, if (C ₁+ C ₃)-(C ₂+ C ₄) absolute value less than (C ₁+ C ₄)-(C ₂+ C ₃) absolute value, then keep C ₁And C ₃Be first pair of difference mutual capacitance, C ₂And C ₄Be second pair of difference mutual capacitance;

(3) the capacitance sum of first pair of difference mutual capacitance of above-mentioned steps (2) and the capacitance sum of second pair of difference mutual capacitance are compared, and a pair of difference mutual capacitance that the capacitance sum is less is as the difference feedback capacitance of level circuit, and another is to the difference sampling capacitance as the level circuit.

The method that the present invention proposes based on the reduction analog to digital converter capacitance mismatch error of capacitance pairing, mainly aforementioned typical grade circuit has been carried out the improvement of two aspects, first, make the mutual capacitance in the circuit commutative, the mutual capacitance that promptly is used as sampling capacitance originally can be adjusted to feedback capacity, and vice versa; The second, pairing is selected in mutual capacitance, make grade circuit gain error less.After electric capacity was selected pairing, a level circuit can begin operate as normal, and its course of work is the same with the course of work of aforementioned typical grade circuit.By the probability distribution analysis as can be known, to reach identical chip yield is standard, the effect of method proposed by the invention be equivalent to the matching precision of electric capacity is brought up to original more than 1.54 times, also be about to precision and improved about 0.62, moreover, because method proposed by the invention has been considered the selection to difference feedback capacitance simultaneously, the level circuit gain error that makes capacitance mismatch and amplifier finite gain be brought weakens mutually, can further improve the precision of grade circuit.Compare with existing capacitance error calibration steps, the advantage of method proposed by the invention is:

1, do not increase circuit power consumption, do not reduce the operating rate of circuit, this method only needs aforementioned typical grade circuit is increased the commutative required switch control of realization electric capacity, and does not increase the active device that power consumption is arranged, and does not also change its course of work.

2, be the calibration steps of a kind of essence linear (Inherently Linear), in case finish capacitance pairing, the calibration effect of capacitance error is insensitive to the variation of chip operation environment, thereby does not need periodic duplicate measurements and calibration.

3, the improvement design of level circuit is comparatively simple, and the realization of the circuit of calibration algorithm is also comparatively simple, and this can be illustrated by a specific embodiment of the present invention.

Description of drawings

Fig. 1 is the operation principle of existing typical 1.5 level circuit.

Fig. 2 is tradable 1.5 the level circuit of electric capacity that the present invention proposes.

Fig. 3 is that the level circuit capacitance that the present invention proposes is selected the pairing algorithm.

Fig. 4 is the realization capacitance size circuit theory relatively that the present invention proposes.

Embodiment

The method based on the reduction analog to digital converter capacitance mismatch error of capacitance pairing that the present invention proposes comprises: in 4 mutual capacitances of definition analog to digital converter middle rank circuit, the electric capacity that two top boards are connected to the operational amplifier positive input terminal jointly is C ₁And C ₂, the electric capacity that two top boards are connected to the operational amplifier negative input end jointly is C ₃And C ₄, C wherein ₁And C ₃Be first pair of difference mutual capacitance, C ₂And C ₄Be second pair of difference mutual capacitance, these two pairs of difference mutual capacitances are respectively the difference sampling capacitance or the difference feedback capacitance of grade circuit; If the size of more above-mentioned four mutual capacitances is (C ₁+ C ₃)-(C ₂+ C ₄) absolute value greater than (C ₁+ C ₄)-(C ₂+ C ₃) absolute value, then make C ₁And C ₄Pairing becomes first pair of difference mutual capacitance, C ₂And C ₃Pairing becomes second pair of difference mutual capacitance, if (C ₁+ C ₃)-(C ₂+ C ₄) absolute value less than (C ₁+ C ₄)-(C ₂+ C ₃) absolute value, then keep C ₁And C ₃Be first pair of difference mutual capacitance, C ₂And C ₄Be second pair of difference mutual capacitance; The capacitance sum of first pair of difference mutual capacitance of above-mentioned steps and the capacitance sum of second pair of difference mutual capacitance are compared, and a pair of difference mutual capacitance that the capacitance sum is less is as the difference feedback capacitance of level circuit, and another is to the difference sampling capacitance as the level circuit.

The key of the inventive method is: the tradable level of design work electric capacity circuit; The selection pairing algorithm and the circuit of electric capacity.Below further introduce the content of the inventive method:

The execution mode of the commutative level of electric capacity circuit:

Fig. 2 has provided a design example of the commutative level of electric capacity circuit.Wherein, top is divided into the circuit of " sampling maintenance/digital-to-analogue conversion/analog subtraction/amplification " module (being designated hereinafter simply as MDAC) of grade circuit, and the bottom is divided into analog-to-digital conversion and switch controlling signal combiner circuit.In the MDAC circuit, C ₁～C ₄Be 4 mutual capacitances, OP is the fully differential spaning waveguide operational amplifier with imbalance self-calibration function, (V _Ip, V _In) be the differential input signal of level circuit, (V _Op, V _On) be the differential output signal of level circuit, (V _Rp, V _Rn) be the difference reference signal, V _CmBe the common-mode reference signal of difference input, 1 and 2 are the two-phase clock signal that do not overlap, respectively the controlled stage circuit working in sampling mutually and amplification mutually, 2a, Xa, Ya, Za, 2b, Xb, Yb, Zb, 2c, Xc, Yc, Zc, 2d, Xd, Yd, Zd are switch controlling signal, are produced by analog-to-digital conversion and switch controlling signal combiner circuit.C ₁And C ₂Top board links together, and is connected to the negative input end of OP, and their base plate is separately by 5 switches and signal V _Ip, V _Op, V _Rp, V _Rn, V _CmLink to each other, by adjust switch controlling signal (2a, Xa, Ya, Za) and (2b, Xb, Yb, logical relation Zb) can realize the exchange between them; Similarly, C ₃And C ₄Top board link together, and be connected to the positive input terminal of OP, and base plate is separately by 5 switches and signal V _In, V _On, V _Rp, V _Rn, V _CmLink to each other, by adjust switch controlling signal (2c, Xc, Yc, Zc) and (2d, Xd, Yd, logical relation Zd) can realize the exchange between them.

In analog-to-digital conversion and switch controlling signal combiner circuit, U1 is 1.5 analog to digital conversion circuits in the level circuit, and U2 is the logical circuit of synthesising switch control clock, d ₁d ₀Select the output result of pairing process for electric capacity.The function of U1 is the trailing edge at clock 1, and the phase of promptly sampling finish time is to (V _Ip, V _In) carry out 1.5 analog-to-digital conversion, and output transformation result b ₁b ₀, b ₁b ₀With (V _Ip, V _In) relation be the same with corresponding relation in the aforementioned typical level circuit, as shown in table 1.The function of U2 is with b ₁b ₀And d ₁d ₀Translate into switch controlling signal 2a, Xa, Ya, Za, 2b, Xb, Yb, Zb, 2c, Xc, Yc, Zc, 2d, Xd, Yd, Zd decides the annexation of base plate in amplifying mutually of each electric capacity by them.Wherein, b ₁b ₀The magnitude of voltage that the base plate of decision difference sampling capacitance is connected in amplifying mutually is corresponding to b ₁b ₀Value be 00,01,10 these three kinds of situations, the base plate of difference sampling capacitance meets (V respectively _Rn, V _Rp), (V _Cm, V _Cm), (V _Rp, V _Rn); d ₁d ₀Determine that each mutual capacitance is as sampling capacitance or feedback capacity, for C ₁And C ₂, if d ₁=0, get C ₂As feedback capacity, if d ₁=1, then get C ₁As feedback capacity, for C ₃And C ₄, if d ₀=0, get C ₄As feedback capacity, if d ₀=1, then get C ₃As feedback capacity.Concrete input and output logical design is among the U2:

2a＝2·d ₁Xa＝2·d ₁·b ₁·b ₀Ya＝2·d ₁·b ₁·b ₀Za＝2·d ₁·b ₁·b ₀

2b＝2·d ₁Xb＝2·d ₁·b ₁·b ₀Yb＝2·d ₁·b ₁·b ₀Zb＝2·d ₁·b ₁·b ₀

2c＝2·d ₀Xc＝2·d ₀·b ₁·b ₀Yc＝2·d ₀·b ₁·b ₀Zc＝2·d ₀·b ₁·b ₀

2d＝2·d ₀Xd＝2·d ₀·b ₁·b ₀Yd＝2·d ₀·b ₁·b ₀Zd＝2·d ₀·b ₁·b ₀

By the execution mode of the commutative level of aforesaid electric capacity circuit as seen, a level circuit proposed by the invention is on typical level circuit base, has increased some extra switches and improves and form at the base plate of each electric capacity, therefore has circuit and realizes characteristic of simple.It is worthy of note that the switch major part that is increased is the switch that is connected to reference voltage, and these switches are generally PMOS or nmos switch, therefore the parasitic capacitance of additionally being brought is very little, and is also very little to the influence of level circuit working speed.

The selection pairing algorithm of electric capacity and the execution mode of circuit: definition e ₁=(C ₁+ C ₃)-(C ₂+ C ₄), e ₂=(C ₁+ C ₄)-(C ₂+ C ₃), e ₃=C ₃-C ₄, e ₄=C ₁-C ₂, according to these variable-definitions, Fig. 3 has provided the course of work that realizes level circuit capacitance selection pairing, specifically describes as follows:

(1) judges e ₁Symbol, if e ₁＞0, make q ₁=1, otherwise, q made ₁=0;

(2) judge e ₂Positive and negative, if e ₂＞0, make q ₂=1, otherwise, q made ₂=0;

(3) judge e ₃Symbol, if e ₃＞0, make q ₃=1, otherwise, q made ₃=0;

(4) judge e ₄Symbol, if e ₄＞0, make q ₄=1, otherwise, q made ₄=0;

(5) result according to step (1)～(4) decides next step operation:

If $\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}\right)\&CenterDot;\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3}\right)\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2=1,$ Be e ₁, e ₂, e ₃Just be all, then forward step (6) to;

If $\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}\right)\&CenterDot;\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3}\right)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}=1,$ Be e ₁, e ₂, e ₃Be all negatively, then forward step (7) to;

If $\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}\right)\&CenterDot;({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3)\&CenterDot;{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1=1,$ Be e ₁, e ₂Just be all and e ₃For negative, then forward step (8) to;

If $\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}\right)\&CenterDot;({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1}=1,$ Be e ₁, e ₂Be all negative and e ₃For just, then forward step (9) to;

If $({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_2)\&CenterDot;\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4}\right)\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2=1,$ Be e ₁, e ₄Be all negative and e ₂For just, then forward step (6) to;

If $({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_2)\&CenterDot;\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4}\right)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}=1,$ Be e ₁, e ₄Just be all and e ₂For negative, then forward step (7) to;

If $({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_2)\&CenterDot;({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4)\&CenterDot;{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1=1,$ Be e ₂, e ₄Be all negative and e ₁For just, then forward step (8) to;

If $({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_2)\&CenterDot;({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1}=1,$ Be e ₂, e ₄Just be all and e ₁For negative, then forward step (9) to;

(6) make d ₁=0, d ₀=1, promptly select C ₁And C ₄Pairing, C ₂And C ₃Pairing, and select C ₂And C ₃As difference feedback capacitance, forward step (10) to;

(7) make d ₁=1, d ₀=0, promptly select C ₁And C ₄Pairing, C ₂And C ₃Pairing, and select C ₁And C ₄As difference feedback capacitance, forward step (10) to;

(8) make d ₁=0, d ₀=0, promptly select C ₁And C ₃Pairing, C ₂And C ₄Pairing, and select C ₂And C ₄As difference feedback capacitance, forward step (10) to;

(9) make d ₁=1, d ₀=1, promptly select C ₁And C ₃Pairing, C ₂And C ₄Pairing, and select C ₁And C ₃As difference feedback capacitance, forward step (10) to;

(10) storage d ₁And d ₀Value, finish the capacitance pairing process of circuit at the corresponding levels.

In above-mentioned capacitance pairing flow process, step (1)～(4) are the operation of comparison capacitance size, and this operation can utilize level circuit itself shown in Figure 2 to finish, and Fig. 4 has provided and realized capacitance size circuit theory relatively.The work of circuit was divided into for two steps, and Fig. 4 a and Fig. 4 b have provided the first step and the circuit connecting relation in second step respectively.In the first step, capacitor C ₁～C ₄Base plate be connected respectively to voltage V _A1～V _A4, the differential input end short circuit of spaning waveguide operational amplifier OP also is connected to voltage V together _Cm, simultaneously, OP carries out self calibration to the DC offset voltage of himself, and when the first step finished, all switches disconnected, V _A1～V _A4Be sampled C ₁～C ₄, and OP finishes the imbalance self calibration; In second step, C ₁～C ₄Base plate be connected respectively to voltage V _B1～V _B4, treat that circuit is stable after, OP is to the voltage V of input _ResCarry out open loop and amplify, this moment, OP was as a comparator, and output is to V _ResPositive and negative judged result.

According to the electric charge transfer relationship, can release V _ResValue be:

$V_{\mathrm{res}}=\frac{(V_{b1}-V_{a1}){\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+(V_{b2}-V_{a2})C_2}{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_2}-\frac{(V_{b3}-V_{a3})C_3+(V_{b4}-V_{a4})C_4}{C_3+C_4}---\left(4\right)$

To voltage V _A1～V _A4And V _B1～V _B4Programme, can finish e respectively ₁～e ₄Positive negative judgement.For example, make V _A1=V _Rn, V _B1=V _Rp, V _A2=V _Rp, V _B2=V _Rn, V _A3=V _Rp, V _B3=V _Rn, V _A4=V _Rn, V _B4=V _Rp, then have:

$V_{\mathrm{res}}\stackrel{\&CenterDot;}{\&ap;}\frac{(V_{\mathrm{rp}}-V_{\mathrm{rn}})[({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+C_3)-({\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">C</figure-callout>}}_2+C_4)]}{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}=\frac{(V_{\mathrm{rp}}-V_{\mathrm{rn}})}{{\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">C</figure-callout>}}_1+{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">C</figure-callout>}}_2}\&CenterDot;e_1---\left(5\right)$

Obviously, by judging V _ResPositive and negative, can learn e ₁Positive and negative.

In above-mentioned capacitance pairing flow process, step (5)～(9) can realize by Digital Logical Circuits simply that logical relation is:

${\mathrm{<figure-callout\; id="1"\; label="d"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">d</figure-callout>}}_1=\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}\right)\&CenterDot;[\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3}\right)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}+({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1}]$

$+({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_2)\&CenterDot;[\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4}\right)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}+({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1}]$

${\mathrm{<figure-callout\; id="0"\; label="d"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">d</figure-callout>}}_0=\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2}\right)\&CenterDot;[\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3}\right)\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2+({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_3)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1}]$

$+({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_2)\&CenterDot;[\left(\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4}\right)\&CenterDot;{\mathrm{<figure-callout\; id="2"\; label="q"\; filenames="C20061008939700111.png"\; state="\{\{state\}\}">q</figure-callout>}}_2+({\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1\&CirclePlus;q_4)\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{<figure-callout\; id="1"\; label="q"\; filenames="C20061008939700112.png"\; state="\{\{state\}\}">q</figure-callout>}}_1}]$

The execution mode of selecting pairing algorithm and circuit by aforesaid electric capacity as seen, it is simple that capacitance pairing method proposed by the invention has a calibration algorithm, do not increase the advantage of the calibration circuit of complexity.

Method proposed by the invention has been that example is described with the circuit design and the capacitance pairing process of the commutative level of 1.5 an electric capacity circuit.Concerning the present technique field had the people of skilled technical ability, it was conspicuous to the effect that reduces the capacitance mismatch error, improves the precision of ADC that the electric capacity that it proposed is selected matching method.In fact, utilize the operating characteristic of difference channel and thought that capacitance pairing reduces matching error to can be applicable to a lot of occasions,, and not only be confined to 1.5 potential difference stage circuits in the above-mentioned example such as the differential levels circuit of multidigit resolution.

Claims (1)

1, a kind of method of the reduction analog to digital converter capacitance mismatch error based on capacitance pairing is characterized in that this method may further comprise the steps:

(1) in 4 mutual capacitances of definition analog to digital converter middle rank circuit, the electric capacity that two top boards are connected to the operational amplifier positive input terminal jointly is C ₁And C ₂, the electric capacity that two top boards are connected to the operational amplifier negative input end jointly is C ₃And C ₄, C wherein ₁And C ₃Be first pair of difference mutual capacitance, C ₂And C ₄Be second pair of difference mutual capacitance, these two pairs of difference mutual capacitances are respectively the difference sampling capacitance or the difference feedback capacitance of grade circuit;

(2) if size of more above-mentioned four mutual capacitances is (C ₁+ C ₃)-(C ₂+ C ₄) absolute value greater than (C ₁+ C ₄)-(C ₂+ C ₃) absolute value, then make C ₁And C ₄Pairing becomes first pair of difference mutual capacitance, C ₂And C ₃Pairing becomes second pair of difference mutual capacitance, if (C ₁+ C ₃)-(C ₂+ C ₄) absolute value less than (C ₁+ C ₄)-(C ₂+ C ₃) absolute value, then keep C ₁And C ₃Be first pair of difference mutual capacitance, C ₂And C ₄Be second pair of difference mutual capacitance;

(3) the capacitance sum of first pair of difference mutual capacitance of above-mentioned steps (2) and the capacitance sum of second pair of difference mutual capacitance are compared, and a pair of difference mutual capacitance that the capacitance sum is less is as the difference feedback capacitance of level circuit, and another is to the difference sampling capacitance as the level circuit.

Images