CN100428352C - Decoding system used for 8-14 modulation or 8-16 modulation - Google Patents
Decoding system used for 8-14 modulation or 8-16 modulation Download PDFInfo
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- CN100428352C CN100428352C CNB2005100642540A CN200510064254A CN100428352C CN 100428352 C CN100428352 C CN 100428352C CN B2005100642540 A CNB2005100642540 A CN B2005100642540A CN 200510064254 A CN200510064254 A CN 200510064254A CN 100428352 C CN100428352 C CN 100428352C
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Abstract
The present invention provides a decoding system used for eight to fourteen modulation or eight to sixteen modulation (EFM/ESM). the present invention comprises an analog-digital conversion device, an adaptive equalization device and a Viterbi decoding device, wherein the analog-digital conversion device receives an analogue signal with the characteristic of EFM or ESM and converts the analogue signal to a digital signal with the characteristic of EFM or ESM; the adaptive equalization device converts the digital signal with the characteristic of EFM or ESM to a first signal with the characteristic of the minimum phase; the Viterbi decoding device receives the first signal and generates a decoding signal according to the Viterbi algorithm and a channel model. When the Viterbi decoding device calculates the path value from a branch to a node, inexistent paths are discarded according to the characteristic of EFM or ESM.
Description
Technical field
The present invention relates to technical field, refer to a kind of decoding system that is used for 8 to 14 modulations or 8 to 16 modulations (EFM/ESM) especially about decoding.
Background technology
Having the intersection data at one disturbs in the environment of (intersymbol interference, ISI), because the influence of data bit before and after the data that read are subjected to, so often disturb (ISI) phenomenon to eliminate the intersection data that receive in the data with the technology that partly responds maximum possible (PRML, Partial Response Maximum Likelihood).The general Viterbi of use deciphers and provides crossing number according to interference signals to separate.
Viterbi decoding is according to some condition probability, to check possible path and to select best path.Fig. 1 is a PRabba channel model, and Fig. 2 is in the PRabba channel model, and a is 1, b is 2 o'clock Trellis synoptic diagram.
In DVD and CD data, owing to use 8 to 14 modulations or 8 to 16 modulations (eight to fourteenmodulation/eight to sixteen modulation, EFM/ESM), be 1 and 2 serial data so do not have consecutive length (run length) in the serial data.So when separating EFM/ESM modulation serial data, the Trellis figure of Fig. 2 can be simplified to the Trellis figure of Fig. 3, just get rid of consecutive length and be 1 and 2 serial data.In Fig. 3, it is-1 that dotted line is represented a4, and it is+1 that solid line is represented a4.Fig. 4 is to use and simplifies the synoptic diagram that Trellis figure carries out Viterbi decoding, wherein list entries be 1 ,-1 ,-1 ,-1 ,+1 ,+1 ,+1 ,-1 ,-1 ,-1 ,-1 ,-1 ,+1 ,+1 ,+1 ,+1 ,+1 ,+1}.Output sequence be 4,0 ,-4 ,-6 ,-4,0,4,4,0 ,-4 ,-6 ,-6 ,-4,0,4,6,6,6}.At the beginning, (be initial 1-1-1), by node according to the path values of the data computation row 0 that receive to row 1.Node (1-1-1) have two branches, be connected to respectively node (1-1-1) and node (1-1+1).(1-1-1) (path values 1-1-1) is in data (4) the substitution path values formula with output to computing node, just with s=4 substitution 9+3s and 4+2s, can obtain 21 and 12 respectively to node.Respectively (1-1-1) and node (1-1+1) top with 21 and 12 nodes that are shown in row 1.Calculated column 1 is during to the path values of row 2, at this moment, in s=0 substitution 9+3s, 4+2s and 0, can obtain 9,4 and 0 respectively, again with 9 and 21 additions, 4 and 21 additions, 0 and 12 additions, and the path values 30,25,12 that obtains accumulating, again (1-1-1), (1-1+1) and node (1+1+1) top with 30,25,12 nodes that are shown in row 2.Analogize in regular turn.Yet the reading speed of DVD and CD drive increases fast, and known techniques is the sequential raising with coding chip.Though this can solve the decoding problem, but can increase coding chip difficult design degree, also because of frequency of operation improves, also produce chip power consumption and become big and heat dissipation problem simultaneously.So known DVD and CD drive decoding system still have the demand of being improved.
Summary of the invention
The objective of the invention is at the decoding system that is provided for 8 to 14 modulations or 8 to 16 modulations (EFM/ESM), produced the problem of coding chip difficult design degree, more reduce chip power consumption and become problem big and heat radiation to avoid known technology.
According to a characteristic of the present invention, be to propose a kind of decoding system that is used for 8 to 14 modulations or 8 to 16 modulations (EFM/ESM), this system comprises to be simulated to digital switching device, an adaptability equalizing apparatus and a Viterbi code translator.This simulates the simulating signal that receives an EFM or ESM modulation characteristics to digital switching device, and will be converted to digital signal with EFM or ESM modulation characteristics; This adaptability equalizing apparatus is coupled to this and simulates to digital switching device, changes first signal with minimum phase characteristic into the digital signal that this is had EFM or ESM modulation characteristics; This Viterbi code translator is coupled to this adaptability equalizing apparatus, receiving this first signal, and according to Viterbi algorithm and a channel model to produce a decoded signal; Wherein, when this Viterbi code translator branches to the path values of a node in calculating one,, give up non-existent path according to this EFM or ESM modulation characteristics.
According to another characteristic of the present invention, be to propose a kind of decoding system that is used for 8 to 14 modulations or 8 to 16 modulation (EFM/ESM) modulations, this system comprises to be simulated to digital switching device, a partitioning circuitry, a frequency and weakened phase restoring device, an adaptability equalizing apparatus and a Viterbi code translator.This simulate to digital switching device be the simulating signal that receives an EFM or ESM modulation characteristics, and will be converted to digital signal with EFM or ESM modulation characteristics; This partitioning circuitry has magnetic hysteresis (hysteresis) characteristic, is a secondary signal with the analog signal conversion with this EFM or ESM modulation characteristics; This frequency and weakened phase restoring device are coupled to this partitioning circuitry and this is simulated to digital switching device, adjust signal to produce one according to this secondary signal, simulate sample time to adjust this, with the frequency and the phase place of the simulating signal of replying this EFM or ESM modulation characteristics to digital switching device; This adaptability equalizing apparatus is coupled to this and simulates to digital switching device, converts first signal with minimum phase characteristic to the digital signal that this is had EFM or ESM modulation characteristics; This Viterbi code translator is coupled to this adaptability equalizing apparatus, receiving this first signal, and according to Viterbi algorithm and a channel model to produce a decoded signal; Wherein, when this Viterbi code translator branches to the path values of a node in calculating one,, give up non-existent path according to this EFM or ESM modulation characteristics.
Because modern design of the present invention can provide on the industry and utilize, and truly have the enhancement effect, so apply for patent of invention in accordance with the law.
Description of drawings
Fig. 1 is the synoptic diagram of a PRabba channel model.
Fig. 2 is that a is 1 in the PRabba channel model, b is 2 o'clock Trellis synoptic diagram.
Fig. 3 is the simplification Trellis synoptic diagram of PRabba channel model.
Fig. 4 is to use and simplifies the synoptic diagram that Trellis figure carries out Viterbi decoding.
Fig. 5 is the calcspar of the decoding system of EFM of being used in of the present invention or ESM modulation.
Fig. 6 is the synoptic diagram that the Trellis figure of Fig. 3 is expanded into 4 row by 2 row.
Fig. 7 is correction Trellis figure of the present invention.
Fig. 8 is the Viterbi decoding synoptic diagram of the present invention according to Fig. 7.
Fig. 9 A is the simplification Trellis figure of a PRaa channel model of the present invention.
Fig. 9 B is the correction Trellis figure of the present invention according to Fig. 9.
Figure 10 A is the simplification Trellis figure of a PRaba channel model of the present invention.
Figure 10 B is the correction Trellis figure of the present invention according to Figure 10.
Symbol description
Simulate to digital switching device 510 adaptability equalizing apparatus 520
Viterbi code translator 530 partitioning circuitries 540
Frequency and weakened phase restoring device 550
Embodiment
Fig. 5 is the calcspar that is used in the decoding system of 8 to 14 modulations or 8 to 16 modulations (EFM/ESM) of the present invention, and it comprises simulates to digital switching device 510, an adaptability equalizing apparatus 520, a Viterbi code translator 530, a partitioning circuitry 540 and a frequency and weakened phase restoring device 550.
Simulate to digital switching device 510 are the simulating signals that receive an EFM or ESM modulation characteristics, and will be converted to digital signal with EFM or ESM modulation characteristics.Partitioning circuitry (slicer) 540, it has magnetic hysteresis (hysteresis) characteristic, and it differentiates the size of input signal, when input signal during greater than the first magnetic hysteresis value, is output as positive potential.And when input signal during less than the second magnetic hysteresis value, output then is zero.Partitioning circuitry 540 is a secondary signal with the analog signal conversion of this EFM or ESM modulation characteristics.Frequency and weakened phase restoring device 550 are coupled to this partitioning circuitry 540 and this is simulated to digital switching device 510, adjust signal to produce one according to this secondary signal, simulate sample time to adjust this to digital switching device, so frequency and weakened phase restoring device 550 are the signals that utilize partitioning circuitry 540 to be produced, with the frequency and the phase place of the simulating signal of replying EFM or ESM modulation characteristics.
Fig. 6 is expanded into 4 row with the Trellis figure of Fig. 3 by 2 row.As shown in Figure 6, after the node of row 1 and row 3 was determined, the node of row 2 can be determined uniquely.Just, when the decoding path via row 1 node (1-1-1) and row 3 nodes (1-1+1) time, this decoding path must (1-1-1), be represented as thick line black among Fig. 6 through the node of row 2.In like manner, when the decoding path via row 2 nodes (1-1-1) and row joints 4 points (1+1+1) time, this decoding path must be through the node of row 3 (1-1+1).
According to above-mentioned, the Trellis figure of Fig. 3 can be made into as shown in Figure 7.Fig. 7 is correction Trellis figure of the present invention, and it once can be deciphered 2 positions.For example, row 1 node (1-1-1-1) run into (and 1-1) during decoding data, then to row 2 nodes (1-1-1-1), among Fig. 7 with dotted line
Expression.Row 1 node (1-1-1-1) run into (1+1) during decoding data, then to row 2 nodes (1-1-1+1), among Fig. 7 with a pecked line
Expression.Row 1 node (1-1-1-1) run into (+1+1) during decoding data, then (1-1+1+1), represent with solid line (→) among Fig. 7 to row 2 nodes.Owing to use the EFM/ESM modulation, be 1 and 2 serial data so do not have consecutive length in the serial data, so row 1 node (1-1-1-1) can not run into (+1-1) decoding data.Row 1 node (+1+1+1+1) run into (+1+1) during decoding data, then to row 2 nodes (+1+1+1-1), among Fig. 7 with two pecked lines
Expression.
By the correction Trellis of Fig. 7 figure, the Viterbi decoding figure of Fig. 4 is repainted as shown in Figure 8.Fig. 8 is the Viterbi decoding synoptic diagram according to the technology of the present invention.List entries be 1 ,-1 ,-1 ,-1 ,+1 ,+1 ,+1 ,-1 ,-1 ,-1 ,-1 ,-1 ,+1 ,+1 ,+1 ,+1 ,+1 ,+1}.At the beginning, (be initial 1-1-1-1), by node according to the path values of the data computation row 0 that receive to row 1.Node (1-1-1-1) has 3 branches, is connected to node respectively and (1-1-1-1), (1-1-1+1) reaches (1-1+1+1).(1-1-1-1) (path values 1-1-1-1) is in data (4) the substitution path values formula with output to computing node, just with s=4 substitution 3s+9,2s+4 and 0, can obtain 21,12 and 0 respectively to node.Respectively 21,12 and 0 node that is shown in row 1 (1-1-1-1), (1-1-1+1) is reached (1-1+1+1) top.Calculated column 1 is during to the path values of row 2, owing to once decipher two positions, so the time with s=-4 substitution 3s+9,2s+4,0 ,-2s+4 ,-2s+4 and-3s+9 in, can obtain-3 ,-4,0,12 and 21 respectively, calculate the path values of accumulation again and obtain 18,17,21,24,12 and 21, again with 18,17,21,24,12 and 21 nodes that are shown in row 2 (1-1-1-1), (1-1-1+1), (1-1+1+1), (1+1+1+1), (+1+1+1-1) and (+1+1+1+1) top.Analogize the Viterbi decoding synoptic diagram that gets final product Fig. 8 in regular turn.
Viterbi code translator 530 is that the correction Trellis figure according to Fig. 7 carries out Viterbi decoding.Because Viterbi code translator 530 once uses 2 positions, so its sampling rate (sampling rate) can be reduced to 1/ (2T) by 1/T.And the processing time of adaptability equalizing apparatus 520 can increase to 2T by 1T.
The point (tabs) of adaptability equalizing apparatus 520 is relevant with the impulse response (impulse response) of transmission channel, and the impulse response of a transmission channel distributes long more at time shaft, and the point (tabs) of adaptability equalizing apparatus 520 required uses is many more.In the present invention since processing time of adaptability equalizing apparatus 520 increase to 2T by 1T, so the point (tabs) of its required use can reduce.Accordingly, the decoding depth of Trellis figure (depth) also can reduce.This not only can reduce required internal memory, more can reduce the power consumption of coding chip.
Fig. 9 A is the simplification Trellis figure of a PRaa channel model, and Fig. 9 B is correction Trellis figure of the present invention.Figure 10 A is the simplification Trellis figure of a PRaba channel model, and Figure 10 B is correction Trellis figure of the present invention.
In sum, the of the present invention simulation to the frequency of operation of digital switching device 510, an adaptability equalizing apparatus 520, a Viterbi code translator 530, a partitioning circuitry 540 and a frequency and weakened phase restoring device 550 can be reduced half than known technology, the point (tabs) of simultaneous adaptation equalizing apparatus 520 and the decoding depth (depth) of Trellis figure also can reduce, this can solve the problem of known technology chip design degree of difficulty, avoids known technology chips power consumption to become big and heat dissipation problem simultaneously.
Above-mentioned preferred embodiment only is to give an example for convenience of description, and the protection domain that the present invention advocated should be as the criterion so that claim is described, but not only limits to the foregoing description.
Claims (6)
1. decoding system that is used for 8 to 14 modulations or 8 to 16 modulations is characterized in that this system comprises:
One simulates to digital switching device, receives the simulating signal of one 8 to 14 modulations or 8 to 16 modulation characteristics, and is converted into the digital signal with this 8 to 14 modulation or 8 to 16 modulation characteristics;
One adaptability equalizing apparatus is coupled to this and simulates to digital switching device, changes first signal with minimum phase characteristic into the digital signal that this is had this 8 to 14 modulation or 8 to 16 modulation characteristics; And
One Viterbi decoding device is to be coupled to this adaptability equalizing apparatus, receiving this first signal, and according to viterbi algorithm and a channel model to produce a decoded signal;
Wherein, when this Viterbi decoding device branches to the path values of a node in calculating one,, give up non-existent path according to this 8 to 14 modulation or 8 to 16 modulations.
2. the system as claimed in claim 1 is characterized in that, also comprises:
One partitioning circuitry, it has hysteresis characteristic, is a secondary signal with the analog signal conversion with this 8 to 14 modulation or 8 to 16 modulation characteristics; And
One frequency and weakened phase restoring device, be coupled to this partitioning circuitry and this is simulated to digital switching device, adjust signal to produce one according to this secondary signal, simulate sample time to adjust this, with the frequency and the phase place of the simulating signal of replying this 8 to 14 modulation or 8 to 16 modulation characteristics to digital switching device.
3. the system as claimed in claim 1, it is characterized in that, when the simulating signal of this 8 to 14 modulation or 8 to 16 modulation characteristics during greater than one first magnetic hysteresis value, this secondary signal is a positive potential, when the simulating signal of this 8 to 14 modulation or 8 to 16 modulation characteristics during less than one second magnetic hysteresis value, this secondary signal voltage is 0.
4. the system as claimed in claim 1 is characterized in that, this channel model is the part respective channel with abba parameter.
5. the system as claimed in claim 1 is characterized in that, this channel model is the part respective channel with aa parameter.
6. the system as claimed in claim 1 is characterized in that, this channel model is the part respective channel with aba parameter.
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| CNB2005100642540A CN100428352C (en) | 2005-04-12 | 2005-04-12 | Decoding system used for 8-14 modulation or 8-16 modulation |
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| CNB2005100642540A CN100428352C (en) | 2005-04-12 | 2005-04-12 | Decoding system used for 8-14 modulation or 8-16 modulation |
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| CN100428352C true CN100428352C (en) | 2008-10-22 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151783A (en) * | 1991-06-05 | 1992-09-29 | Faroudja Y C | Digital television with enhancement |
| DE10114052C1 (en) * | 2001-03-15 | 2002-07-25 | Hertz Inst Heinrich | Radio transmission method within closed space uses simultaneous transmission and reception antenna elements and space-time encoders and decoders |
| US20020196862A1 (en) * | 2001-04-16 | 2002-12-26 | Dill Jeffrey C. | Apparatus and method of CTCM encoding and decoding for a digital communication system |
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2005
- 2005-04-12 CN CNB2005100642540A patent/CN100428352C/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5151783A (en) * | 1991-06-05 | 1992-09-29 | Faroudja Y C | Digital television with enhancement |
| DE10114052C1 (en) * | 2001-03-15 | 2002-07-25 | Hertz Inst Heinrich | Radio transmission method within closed space uses simultaneous transmission and reception antenna elements and space-time encoders and decoders |
| US20020196862A1 (en) * | 2001-04-16 | 2002-12-26 | Dill Jeffrey C. | Apparatus and method of CTCM encoding and decoding for a digital communication system |
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| CN1848274A (en) | 2006-10-18 |
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