CN100426199C - Configuration register and loading method thereof - Google Patents
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- CN100426199C CN100426199C CNB2006101577172A CN200610157717A CN100426199C CN 100426199 C CN100426199 C CN 100426199C CN B2006101577172 A CNB2006101577172 A CN B2006101577172A CN 200610157717 A CN200610157717 A CN 200610157717A CN 100426199 C CN100426199 C CN 100426199C
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Abstract
The invention relates to a distributed register which includes: the first trigger is to collect the sample and register the inputting data by the inner operation module; the second trigger is to collect the data registered by the first trigger when there is no new data inputted into the first trigger or the data inputted into the first trigger is same as the register data. The sampling data is used by the inner operation module. The invention also discloses a data register method. The invention has the high reliability and can read the distributed register value.
Description
Technical field
The present invention relates to Microprocessor Interface (MicroProcessor Interface is called for short MPI) technical field, more particularly, relate to a kind of configuration register and register method thereof.
Background technology
At special IC (Application Specific Integrated Circuit, be called for short ASIC) and field programmable gate array (Field Programmable Gate Array, abbreviation FPGA) in the design, for with outer CPU system communication, inside tends to exist the MPI Interface design.And in the MPI interface, configuration register is absolutely necessary, and generally by configuration register business processing logic module in the sheet of ASIC, FPGA is carried out reasonable disposition, finishes needed function.
In the logical design of prior art, adopt the one-level trigger to realize the configuration (as shown in Figure 1) of configuration register usually to logic function.According to the difference in functionality demand, the data bit width of configuration register can be different, are generally 8,16.The type of configuration register is readable writing, and promptly outer CPU can read the value of register, also can rewrite the value of this configuration register, and the value of configuration register is to use for the interior business processing module.
Because each configuration register all can be assigned a reference address, so address decoding combinational logic module just can be judged the address signal value of outside input and whether equal the current address value of distributing to this configuration register, if equate, then export a signal and give read-write decision logic (being " with door " among Fig. 1), the read-write decision logic again according to the chip selection signal of input whether effectively, address signal whether effectively, write enable signal whether effectively, read enable signal and whether effectively export a signal and indicate configuration register is carried out write operation or read operation:
When chip selection signal, when address signal is effective, and the current enable signal of writing is when effective, and then CPU carries out write operation to this register;
When chip selection signal, when address signal is effective, and the current enable signal of reading is when effective, and promptly MUX (MUX) selects to be designated as the output as MUX of 1 input signal, and then CPU carries out read operation to this register, and the currency of register delivered to the MPI interface, read for outer CPU.
In chip design, generally clock and the employed clock of interior business processing module with configuration register is designed to asynchronous or synchronous both of these case:
First kind: when the clock of configuration register and the employed clock of interior business processing module are asynchronous, be asynchronous interface between configuration register and the internal logic promptly.As CPU during in operate as normal, the interior business processing module can adopt the value of configuration register at any time, if the value of CPU online modification configuration register, the interior business processing module just may use an improper value so, will influence the regular traffic of chip like this, even also can cause chip can't recover normally, promptly reliability is low.
Second kind: when the clock that the clock of configuration register and interior business processing module are used is synchronous, if the clock of interior business processing module for a certain reason, deterioration takes place, even after invalid, then the interior business processing module will break down, at this moment the value that needs to read configuration register is analyzed, but because clock is unusual, causes the value of retaking of a year or grade configuration register unavailable.
Therefore, though above-mentioned first kind of situation can solve the problem of second situation value of retaking of a year or grade configuration register " can't ", but " reliability is low "; Though and second situation can solve the problem of first kind of situation " reliability is low ", but cause " value of retaking of a year or grade configuration register is unavailable ".
Hence one can see that, when adopting above-mentioned first kind, has " reliability is low " this shortcoming; When adopting above-mentioned second kind, there is " value of retaking of a year or grade configuration register is unavailable " this shortcoming.
Summary of the invention
The technical matters that the embodiment of the invention will solve is, the configuration register and the register method thereof that provide a kind of reliability height and retaking of a year or grade Configuration Values to use.
The embodiment of the invention solves the technical scheme that its technical matters adopts: construct a kind of configuration register, comprising:
First trigger is used to sample and deposit the data that the interior business module writes;
Second trigger, be used for when there not being data to write described first trigger, perhaps there are data to write and the data of these data and described first flip-flop register when the same, the data of described first flip-flop register of sampling, the data that sampling obtains are used for the interior business module.
The embodiment of the invention also discloses a kind of register method of data simultaneously, and described method comprises the following steps:
A, judged whether that data need deposit, and/or the data that need deposit are whether identical with the data that the first order is deposited;
B, if when having data need be deposited and these data and the first order are deposited data inequality, data of sampling and need deposit according to first clock signal, and the data that sampling obtains are carried out the first order deposit;
When if the data that the data that do not have data to deposit maybe need to deposit and the first order are deposited are identical, the data of depositing according to the second clock signal sampling first order, and the data that sampling obtains are carried out the second level deposit.
The secondary trigger of the employing embodiment of the invention realizes the chip configuration value is write the technological means of Service Processing Module in the chip, unavailable these two technical matterss of value of the low and retaking of a year or grade configuration register of reliability of the prior art have been solved simultaneously, make that the value of the present invention's retaking of a year or grade configuration register under the asynchronous or synchronous both of these case of clock of the clock of configuration register and interior business processing module is available, and the reliability height.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the synoptic diagram of the configuration register of prior art;
Fig. 2 is the synoptic diagram of the described configuration register of the embodiment of the invention;
Fig. 3 is the process flow diagram of the register method of the described configuration register of the embodiment of the invention.
Embodiment
For making purpose of the present invention, technical scheme and advantage clearer, below by specific embodiment and referring to accompanying drawing, the present invention is described in detail.
Fig. 2 is the synoptic diagram of configuration register of the present invention, as shown in the figure.The configuration register that the present invention is made up of two-stage trigger (i.e. first trigger and second trigger) makes the interior business logic processing module can read the exact value of configuration register output.
The D input end of first trigger receives the data of cpu data bus, be input to the first read-write decision logic, the Enable Pin EN of output termination first trigger of the first read-write decision logic with writing enable signal and chip selection signal behind the address signal process address decoding combinational logic on the system bus.Be input to the second read-write decision logic with reading enable signal and chip selection signal behind the address signal process address decoding combinational logic on the system bus, the output terminal of the second read-write decision logic takes back the read through model input end, and the retaking of a year or grade module is MUX in this preferred embodiment.Clock signal 1 connects the CLK input end of first trigger, and reset signal 1 connects the RST input end of first trigger.Wherein, first, second read-write decision logic is the AND gate decision logic.The Q output terminal of first trigger connects the input end D of second trigger and the input end of MUX respectively, and another input termination second reading of this MUX is write the output terminal of decision logic, the output termination MPI interface of this MUX.
Wherein, first trigger is according to the difference in functionality demand, and its data bit width can be different, are generally 8,16.The type of first trigger is readable writing, and promptly outer CPU can read the value of first trigger, also can rewrite the value of first trigger, and the value of first trigger is to use for the interior business processing module.Because first trigger is assigned a reference address, so address decoding combinational logic module just can be judged the address signal value of outside input and whether equal the current address value of distributing to first trigger, if equate, then export a signal to the first read-write decision logic, the first read-write decision logic again according to the chip selection signal of input whether effectively, address signal whether effectively, write enable signal whether effectively, read enable signal and whether effectively export a signal and indicate first trigger is carried out write operation or read operation:
When chip selection signal, when address signal is effective, and the current enable signal of writing is when effective, and then CPU carries out write operation to this register;
When chip selection signal, when address signal is effective, and the current enable signal of reading is when effective, be that MUX (MUX) selects to be designated as the output of the input signal of " 1 " as MUX, then CPU carries out read operation to this register, and the currency of register delivered to the MPI interface, read for outer CPU.
For guarantee CPU can retaking of a year or grade to the output valve of configuration register, when to read enable signal be invalid, MUX just sent entirely " 0 " (ALL0) signal, like this, through " or " logic just can not influence the value that CPU needs retaking of a year or grade.
The input end of the interior Service Processing Module of the Q output chip termination of second trigger, the CLK input end that connects second trigger of clock signal 2, reset signal 2 connects the RST input end of second trigger.The effect of second trigger mainly is that the exact value that samples first flip-flop register is used for the interior business processing module.
As an improvement of the present invention, in the preferred embodiment of the present invention, a kind of configuration register also comprise be used to produce refresh enable signal refresh the enable signal generation module, what this refreshed that the enable signal generation module comprises that generation refreshes enable signal temporarily refreshes enable signal generation module and synchronization module temporarily.
Refresh the control signal on the system bus that the enable signal generation module receives with configuration register of the present invention links to each other temporarily, clock signal 1 (i.e. first clock signal) according to this control signal and first trigger, when not having data to write configuration register, in the clock zone of the first trigger clock, produce one and refresh enable signal temporarily.Synchronization module receives the described enable signal that temporarily refreshes, according to the described clock signal 2 (being the second clock signal) that refreshes the enable signal and second trigger temporarily, refresh in the clock zone of clock that enable signal is synchronized to second trigger described temporarily, produce the Enable Pin EN that refreshes enable signal and export second trigger to.
The reset signal 1 of first trigger and the reset signal 2 of second trigger can be same signal; And the clock signal 2 of the clock signal 1 of first trigger and second trigger can be synchronous or asynchronous, specifically decides according to chip design; The clock signal 2 of second trigger is the employed clock of interior business processing module.
In the prior art, because the clock that the clock of first trigger and interior business processing module are used is asynchronous (being asynchronous interface between first trigger and the interior business processing module promptly), may cause the interior business processing module to sample this problem of improper value, present embodiment addresses this problem like this:
When first trigger under following arbitrary situation, think that then the output valve of this first order trigger keeps steady state (SS):
When (1) chip selection signal is invalid, when promptly cpu i/f does not have operation;
(2) cpu i/f is write enable signal when invalid, does not promptly carry out write operation;
Whether when (3) address of cpu i/f operation is not the address of this first trigger, no matter remaining address is read and write, the output valve of first trigger of this address all keeps stable.
When the output valve of first trigger remained on steady state (SS), the Enable Pin EN of second trigger produced and refreshes enable signal, and it is specific as follows to produce the step that refreshes enable signal:
At first, in the clock zone of the clock 1 of first trigger, produce one and refresh enable signal temporarily; After then this being refreshed temporarily the clock zone of clock 2 that enable signal is synchronized to second trigger, the back produces synchronously refreshes enable signal and uses as the enable signal that refreshes of second trigger.
Because interim refresh signal is to use clock signal 1 control, so this signal also belongs to the clock zone of clock signal 1.If this signal is without clock signal 2 synchronous processing, the output valve that samples first trigger so is insecure, may adopt data by mistake.
Present embodiment is realized synchronous by two low triggers, promptly earlier this is refreshed enable signal temporarily and input to trigger D input end and the clock signal 2 of second trigger is inputed to this trigger CLK input end.According to actual needs, can adopt one or more triggers to realize this is refreshed the clock zone that enable signal is synchronized to the clock 2 of second trigger temporarily.
Therefore, when the output valve of first trigger be in steady state (SS), refresh enable signal when effective (in this logical design, when refreshing enable signal for " 1 " signal as if this, it is effective synchronously to think that then this refreshes enable signal), the output valve of second trigger sampling configuration register, and deliver to the interior business processing module by the correct output valve that this second trigger obtains sampling and use for it.
Hence one can see that, when chip during in operate as normal, if the output valve of CPU online modification first trigger, after second trigger can wait the output valve of first trigger to be in steady state (SS) so, the output valve that just can remove to sample first trigger, can guarantee that like this second trigger samples a right value, and can not influence regular traffic, the reliability height.
In addition, the present invention also solves in the prior art because the clock of first trigger uses identical clock synchronization with the interior business processing module, and may cause unavailable this problem of value of retaking of a year or grade configuration register.
Because if the clock of interior business processing module is for a certain reason, deterioration takes place, even after invalid, business breaks down, the value that at this moment needs to read configuration register is analyzed.Though the clock of interior business processing module unusual (promptly the clock of second trigger is also unusual) at this time, at this moment the clock of first trigger is normally, so still can read the output valve from first trigger.Therefore, the output valve of having guaranteed retaking of a year or grade first trigger is available.
Fig. 3 is the process flow diagram of the control method that the register value of configuration register is sampled of the present invention, as shown in the figure.
Step S1, S2: judged whether that data need deposit, whether the data that need deposit are identical with the data that the first order is deposited.
Step S3: if the data that do not have need be deposited, when perhaps having data need be deposited and these data and the first order are deposited data identical, in the clock zone of first clock signal, produce the useful signal that temporarily refreshes enable signal, according to the second clock signal the described useful signal that temporarily refreshes enable signal is synchronized in the clock zone of described second level clock, generation refreshes the useful signal of enable signal, and execution in step S5.
Step S4: if there are data need deposit and these data and first data of depositing when inequality, promptly the data that need deposit and the first order data of depositing are different, generation refreshes the invalid signals of enable signal, the data that sampling need be deposited according to first clock signal, and the data that sampling obtains are carried out the first order deposit.
Step S5: data of depositing according to the second clock signal sampling first order, and the data that sampling obtains are carried out the second level deposit, when the interior business module need read the data of being deposited, then the data that the second level is deposited offered the interior business module and read.
Therefore, the present invention can be applied in the clock synchronization or asynchronous design of the clock of configuration register and interior business processing module simultaneously, can in each project, realize sharing, reduced the input and the risk of the exploitation manpower of configuration register, and the present invention is applicable to simultaneously also in the EDA designs such as ASIC, FPGA.
Though described the present invention by embodiment, those of ordinary skills know, the present invention has many distortion and variation and do not break away from spirit of the present invention, and the claim of application documents of the present invention comprises these distortion and variation.
Claims (10)
1, a kind of configuration register is characterized in that, comprising:
First trigger is used to sample and deposit the data that the interior business module writes;
Second trigger, be used for when there not being data to write described first trigger, perhaps there are data to write and the data of these data and described first flip-flop register when the same, the data of described first flip-flop register of sampling, the data that sampling obtains are used for the interior business module.
2, configuration register according to claim 1, it is characterized in that, described configuration register also comprises the retaking of a year or grade module, described retaking of a year or grade module links to each other with the output terminal of described first trigger, be used for when the interior business module has read request to described configuration register, the value of the output terminal of described first trigger delivered to the interface of the read operation correspondence of described interior business module.
3, configuration register according to claim 2, it is characterized in that, described retaking of a year or grade module is a MUX, an input end of described MUX links to each other with the output terminal of described first trigger, control end is by the read-write control of the second read-write decision logic output, be used at the control end signal when reading useful signal, the data of the output terminal of described first trigger delivered to the interface of the read operation correspondence of described interior business module.
4, configuration register according to claim 1 and 2 is characterized in that, described second trigger comprises Enable Pin, and when the signal of described Enable Pin was effective, described second trigger was according to the value of described first flip-flop register of second clock signal sampling.
5, configuration register according to claim 4, it is characterized in that, described configuration register also comprises and refreshes the enable signal generation module, the described control signal that refreshes on the system bus that the enable signal generation module receives with described configuration register links to each other, according to the described control signal and first clock signal, when not having new data to write described configuration register, output effectively refreshes the Enable Pin of enable signal to described second trigger.
6, configuration register according to claim 5 is characterized in that, the described enable signal generation module that refreshes also comprises:
Refresh the enable signal generation module temporarily, the described control signal that temporarily refreshes on the system bus that the enable signal generation module receives with described configuration register links to each other, according to described control signal and described first clock signal, not having data to write described configuration register or having data to write and the data of these data and described first flip-flop register when the same, in the clock zone of described first clock signal, produce and refresh enable signal temporarily;
Synchronization module, described synchronization module receives the described enable signal that temporarily refreshes, according to described enable signal and the described second clock signal of refreshing temporarily, refresh in the clock zone that enable signal is synchronized to described second clock signal described temporarily, produce the described useful signal that refreshes enable signal.
7, a kind of register method of data is characterized in that, described method comprises the following steps:
A, judged whether that data need deposit, and/or the data that need deposit are whether identical with the data that the first order is deposited;
B, if when having data need be deposited and these data and the first order are deposited data inequality, data of sampling and need deposit according to first clock signal, and the data that sampling obtains are carried out the first order deposit;
When if the data that the data that do not have data to deposit maybe need to deposit and the first order are deposited are identical, the data of depositing according to the second clock signal sampling first order, and the data that sampling obtains are carried out the second level deposit.
8, register method according to claim 7 is characterized in that, described method also comprises the steps:
C, when the interior business module need read the data of being deposited, then the data that the second level is deposited offer the interior business module and read.
9, register method according to claim 7 is characterized in that, described step b specifically comprises the steps:
If there are data to deposit, then produce the invalid signals that refreshes enable signal;
If when the data that the data that do not have data to deposit maybe need to deposit and the first order are deposited were identical, then generation refreshed the useful signal of enable signal, the data of depositing according to the second clock signal sampling first order.
10, register method according to claim 9 is characterized in that, the step that described generation refreshes the useful signal of enable signal is specially:
In the clock zone of described first clock signal, produce the useful signal that temporarily refreshes enable signal, according to described second clock signal the described useful signal that temporarily refreshes enable signal is synchronized in the clock zone of described second clock, produces the described useful signal that refreshes enable signal.
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| CNB2006101577172A CN100426199C (en) | 2006-12-20 | 2006-12-20 | Configuration register and loading method thereof |
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| CNB2006101577172A CN100426199C (en) | 2006-12-20 | 2006-12-20 | Configuration register and loading method thereof |
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| CN100426199C true CN100426199C (en) | 2008-10-15 |
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| JP6156599B2 (en) * | 2015-02-09 | 2017-07-05 | 株式会社村田製作所 | Register circuit |
| CN109343794B (en) * | 2018-09-12 | 2021-11-09 | 杭州晨晓科技股份有限公司 | Configuration method and configuration device of memory |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1679009A (en) * | 2002-06-28 | 2005-10-05 | 英特尔公司 | Joshi Aniruddha,Lee John,Kwatra Atul |
| US20050251712A1 (en) * | 2000-12-20 | 2005-11-10 | Nec Corporation | Skew adjusing circuit and semiconductor integrated circuit |
| US20060059282A1 (en) * | 2004-08-30 | 2006-03-16 | International Business Machines Corporation | Snapshot interface operations |
| US20060273823A1 (en) * | 2005-05-19 | 2006-12-07 | Infineon Technologies Ag | Circuit arrangement for supplying configuration data in FPGA devices |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050251712A1 (en) * | 2000-12-20 | 2005-11-10 | Nec Corporation | Skew adjusing circuit and semiconductor integrated circuit |
| CN1679009A (en) * | 2002-06-28 | 2005-10-05 | 英特尔公司 | Joshi Aniruddha,Lee John,Kwatra Atul |
| US20060059282A1 (en) * | 2004-08-30 | 2006-03-16 | International Business Machines Corporation | Snapshot interface operations |
| US20060273823A1 (en) * | 2005-05-19 | 2006-12-07 | Infineon Technologies Ag | Circuit arrangement for supplying configuration data in FPGA devices |
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