CN100417058C - Coder-decoder for return-to-zero code or mark inverse code - Google Patents
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Abstract
The present invention relates to a line coding and decoding technology which is used for a digital transmission system, particularly to a coding and decoding device for converting a non-return-to-zero (NRZ) code into a code-mark (CMI) inverse code and converting the CMI code into the NRZ code, wherein a coding part which is used for causing the NRZ code to be coded into the CMI code comprises a mode controlling unit, a code pattern converting unit and a parallel-serial converting unit; a decoding part which is used for causing the CMI code to be decoded into the NRZ code comprises a clock processing unit for receiving CMI data on an input end, a parallel-serial converting unit, a code pattern converting unit, an error code monitoring unit, an error code counting unit and a synchronization adjustment unit. The coding and decoding device has the advantages of simple and reliable structure and low cost, and can realize OSC interconnection and intercommunication of different manufacturers; the limited bandwidth of an OSC passage can not be occupied. Compared with the existing synchronization character time slot filling method, the present invention has the advantages of no dependence for data formats, reliable operation and high utilization rate of the bandwidth. Compared with the coding and decoding processes which are realized by an exclusive chip, the technology of the present invention has the advantages of simplicity, reliability and low cost, coding and decoding operation of various speed rates can be realized, and the space is saved.
Description
Technical field
The present invention relates to be used for the circuit encoding and decoding technique of digital transmission system, be specifically related to the coding and decoding device of nonreturn to zero code (nonreturn to zero code be abbreviated as NRZ, the i.e. abbreviation of NO RETURN ZERO)-coded mark inverse code.
Background technology
In digital communication system, for long even " 0 " and length in the erasure signal connect " 1 " so that at receiving terminal clock signal is effectively extracted, often before transmission, signal is carried out certain code conversion, the line code of using always has a variety of, for example CMI sign indicating number (abbreviation of CODEMARKED INVERSION, expression coded mark inverse code), mBnB sign indicating number, HDBn sign indicating number, AMI sign indicating number or the like.Wherein CMI (Coded Mark Inversion) sign indicating number is a coded mark inverse code, is a kind of line code commonly used.So-called code conversion is exactly to need NRZ (nonreturn to zero code) code data is carried out line coding at transmitting terminal, is encoded to the CMI sign indicating number, carries out opposite decoding processing at receiving terminal then, is decoded into the NRZ sign indicating number.In optical communication system, this conversion is often used especially.
According in " CAINONET Optical Supervisory Channel technical specification " relevant with the Ministry of Posts and Telecommunications " dense wave division multipurpose optical transmission system " to Optical Supervisory Channel (hereinafter to be referred as OSC,
Optical The abbreviation of Supervisory Channel) requirement, clearly the numeric data code type that transmits on the regulation circuit is the CMI sign indicating number.Like this before carrying out electricity/light transform data emission, just the signal of telecommunication (NRZ sign indicating number) that transmits need be converted to CMI sign indicating number type, modulate transmission then, same will be the sign indicating number type that the signal of telecommunication contravariant of CMI is changed to the NRZ sign indicating number after receiving terminal carries out light/electric conversion, is beneficial to the OSC plate signal is handled.
In dense wavelength division multiplexing system, the signal that regulation requires OSC to handle onboard is the PCM basic group 2Mbit/sNRZ signal of G703 regulation, is made up of 32 time slots at present.And the signal that transmits on light path is the CMI signal of 4Mbit/s.Can have a variety ofly for NRZ to the converter technique of CMI signal, the synchronization slot completion method is for example arranged, promptly utilize the idle time slot of 2Mbit/s signal to fill in the used synchronization overhead word of encoding and decoding, be beneficial to decode at receiving terminal.Also can carry out conversion designs by some proprietary chips.Synchronization character time slot completion method utilizes the idle time slot transmission in the 2Mbit/s signal to be used for the synchronization character that receiving terminal carries out the synchronized packets decoding, for the reliable Detection synchronization character, be correctly decoded, must adopt a plurality of time slots, this just makes the OSC passage be used for transmitting the ECC data, the available bandwidth of other overheads such as public affair data reduces, increase along with ECC data and other overhead data, the limitation of this method is obvious day by day, this method of while depends on the data of being transmitted and has certain frame format, to be used at fixed position insertion synchronization character, its disadvantage is exactly to interconnect with the OSC of other producer, can't be sufficient the demand of modern optical networks development.And realize that with proprietary chip above-mentioned conversion is also fewer, and this method cost is higher, and switching rate also is restricted simultaneously, can not satisfy the encoding and decoding conversion under the multiple speed flexibly, also is restricted on the circuit board wiring space of growing tension.
Summary of the invention
The technical problem to be solved in the present invention is to overcome the limitation of above-mentioned available technology adopting synchronization character time slot completion method and the shortcomings such as cost height that proprietary chip is realized, thereby satisfy different manufacturers OSC interconnection requirement.
Above-mentioned technical problem is to solve like this, construct the coding and decoding device of a kind of nonreturn to zero code (NRZ)-coded mark inverse code (CMI), it is characterized in that, the coded portion that is used for nonreturn to zero code is encoded to coded mark inverse code comprises: the pattern control unit is used for providing two kinds of coding modes according to the content of the NRZ sign indicating number of input; Coding sign indicating number type converting unit, the pattern output and the encoded clock that are used for providing based on described pattern control unit are converted to 2 one group parallel C MI sign indicating number with the serial NRZ sign indicating number of importing by truth table; Parallel serial conversion unit, be used for the parallel C MI data transaction of described coding sign indicating number type converting unit output is become the CMI serial data, the decoded portion that is used for the CMI sign indicating number is decoded as the NRZ sign indicating number comprises: the clock processing unit, after receiving the CMI data, at first data are regenerated and Clock Extraction, string and grouping before the data of output are delivered to string and modular converter and prepared to decode are extracted the clock that obtains and are delivered to simultaneously in each module in the decoded portion, are used for deal with data; String and converting unit, the serial data that is used for importing from described clock processing unit is converted to the parallel data of 2 one group CMI sign indicating number; A decoding sign indicating number type converting unit, the data based coding rule that being used to receive described string and converting unit provides is converted to the NRZ sign indicating number with the CMI sign indicating number; Be used for whether existing the error monitoring unit of error code according to the status data monitoring that described decoding sign indicating number type converting unit provides; The Bit Error Code Statistics unit of Bit Error Code Statistics is carried out in the error code pulse that provides according to described error monitoring unit; And the error code number of times that provides according to described Bit Error Code Statistics unit provides the synchronous adjustment unit of synchronous conditioning signal to described string and converting unit when surpassing a predetermined value.
In according to device provided by the invention, in described coded portion, described pattern control unit comprises the state machine of 1 bit representation of a usefulness, is used for rotating between pattern 1 and pattern 2 for " 1 " according to the current input NRZ sign indicating number of described sign indicating number type converting unit.
In according to device provided by the invention, in described coded portion, described NRZ-CMI conversion truth table is such, and when described pattern control unit output state was pattern 1, the NRZ sign indicating number of input was 0 and 1, was converted to 01 and 00 of CMI respectively; When described pattern control unit output state was pattern 2, the NRZ sign indicating number of input was 0 and 1, was converted to 01 and 11 of CMI respectively.
In according to device provided by the invention, in described coded portion, described parallel serial conversion unit utilizes the high-low level of clock that 2 CMI sign indicating number parallel datas that provided by described sign indicating number type converting unit are sampled serial output then.
In according to device provided by the invention, in described decoded portion, described clock processing unit comprises the regeneration shaping circuit, is used for the input data are carried out shaping regeneration; With and input be connected with described regeneration shaping circuit and be used for phase-locked loop circuit that clock signal is extracted, described clock processing unit is exported data that described regeneration shaping circuit regeneration shaping obtains and by described phase-locked loop circuit recovered clock signal.
In according to device provided by the invention, in described decoded portion, described string and converting unit comprise shift register, are used for the CMI data that receive are carried out the 2BIT grouping, form the parallel data of one group of 2BIT, export described code conversion unit to.
In according to device provided by the invention, in described decoded portion, described decoding code conversion unit is to the CMI data 01,00 of pattern 1, the CMI data 01,11 of pattern 2 and the illegal taboo word 10 that may occur, the status word output that error code is differentiated that is used for of the output of 0,1,0,1,1 NRZ code data and 000,001,000,010 and 100 is provided respectively, current state word and previous state word are all 010 or at 010 o'clock, and the output state word is 100.
In according to device provided by the invention, in described decoded portion, the status word that described error monitoring unit provides according to described decoding sign indicating number type converting unit, the status recognition word is 100 o'clock, produce an error code pulse and give described Bit Error Code Statistics unit, described Bit Error Code Statistics unit to error code pulse count, when reaching predetermined value, produce output and adjust pulse.
In according to device provided by the invention, in described decoded portion, described synchronous adjustment unit is adjusted the time window of a bit according to the adjustment pulse from described Bit Error Code Statistics unit to the clock signal of the shift register in described string and the converting unit.
In according to device provided by the invention, described pattern control unit in the described coded portion, described coding sign indicating number type converting unit and described parallel serial conversion unit adopt electrically programmable logical device EPLD to realize, the error monitoring unit of the described clock processing unit in the described decoded portion, described string and converting unit, described decoding sign indicating number type converting unit, described error code, described Bit Error Code Statistics unit and described synchronous adjustment unit adopt EPLD to realize.
Implement coding and decoding device provided by the invention, compared with prior art, have simple and reliable for structurely, cost is low, can realize that the OSC of different manufacturers interconnects simultaneously, does not take the advantages such as finite bandwidth of OSC passage.The synchronization character time slot completion method that adopts with prior art compares, and the present invention does not rely on data format, reliable operation, makes more advantages of higher of bandwidth availability ratio.Compare with the decoding method that the proprietary chip of prior art is realized, the advantage that this method has is simple and reliable, with low cost, can realize the encoding and decoding under the multiple speed has been saved the space for the limited pcb board in space simultaneously.Device of the present invention can utilize in the present Design of Digital Circuit programming device EPLD that arrives commonly used to realize conversion and the inverse transformation of NRZ to CMI, not only can be used for the CMI sign indicating number type conversion on the present OSC plate, also be applicable to the conversion of sign indicating number type and the inverse transformation of higher rate simultaneously.
Description of drawings
Fig. 1 is the theory diagram of coded portion in apparatus of the present invention;
Fig. 2 is the theory diagram of decoded portion in apparatus of the present invention;
Fig. 3 is the clock processing module 201 and the also composition detail view of module 202 of going here and there in the decoded portion theory diagram shown in Figure 2;
Fig. 4 is the logic diagram of the concrete error code discrimination unit in the embodiment of explanation Error detection principle.
Embodiment
Based on the coding and decoding device of nonreturn to zero code-coded mark inverse code provided by the invention, can realize the codec functions of NRZ-CMI by EPLD, the implementation procedure and the principle of accompanying drawings NRZ-CMI encoding and decoding of the present invention.
As shown in Figure 1, for implementing NRZ-CMI code device of the present invention, comprise coding sign indicating number type converting unit 101, mode switch module 102 and three parts of parallel serial conversion module.Wherein, parallel serial conversion module 103 required clocks are provided by the external crystal-controlled oscillation source.The NRZ data that input to yard type modular converter 101 are encoded and are converted to the CMI parallel data and directly deliver in the parallel serial conversion module 103 and to prepare to carry out and go here and there conversion, the mode bit that to also have an output simultaneously be pattern is delivered to 102 modules, replace control bit by 102 module generation patterns and return to 101 modules again, the pattern alternate coded is carried out in control.Coding sign indicating number type converting unit 101 is used for the NRZ sign indicating number of input is converted to the CMI sign indicating number, and this coding sign indicating number type converting unit 101 can be carried out code conversion according to the rule of CMI coding, and the transformation rule of being followed is as shown in table 1:
Table 1CMI coding rule
Can realize code conversion to data BIT the data of NRZ sign indicating number can being converted to the CMI code data according to above coding rule.Wherein the CMI sign indicating number of " 10 " is invalid CMI sign indicating number.In EPLD, can realize the coding rule shown in the table 1 with the mode of truth table.Herein, the NRZ data are input to the input of coding sign indicating number type converting unit 101, encode according to the coding rule that truth table provides, be output as the parallel output data output of one group of 2BIT behind the coding, this output is connected to parallel serial conversion module 103 and carries out and go here and there conversion.Also have an output to be connected with the input and output side of mode control module 102 respectively with an input in coding sign indicating number type converting unit 101, mode control module 102 comprises the state machine control of a mode bit.Mode control module 102 is used to provide the mode switch of CMI sign indicating number.In order to reduce long connect " 0 " and the long appearance that connects " 1 ", according to pattern alternate coded principle, promptly alternately encode during coding with " 00 " and " 11 " for " 1 " of the NRZ sign indicating number that is encoded.Can reduce long " 1 " and long connect " 0 " of connecting in the data flow like this.Occurring even in the data-signal of coding back, the maximum number of " 1 " is 3.Pattern when the state machine that utilization is included in a 1bit in the mode control module can be realized encoding is conversion alternately, the pattern position is exported in the mode control module 102 when encoding by coding sign indicating number type converting unit 101, select different patterns next time when " 1 " being encoded by the output control of mode control module 102.Respective logic can realize with text language in EPLD.The input of parallel serial conversion module 103 receives the parallel output data of the CMI sign indicating number of own coding sign indicating number type converting unit 101.Rise to 2 times of NRZ code data speed through the CMI code data speed after 101 conversions of coding sign indicating number type converting unit, and be parallel data, before final output, also need to carry out and go here and there conversion, the serial of CMI sign indicating number is exported at parallel serial conversion module 103.Parallel serial conversion module 103 can utilize the high-low level of clock that CMI sign indicating number parallel data is sampled, serial output then.The logical circuit of same this module can utilize the text language of EPLD to realize.
The following describes decoding (decoding) part of CMI-NRZ sign indicating number.We know, the decoded portion more complicated, key is the stationary problem of word when having a decoding, because every BIT with NRZ when coding encodes with two BIT, when decoding, should at first serial data be gone here and there and change receiving terminal like this, be converted to the CMI sign indicating number of one group of every 2BIT, just can carry out inverse transformation then and realize decoding according to coding rule, but owing to when the group of serial data being carried out 2BIT is divided, be at random, can the appearance group divide the possibility that misplaces, will cause the appearance of a large amount of invalid codes " 10 " like this, cause a large amount of error codes.
As described in Figure 2, comprise according to decoded portion of the present invention: clock processing module 201, string and modular converter 202, decoding sign indicating number type converting unit 203, error code detection module 204, Bit Error Code Statistics module 205, synchronous adjusting module 206.Wherein, but the CMI data that the input receiving terminal of clock processing circuit module 201 receives.Clock processing module 201 is at first regenerated and Clock Extraction to data, the data of output deliver to string and modular converter 202 is prepared decode preceding string and grouping, the clock that extraction simultaneously obtains should be delivered to string and modular converter 202, a decoding sign indicating number type converting unit 203, error monitoring module 204, Bit Error Code Statistics module 205 and synchronous adjusting module 206 simultaneously, is used for deal with data.Data after the regeneration are sent into string and modular converter 202, utilize the shift register generation parallel data that is shifted in string and modular converter 202, and the parallel data of output is delivered to the conversion of decoding of a yard type modular converter 203.The NRZ data of output serial and the mode bit that is used to carry out the error code discriminating, the NRZ data are directly sent, and the mode bit that obtains is sent in the error monitoring module 204, produce the error code pulse when monitoring error code, pulse is counted to error code then, export the error code pulse behind the counting to synchronous adjusting module 206, adjusting module 206 is adjusted pulse synchronously according to the numerical value generation that error code counts to get synchronously, should adjust synchronously pulse output and be fed through string and modular converter 202, and be controlled at and go here and there and the synchronized packets when changing.
The further composition situation of clock processing module 201 as shown in Figure 3, Fig. 3 shows the clock processing module 201 in Fig. 2 decoded portion and the institutional framework of string and modular converter 202.Clock processing module 201 is made up of regeneration shaping circuit 301 and phase-locked loop circuit 302, the input of this module comes from the CMI data that receive, the data that being output as regenerates obtains and the clock of extraction, string and modular converter 202 mainly are made up of shift register, input comes the data after 201 regeneration of self-clock processing module, is output as the parallel data of one group of 2BIT.Undertaken inputing to phase-locked loop circuit 302 after the shaping regeneration by 301 pairs of CMI data of regeneration shaping circuit, extract, then data after the output regeneration and the clock that recovers to obtain by 302 pairs of clock signals of phase-locked loop.With inputing to string and modular converter 202 and other module behind clock 2 frequency divisions that recover to obtain, when the subsequent treatment data, use.Data after the regeneration also input to string and modular converter 202 simultaneously simultaneously.String and modular converter 202 are used for data of delivering to decoding sign indicating number type converting unit 203 are gone here and there earlier and changed, and promptly the CMI data that receive are carried out the 2BIT grouping, can realize the division of 2BIT group with shift register.This module is output as the parallel data of one group of 2BIT, exports in the decoding sign indicating number type converting unit 203 to carry out code conversion.Simultaneously, string and modular converter 202 also have an input to come motor synchronizing adjusting module 206, are controlled at grouping to occur and divide that the division window to the packet synchronization signal moves 1 when wrong.Decoding sign indicating number type converting unit 203 is used for parallel CMI data are carried out a yard shape inverse transformation according to the situation that may occur, and promptly is converted to the NRZ sign indicating number.Its transformation rule is as shown in table 2:
Table 2CMI-NRZ transformation rule
The parallel data of string and modular converter 202 outputs is carried out code conversion according to table 2,2 outputs are arranged, one of them is exactly decoded NRZ code data output, and another is output as the wide state output of 3BIT, is used for error code and differentiates.The NRZ data are directly exported, and the state dateout need be received and carries out error code in the error monitoring module 204 and differentiate.Noting this moment invalid code " 10 " also being decoded, is the situation of considering the circuit error code, is convenient in Bit Error Code Statistics error code statistical.This part can realize logic function with truth table in EPLD.The state dateout qq[3..1 that error code detection module 203 provides with decoding sign indicating number type converting unit 203] as the input data of Error detection, the principle of carrying out the error code discriminating has two: 1) when code conversion, taboo word " 10 " when utilizing coding is as a principle of error code discrimination, promptly when separating code conversion, if " 10 " state appears in grouped data, then the qq3 position is " 1 ", and as the qq3 in the table 2, thinking has error code to produce; 2) principle that replaces according to pattern when encoding, promptly the coding of " 00 " or " 11 " can not occur continuously, utilizes the qq1 of status register to represent pattern 1 effective like this, and qq2 represents pattern 2 effective, this set in the time of effectively.Then qq1 and qq2 are shifted under the control of clock respectively, data before and after the displacement are carried out and operation, if the result is " 1 ", then the phenomenon that the same pattern of double usefulness is encoded has appearred in explanation, i.e. explanation has error code to produce, and produces the error code pulse.The input of error code counting module 206 is provided by the output of error monitoring module 204 modules, by in the error monitoring module 204 to utilizing above-mentioned two kinds of error codes to differentiate that principle judges that by error monitoring module 204 the error code pulse that obtains carries out counting statistics, judge whether to take place the grouping step-out.Think then that when error code reaches certain numerical value mistake appears in the grouping when string and conversion, need adjust, produce output adjustment pulse and give synchronous adjusting module 206.In error code counting module 204, in case error code surpasses certain limit, just think that the mistake division has appearred in the random packet when going here and there and change, the logic of controlling synchronous adjusting module 206 immediately produces adjusts pulse, feeds back to being shifted synchronously to group in the synchronized packets logic in string and the modular converter 202.Because at coding the time is that 1BIT is encoded with 2BIT, if so in case the mistake of appearance group is synchronous, moves one and just can realize that correct word is synchronous as long as will divide window, recovery is rapid.
Fig. 4 is the concrete error code discrimination logic diagram in the embodiment of the invention.Among the figure mode bit that obtains is carried out error code and differentiate in 203 modules, carry out error code according to foregoing two principles and differentiate, produce the error code pulse.
Example:
Hardware components adopts programming device EPLD, adds JTAG or PS mouth and downloads for carrying out program, realizes that circuit is simple.Software section adopts the EPLD of ALTERA company to design and develop software MAXPLUS29.01, utilizes schematic diagram and text formatting to carry out the realization of logic function.In an experimental system, adopt the present invention to realize encoding and decoding between the NRZ-CMI on the OSC plate, speed at NRZ signal and CMI signal is respectively under 2Mbit/s and the 4Mbit/s condition, proves that this visit case is reliable and stable, satisfies the OSC plate to the error rate 10
-11Requirement.
Example: with the NRZ data instance of 2Mbit/s, the NRZ data sequence of input is:
“0000?0001?0010?0011?0100?0101?0110?0111?1000”
At first handled by parallel serial conversion module 101 when coding, the data behind parallel serial conversion module 101 codings are output as:
“01010101?01010100?01011101?01010011?01000101?0111010001110001?01110011?00010101”
The mode state position of parallel serial conversion module 101 is output as simultaneously:
“0000?0000?0010?0001?0000?0100?0100?0101?0000”
This mode state position is carried out state machine by mode control module 102 and is handled memory, then same sequence is sent back in yard type modular converter 101.
Sign indicating number type modular converter 101 is output as parallel data, then becomes the serial CMI data of 4Mbit/s behind process parallel serial conversion module 103.
The CMI data sequence of sending into clock processing module 201 during decoding is " " 0,101,010,101,010,100 01,011,101 01,010,011 01,000,101 01,110,100 01,110,001 0111001100010101 "
The clock of clock processing module 201 outputs is 4MHz and 2MHz, and the data of output are identical with input, but passed through shaping.In string and modular converter 202, the CMI sequence of input is divided into groups, promptly become two one group, here in two kinds of situation:
A) if be output as " 01 01 01 01 01 01 01 00----------01 01; again this output is sent into a yard type modular converter 203; obtain: " 0000 0001-----1000 "; this moment, grouping was correct; so the mode bit of sign indicating number type modular converter 203 outputs is: " 000 000,000 000 000 000 000 001----001 000 000 000 "; the error code that obtain by error monitoring module 204 this moment is 0, therefore do not producing synchronous adjustment pulse in the adjusting module 206 synchronously yet, guaranteeing in string and modular converter 202, still to go here and there and change according to correct grouping.
If the data of output for " 10 10 10 10 10 10 10 00----00 10 10 10 " also promptly wherein grouping mistake appearred, lost first bit, mistake appears so divide, then output " 100 100 100-----000 100,100 100 " is such because the highest order of mode bit is " 1 " under most situation in the mode bit in sign indicating number type modular converter 203 like this, therefore the error code in error monitoring module 204 then can produce the error code pulse in differentiating, in the error code counting, have a large amount of error codes, therefore produce and adjust pulse synchronously, export a high level, shift register in this high level control string and the modular converter 202, grouping is shifted, guarantees that grouping is correct.Sequence after the displacement is because grouping is correct, so the same A of the result of back.
The coding and decoding device of NRZ-CMI of the present invention, fundamentally eliminated the defective that can't interconnect that slot synchronization word method is brought, a method that realizes the conversion of sign indicating number type with software and hardware combining is provided simultaneously, it is low to have cost, and working stability is reliable, be fit to and characteristics such as multiple speed encoding/decoding.
More than be to realize the simple introduction of NRZ-CMI code conversion and the inverse transformation basic principle and the example with EPLD, wherein can realize with diverse ways specific to each part, for example can realize, also can realize logic with the schematic diagram form with text.
Claims (8)
1. the coding and decoding device of a nonreturn to zero code-coded mark inverse code is characterized in that, the coded portion that is used for nonreturn to zero code is encoded to coded mark inverse code comprises: the pattern control unit is used for providing two kinds of coding modes according to the content of the nonreturn to zero code of input; The pattern control unit comprises the state machine of 1 bit representation of a usefulness, be used for rotating between pattern 1 and pattern 2 for " 1 " according to the current input nonreturn to zero code of described code-shaped converting unit, when pattern control unit output state is pattern 1, the nonreturn to zero code of input is 0 and 1, is converted to 01 and 00 of coded mark inverse code respectively; When described pattern control unit output state was pattern 2, the nonreturn to zero code of input was 0 and 1, was converted to 01 and 11 of coded mark inverse code respectively;
Coding sign indicating number type converting unit, the pattern output and the encoded clock that are used for providing based on described pattern control unit are converted to 2 one group parallel coded mark inverse code with the serial nonreturn to zero code of importing by truth table; Parallel serial conversion unit is used for the parallel coded mark inverse code data transaction of described coding sign indicating number type converting unit output is become the coded mark inverse code serial data; The decoded portion that is used for coded mark inverse code is decoded as nonreturn to zero code comprises: the clock processing unit, after receiving the coded mark inversion code data, at first data are regenerated and Clock Extraction, the data of output deliver to string and converting unit is prepared decode preceding string and grouping, the clock that extraction obtains is delivered in each module in the decoded portion simultaneously, is used for deal with data; String and converting unit, the serial data that is used for importing from described clock processing unit is converted to the parallel data of 2 one group coded mark inverse code; The codec type converting unit, the data based coding rule that being used to receive described string and converting unit provides is converted to nonreturn to zero code with coded mark inverse code; Be used for whether existing the error monitoring unit of error code according to the status data monitoring that described decoding sign indicating number type converting unit provides; The Bit Error Code Statistics unit of Bit Error Code Statistics is carried out in the error code pulse that provides according to described error monitoring unit; And the error code number of times that provides according to described Bit Error Code Statistics unit provides the synchronous adjustment unit of synchronous conditioning signal to described string and converting unit when surpassing a predetermined value.
2. according to the coding and decoding device of claim 1, it is characterized in that, in described coded portion, described parallel serial conversion unit utilizes the high-low level of clock that 2 coded mark inverse code parallel datas that provided by described sign indicating number type converting unit are sampled serial output then.
3. according to the coding and decoding device of claim 1, it is characterized in that in described decoded portion, described clock processing unit comprises the regeneration shaping circuit, be used for the input data are carried out shaping regeneration; Comprise also being connected being used for phase-locked loop circuit that clock signal is extracted that described clock processing unit is exported regenerate data that shaping obtains and by described phase-locked loop circuit recovered clock signal of described regeneration shaping circuit with regeneration shaping circuit output.
4. according to the coding and decoding device of claim 1, it is characterized in that, in described decoded portion, described string and converting unit comprise shift register, be used for the coded mark inversion code data that receives is carried out 2 bit groupings, form the parallel data of one group of 2 bit, export described decoding sign indicating number type converting unit to.
5. according to the coding and decoding device of claim 1, it is characterized in that, in described decoded portion, described decoding sign indicating number type converting unit is to coded mark inversion code data 01,00 and the coded mark inversion code data 01,11 of pattern 2 and the illegal taboo word 10 that may occur of pattern 1, and the status word output that error code is differentiated that is used for of 0,1,0,1,1 nonreturn to zero code code data output and 000,001,000,010 and 100 is provided respectively.
6. according to the coding and decoding device of claim 1, it is characterized in that, in described decoded portion, the status word that described error monitoring unit provides according to described sign indicating number type converting unit, the status recognition word is 100 o'clock, produce an error code pulse and give described Bit Error Code Statistics unit, described Bit Error Code Statistics unit to error code pulse count, when reaching predetermined value, produce output and adjust pulse.
7. according to the coding and decoding device of claim 1, it is characterized in that, in described decoded portion, described synchronous adjustment unit is adjusted the time window of a bit according to the adjustment pulse from described Bit Error Code Statistics unit to the clock signal of the shift register in described string and the converting unit.
8. according to any one the coding and decoding device among the claim 1-7, it is characterized in that, described pattern control unit in the described coded portion, described coding sign indicating number type converting unit and described parallel serial conversion unit adopt the electrically programmable logical device to realize, the described clock processing unit in the described decoded portion, described string and converting unit, described decoding sign indicating number type converting unit, described error monitoring unit, described Bit Error Code Statistics unit and described synchronous adjustment unit adopt the electrically programmable logical device to realize.
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| CN102916681B (en) * | 2012-10-31 | 2015-04-22 | 电子科技大学 | Pulse width-adjustable NRZ/ RZ (Non-return-to-zero/return-to-zero) code converting device |
| CN102916682B (en) * | 2012-10-31 | 2015-07-15 | 电子科技大学 | Pulse width-adjustable NRZ/ R1 (non-return-to-zero/ return-to-1) code converting device |
| CN104009823B (en) * | 2014-06-02 | 2017-07-07 | 复旦大学 | Dislocation detection and error correction circuit in a kind of SerDes technologies |
| CN106656399A (en) * | 2016-12-05 | 2017-05-10 | 成都瑞科电气有限公司 | Optical fiber-digital synchronous interface system based on FPGA |
| CN108964717B (en) * | 2018-08-02 | 2021-05-28 | 重庆川仪自动化股份有限公司 | NRZ current coding circuit based on single control line |
| CN110380736B (en) * | 2019-06-13 | 2023-04-21 | 华南师范大学 | Novel HDB 3code encoding method, device, equipment and storage medium |
| CN110351000B (en) * | 2019-08-15 | 2020-09-15 | 中国科学院半导体研究所 | All-optical serial-parallel conversion system based on wavelength division multiplexing technology |
| CN115428365B (en) * | 2020-09-11 | 2024-01-23 | Oppo广东移动通信有限公司 | Symbol detection method, device and system |
| CN113438052B (en) * | 2021-06-15 | 2022-09-16 | 深圳市元征未来汽车技术有限公司 | Signal decoding method, device, electronic equipment and storage medium |
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| US524628A (en) * | 1894-08-14 | wright | ||
| US5510786A (en) * | 1994-04-25 | 1996-04-23 | Nec America, Inc. | CMI encoder circuit |
| JPH10135838A (en) * | 1996-10-30 | 1998-05-22 | Fujitsu Ltd | Cmi/nrz conversion circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US524628A (en) * | 1894-08-14 | wright | ||
| US5510786A (en) * | 1994-04-25 | 1996-04-23 | Nec America, Inc. | CMI encoder circuit |
| JPH10135838A (en) * | 1996-10-30 | 1998-05-22 | Fujitsu Ltd | Cmi/nrz conversion circuit |
Also Published As
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| CN1396736A (en) | 2003-02-12 |
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