CN100414908C - Storage network adapter of supporting virtual interface - Google Patents
Storage network adapter of supporting virtual interface Download PDFInfo
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- CN100414908C CN100414908C CNB2005100198583A CN200510019858A CN100414908C CN 100414908 C CN100414908 C CN 100414908C CN B2005100198583 A CNB2005100198583 A CN B2005100198583A CN 200510019858 A CN200510019858 A CN 200510019858A CN 100414908 C CN100414908 C CN 100414908C
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Abstract
The present invention relates to a memory network adapter based on a virtual interface, which belongs to the technical field of computer memory. A virtual interface protocol and a data cache managing function are realized by combining software and hardware in an FPGA chip, and the cost of host computer communication is reduced; consequently, the goals of widening the effective bandwidth of a memory network, accelerating access speed, and enhancing the interconnection and the interoperability of the network are realized, and other goals can be also achieved. The memory network adapter of the present invention comprises a host interface, a system on a chip, an Ethernet interface and a special logic circuit for a virtual interface, wherein the system on a chip is interconnected with the Ethernet interface by the bus line of the system on a chip; the host interface and the system on a chip adopt a communication mechanism with shared memory to realize interconnection and communication. The present invention reduces the cost of node communication, and obtains transmission performance with higher efficiency. The present invention adopts a VIA light level communication protocol, reduces the data copy in the process of communication, and shortens the key path for memorizing data. Ethernet is used as transmission media by the bottom layer of the memory network adapter, and the interconnection and the interoperability with the existing networks are ensured. The cooperative work of software and hardware accelerates the protocol processing process.
Description
Technical field
The invention belongs to computer memory technical field, be specifically related to a kind of storage network adapter, be used to make up storage networking based on virtual interface.
Background technology
The network storage has become the main flow and the focus of storage system applications and research, and it is with traditional memory device (disk, CD, tape library, disk arrays etc.) interconnected by computer network, the formation capacity is bigger, the higher novel storage system that has high availability and high security simultaneously of performance.Except memory device itself, another key factor of decision network store system performance is exactly a network communication and transmission.Existing majority of network storage system all uses ICP/IP protocol to communicate transmission, and TCP/IP itself designs towards the memory system data transmission, and it is more suitable for the transmission of a large amount of small data packets.For the continuous memory system data of bulk, use TCP/IP to transmit, communication overhead is excessive, causes the effective I/O bandwidth of network to reduce, and has influenced the response speed of the network storage.The FC network that another kind is used for storage system then exist cost an arm and a leg, with the problem of existing network compatibility difference; Between the FC network, also exist because the problems such as interoperability that the standard disunity brings.
Virtual Interface Architecture (VIA) is the industrial standard of user class lightweight communications protocol, its design philosophy is: a shielded direct addressable virtual network interface is provided for each consumer process, to save the expense that protocol system is handled in the legacy network pattern; Each virtual interface is represented a communication end point, and two virtual interfaces can couple together the realization point in logic---the some bidirectional data transfers; By the system data area at elimination two ends and the copy between the user data area, to improve the actual data transfer bandwidth.The method that realizes VIA at present comprises that software is realized and hardware is realized two classes, but software realizes that performance is not high, and hardware realizes that cost is higher, and is compatible bad.
Summary of the invention
The present invention proposes a kind of storage network adapter of virtual support interface, by in fpga chip, adopting way of hardware and software combination to realize the virtual interface protocol function, and realize certain metadata cache management function, reduce the communication overhead of main frame to greatest extent, reach the effective bandwidth of expanding storage networking, improve memory access speed, strengthen the purposes such as interconnection interoperability of storage networking.
The storage network adapter of a kind of virtual support interface of the present invention comprises host interface, SOC (system on a chip), Ethernet interface and virtual interface dedicated logic circuit; SOC (system on a chip) and Ethernet interface are by the SOC (system on a chip) bus interconnection; Host interface adopts the communication mechanism of shared drive to realize interconnection and communicate by letter with SOC (system on a chip);
(1) host interface is the interface that communication host and this storage network adapter carry out order, data interaction, when main frame need carry out data communication, send request command by host interface to this storage network adapter, treat after this storage network adapter response again to submit to or from host interface obtaining communication data to host interface;
(2) SOC (system on a chip) comprises embedded core processor, SOC (system on a chip) bus, memory, constitutes an embedded computer system with protocol processes, I/O ability, by carrying out firmware code, cooperates the virtual interface dedicated logic circuit, finishes following function:
(2-1) data send, behind the transmission request virtual interface descriptor that obtains main frame, resolve the logical address and the data length of descriptor acquiring metadata cache, finish the map addresses of metadata cache, obtain the physical address of data, start the data that DMA must transmit from the main frame primary access, form the Virtual Interface Architecture packet and it is packaged into ethernet frame, start Ethernet interface transmission data;
(2-2) Data Receiving, obtain Frame from Ethernet, therefrom parse the virtual interface data packet head, identify data purpose virtual interface, form complete virtual interface packet, find out corresponding reception descriptor from receive descriptor queue, map addresses is obtained purpose user's buffer memory physical address, starts DMA with the reception buffer memory of transfer of data to the user;
(3) Ethernet interface comprises the MAC layer of Ethernet, finishes transmission and reception control to ethernet frame; Its end is connected by system bus with SOC (system on a chip), receives the control of SOC (system on a chip), carries out the transmission and the reception of frame, and the other end provides GMII or MII interface, the convenient access of adopting different Ethernet physical mediums;
(4) the virtual interface dedicated logic circuit is realized by hardware description language in fpga chip inside, the dedicated logic circuit that comprises dma controller and realization virtual interface, DMA transmission, map addresses, the descriptor queue that finishes the storage data manages, descriptor is resolved and the production and the authentication function of check code.
The storage network adapter of described a kind of virtual support interface is characterized in that:
(1) host interface adopts PCI or PCI-X computer external apparatus interface standard;
(2) firmware that supports SOC (system on a chip) is finished the virtual interface protocol function that comprises virtual interface core agency, comprises the cache management scheduling feature module of the system function module of SOC (system on a chip), the module of finishing the Virtual Interface Architecture protocol function and raising storage networking transmission performance;
(2-1) system function module of SOC (system on a chip) comprises the embedded OS and relevant device driver of supporting core processor, wherein relevant device driver realizes the control to ethernet mac, after system power-up resets, be written into the system command code of curing, finish system initialization work according to predetermined configuration, enter normal operating condition then;
(2-2) module of finishing the Virtual Interface Architecture protocol function is downloaded into by the indication of operating system at main frame, with the kernel thread operation, up to receiving that countermanding an order of main frame just withdraw from; This thread cooperates main frame to finish the registration of virtual interface internal memory, create address mapping table, finish encapsulation and decapsulation that the virtual interface bag divides encapsulation and decapsulation, finishes ethernet frame;
(2-3) cache management scheduling feature module is responsible for managing and dispatching accepting the pairing metadata cache of formation and transmit queue, with the virtual interface is that unit carries out dynamic management to the data buffer memory, virtual interface to communications-intensive distributes more buffer memory, otherwise then reduces its buffer memory capacity; Among the data cached RAM that leaves dual-port in, reach executed in parallel to the buffer memory read-write;
(3) shared drive of described host interface and SOC (system on a chip) is divided into two parts, and a part is used to deposit the transmission descriptor, constitutes to send descriptor queue; Another part is used to deposit the reception descriptor, constitutes to receive descriptor queue; Main frame writes descriptor to two formations, SOC (system on a chip) then reads descriptor from two formations, the realization of formation adopts two-port RAM to cooperate the virtual interface dedicated logic circuit to finish with management, whenever write a descriptor, the capital is triggered corresponding descriptor processing logic and is made suitable processing, thereby realizes the doorbell mechanism of Virtual Interface Architecture.
The present invention passes through in fpga chip internal build SOC (system on a chip) (SOC), adopt cooperative work of software and hardware, realize VIA communication protocol, and adopt Ethernet to finish the final agreement transfer of data, thereby constitute a storage networking interface adapter with complete protocol processes function as physical transmission medium.
Realize that by FPGA hardware the VIA agreement has very strong flexibility on Ethernet, pass through software and hardware combining, both can realize the VIA agreement, and can realize traditional ICP/IP protocol again, and guarantee that as transmission medium the equipment of developing has good interconnection interoperability with Ethernet.The agreement full solidification is realized a fpga chip inside, thereby reduced the protocol processes expense of communication host to greatest extent, the communications performance of raising system can effectively be improved main network storage issue such as storage networking bandwidth, memory access speed, interoperability.
Use network adapter of the present invention to can be used for setting up network store systems such as storage networking, distributed storage, OO storage.Different with the legacy network adapter is that its employing is finished VIA or other network communication protocols in fpga chip inside by SOC (system on a chip), and the protocol overhead that former cause communication host is finished is transferred to network interface adapter.
The present invention has the following advantages:
(1) communication overhead of minimizing node obtains network transmission performance more efficiently;
(2) adopt the VIA lightweight communications protocol, reduce the data copy in the communication process, shortened the critical path of network stored data;
(3) bottom adopts Ethernet as transmission medium, has guaranteed the interconnection interoperability of itself and existing network;
(4) cooperative work of software and hardware has been accelerated the processing procedure of agreement.
Description of drawings
Fig. 1 is one embodiment of the present of invention structural representation.
Embodiment
The invention will be further described below in conjunction with Fig. 1.Host interface part 120 adopts the PCI (Peripheral Component Interconnect) of 64 66MHz to realize, can also adopt PCI-X interface more at a high speed and obtains higher speed ability, and 180 is 64 pci interface buses.Core processor 110 adopts the general risc microcontroller Nios II that provides of altera corp to realize, corresponding SOC (system on a chip) bus 150 adopts Avalon switch type bus, memory 130 comprises dual-port static RAM (Static Random Access Memory) 130.1 again, is used for carrying out the mutual of order (descriptor) with main frame; The relative bigger synchronous dynamic ram (Synchronous Dynamic RAM) 130.2 of dual-port static RAM 130.1 capacity is used for the main memory and the metadata cache of processor; Flash memory 130.3 is used for the curing of program and the preservation of configuration information; These modules are cooperated jointly and have been guaranteed the reliability service of SOC (system on a chip).Virtual interface dedicated logic circuit 160 modules comprise the dedicated logic circuit of dma controller and realization VI among the figure, be used to finish the production and the authentication function of DMA transmission, map addresses, descriptor queue's management, descriptor parsing and the check code of storage data, can realize the function of this part in fpga chip inside by hardware description language.Ethernet interface partly comprises key-course (MAC) 140 and physical layer (PHY) 210 two parts.Wherein MAC layer 140 realizes in the FPGA sheet, and its end links to each other with system bus 150, accepts the control of core processor 110, and frame, the receiving data frames being responsible for sending in the metadata cache are stored in corresponding data buffer area; The other end adopts the GMII/MII interface to be connected with PHY layer external chip, physical interface 170 (copper cable or the light) access network based on ethernet that relies on the PHY layer to provide.
It is as follows that data send basic procedure:
1. main frame sends and sends the request descriptor in the descriptor queue of dual-port SRAM 130.1, triggers the doorbell incident simultaneously one time;
2. be subjected to the triggering of doorbell, virtual interface dedicated logic circuit 160 is described symbol and resolves, and obtains the host memory logical address that sends data, pass through address mapping logic, cooperate address mapping table, finish security inspection and map addresses, obtain sending the host memory physical address at data place;
3. according to the descriptor information of resolving, core processor carries out the structure of VI packet header and Ethernet frame head, postamble, and the allocation schedule of metadata cache obtains one 130.2 interior buffer address;
4. according to 2., 3. go on foot the address information that obtains, configuration DMA register starts DMA and carries out transfer of data, produces interrupt signal after finishing, and notifies the main frame transmission to finish;
5. finish as the encapsulation of complete frame and can start the ethernet mac module simultaneously and carry out data and send, up to all frames all send finish till.
The reception of data then is the inverse process of said process.
Claims (2)
1. the storage network adapter of a virtual support interface comprises host interface, SOC (system on a chip), Ethernet interface and virtual interface dedicated logic circuit; SOC (system on a chip) and Ethernet interface are by the SOC (system on a chip) bus interconnection; Host interface adopts the communication mechanism of shared drive to realize interconnection and communicate by letter with SOC (system on a chip);
(1) host interface is the interface that communication host and this storage network adapter carry out order, data interaction, when main frame need carry out data communication, send request command by host interface to this storage network adapter, treat after this storage network adapter response again to submit to or from host interface obtaining communication data to host interface;
(2) SOC (system on a chip) comprises embedded core processor, SOC (system on a chip) bus, memory, constitutes an embedded computer system with protocol processes, I/O ability, by carrying out firmware code, cooperates the virtual interface dedicated logic circuit, finishes following function:
(2-1) data send, behind the transmission request virtual interface descriptor that obtains main frame, resolve the logical address and the data length of descriptor acquiring metadata cache, finish the map addresses of metadata cache, obtain the physical address of data, start the data that DMA must transmit from the main frame primary access, form the Virtual Interface Architecture packet and it is packaged into ethernet frame, start Ethernet interface transmission data;
(2-2) Data Receiving, obtain Frame from Ethernet, therefrom parse the virtual interface data packet head, identify data purpose virtual interface, form complete virtual interface packet, find out corresponding reception descriptor from receive descriptor queue, map addresses is obtained purpose user's buffer memory physical address, starts DMA with the reception buffer memory of transfer of data to the user;
(3) Ethernet interface comprises the MAC layer of Ethernet, finishes transmission and reception control to ethernet frame; Its end is connected by system bus with SOC (system on a chip), receives the control of SOC (system on a chip), carries out the transmission and the reception of frame, and the other end provides GMII or MII interface, the convenient access of adopting different Ethernet physical mediums;
(4) the virtual interface dedicated logic circuit is realized by hardware description language in fpga chip inside, the dedicated logic circuit that comprises dma controller and realization virtual interface, DMA transmission, map addresses, the descriptor queue that finishes the storage data manages, descriptor is resolved and the production and the authentication function of check code.
2. the storage network adapter of a kind of virtual support interface as claimed in claim 1 is characterized in that:
(1) host interface adopts PCI or PCI-X computer external apparatus interface standard;
(2) firmware that supports SOC (system on a chip) is finished the virtual interface protocol function that comprises virtual interface core agency, comprises the cache management scheduling feature module of the system function module of SOC (system on a chip), the module of finishing the Virtual Interface Architecture protocol function and raising storage networking transmission performance;
(2-1) system function module of SOC (system on a chip) comprises the embedded OS and relevant device driver of supporting core processor, wherein relevant device driver realizes the control to ethernet mac, after system power-up resets, be written into the system command code of curing, finish system initialization work according to predetermined configuration, enter normal operating condition then;
(2-2) module of finishing the Virtual Interface Architecture protocol function is downloaded into by the indication of operating system at main frame, with the kernel thread operation, up to receiving that countermanding an order of main frame just withdraw from; This thread cooperates main frame to finish the registration of virtual interface internal memory, create address mapping table, finish encapsulation and decapsulation that the virtual interface bag divides encapsulation and decapsulation, finishes ethernet frame;
(2-3) cache management scheduling feature module is responsible for managing and dispatching accepting the pairing metadata cache of formation and transmit queue, with the virtual interface is that unit carries out dynamic management to the data buffer memory, virtual interface to communications-intensive distributes more buffer memory, otherwise then reduces its buffer memory capacity; Among the data cached RAM that leaves dual-port in, reach executed in parallel to the buffer memory read-write;
(3) shared drive of described host interface and SOC (system on a chip) is divided into two parts, and a part is used to deposit the transmission descriptor, constitutes to send descriptor queue; Another part is used to deposit the reception descriptor, constitutes to receive descriptor queue; Main frame writes descriptor to two formations, SOC (system on a chip) then reads descriptor from two formations, the realization of formation adopts two-port RAM to cooperate the virtual interface dedicated logic circuit to finish with management, whenever write a descriptor, the capital is triggered corresponding descriptor processing logic and is made suitable processing, thereby realizes the doorbell mechanism of Virtual Interface Architecture.
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| CNB2005100198583A CN100414908C (en) | 2005-11-22 | 2005-11-22 | Storage network adapter of supporting virtual interface |
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Families Citing this family (25)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1858227A1 (en) * | 2006-05-16 | 2007-11-21 | THOMSON Licensing | Network storage device with separated control and storage data interfaces |
| CN101163133B (en) * | 2006-10-10 | 2011-06-29 | 天津中科蓝鲸信息技术有限公司 | Communication system and method of implementing resource sharing under multi-machine virtual environment |
| CN1997033B (en) * | 2006-12-28 | 2010-11-24 | 华中科技大学 | A protocol for network storage and its system |
| CN101340568B (en) * | 2007-07-02 | 2012-08-22 | 同方威视技术股份有限公司 | Data collecting system |
| CN101520797B (en) * | 2009-02-11 | 2011-02-16 | 国网电力科学研究院 | High-speed concurrent access method for power system large data files across platform |
| CN101599294B (en) * | 2009-05-11 | 2012-01-25 | 曙光信息产业(北京)有限公司 | Method for storing multiple virtual queues data based on FPGA |
| CN102193742A (en) * | 2010-03-05 | 2011-09-21 | 零壹科技股份有限公司 | Virtual storage device and control method thereof |
| US8966199B2 (en) | 2010-03-17 | 2015-02-24 | Nec Corporation | Storage system for data replication |
| CN102467472B (en) * | 2010-11-08 | 2015-01-28 | 中兴通讯股份有限公司 | System-on-chip (SoC) chip boot startup device and SoC chip |
| CN102594660B (en) * | 2012-01-19 | 2015-09-09 | 华为技术有限公司 | A kind of virtual interface exchange method, Apparatus and system |
| CN103514125B (en) * | 2012-06-25 | 2016-06-08 | 宏碁股份有限公司 | Main control electronic device and main control end operational approach |
| CN103546231B (en) * | 2012-07-10 | 2018-10-23 | 南京中兴新软件有限责任公司 | A kind of control method and device of Ethernet service air interface transmission delay variation |
| CN103150278B (en) * | 2013-03-05 | 2014-03-05 | 中国人民解放军国防科学技术大学 | Submission method of descriptor of network interface card (NIC) based on mixing of PIO (process input output) and DMA (direct memory access) |
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| CN104717152B (en) * | 2013-12-17 | 2019-07-19 | 深圳市中兴微电子技术有限公司 | A kind of method and apparatus realizing interface caching and dynamically distributing |
| CN104655438B (en) * | 2014-12-17 | 2017-08-29 | 中广核核电运营有限公司 | Nuclear fuel loads and unloads the detecting system and method for storage system |
| CN105808502B (en) * | 2014-12-29 | 2019-09-13 | 杭州华为数字技术有限公司 | System on chip |
| CN106598752B (en) * | 2016-11-15 | 2020-05-12 | 北京大学深圳研究生院 | Remote zero-copy method |
| TWI705374B (en) * | 2017-01-23 | 2020-09-21 | 威鋒電子股份有限公司 | Electronic apparatus and operation method thereof |
| WO2019056380A1 (en) * | 2017-09-25 | 2019-03-28 | 华为技术有限公司 | Data access method and device |
| CN112347028A (en) * | 2020-09-24 | 2021-02-09 | 深圳市紫光同创电子有限公司 | Data processing method and system based on FPGA |
| CN112445728B (en) * | 2020-11-30 | 2023-07-21 | 中科院软件研究所南京软件技术研究院 | Robot development board ROS communication system supporting multiple hardware interfaces |
| CN113434089B (en) * | 2021-06-29 | 2022-08-16 | 苏州科达科技股份有限公司 | Data moving method and device and PCIE system |
| CN113691397B (en) * | 2021-08-12 | 2023-10-20 | 江苏杰瑞信息科技有限公司 | Low-delay 5G wireless transparent transmission method for industrial control data transmission |
| CN117493236B (en) * | 2023-12-28 | 2024-03-01 | 苏州元脑智能科技有限公司 | FPGA accelerator and accelerator system |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1324462A (en) * | 1998-10-19 | 2001-11-28 | 英特尔公司 | Raid striping using multiple virtual channels |
| US6360282B1 (en) * | 1998-03-25 | 2002-03-19 | Network Appliance, Inc. | Protected control of devices by user applications in multiprogramming environments |
| US6738821B1 (en) * | 1999-01-26 | 2004-05-18 | Adaptec, Inc. | Ethernet storage protocol networks |
| US20040170196A1 (en) * | 2000-06-13 | 2004-09-02 | Intel Corporation | Synchronization of network communication link |
-
2005
- 2005-11-22 CN CNB2005100198583A patent/CN100414908C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6360282B1 (en) * | 1998-03-25 | 2002-03-19 | Network Appliance, Inc. | Protected control of devices by user applications in multiprogramming environments |
| CN1324462A (en) * | 1998-10-19 | 2001-11-28 | 英特尔公司 | Raid striping using multiple virtual channels |
| US6738821B1 (en) * | 1999-01-26 | 2004-05-18 | Adaptec, Inc. | Ethernet storage protocol networks |
| US20040170196A1 (en) * | 2000-06-13 | 2004-09-02 | Intel Corporation | Synchronization of network communication link |
Non-Patent Citations (2)
| Title |
|---|
| 基于VIA的存储局域网的设计与研究. 陈俭喜，冯丹，张江陵.小型微型计算机系统，第26卷第9期. 2005 |
| 基于VIA的存储局域网的设计与研究. 陈俭喜，冯丹，张江陵.小型微型计算机系统，第26卷第9期. 2005 * |
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