CN100413058C - Interposer and interposer producing method - Google Patents
Interposer and interposer producing method Download PDFInfo
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- CN100413058C CN100413058C CNB2005800009842A CN200580000984A CN100413058C CN 100413058 C CN100413058 C CN 100413058C CN B2005800009842 A CNB2005800009842 A CN B2005800009842A CN 200580000984 A CN200580000984 A CN 200580000984A CN 100413058 C CN100413058 C CN 100413058C
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
An interposer producing method comprises the steps of forming a seed layer (14) in the opening in a through-hole (13) on the back (12) side of a base plate (10), forming a plating electrode layer (15) on the basis of the seed layer (14), and forming a plated layer (16) on the face (11) side of the base plate (10) to fill the through-hole (13). As a result, it is possible to provide an interposer producing method in which the production process is easy and no blowhole is produced in the through-hole.
Description
Technical field
The present invention relates to interconnect conductive layers (Interposer) and manufacture method thereof, particularly in through hole, do not produce the interconnect conductive layers and the manufacture method thereof of interruption (Pinch-off).
Background technology
The interconnect conductive layers that in the past was provided with via in substrate for example is documented in the Japanese documentation spy and opens in the 2004-165291 communique.
Disclose a kind of ceramic substrate according to this communique, this ceramic substrate lamination the tellite that is configured to certain Butut and has a plurality of through holes of having filled electroconductive component be configured to identical with it Butut and have the tellite of the different through hole of a plurality of diameters, in this ceramic substrate, electroconductive component is constituted as its diameter and becomes big continuous or interimly or reduce from another surperficial side of a surperficial side direction.
Fig. 9 is when in silicon substrate 60 via being set and making interconnect conductive layers, is used to illustrate the sectional view of the silicon substrate 60 of problem points in the past.With reference to Fig. 9, through hole 91 was set in substrate 80 at first in the past.This moment, through hole 91 was shapes that central portion expand into convex as shown in Figure 9, rather than straight cylindrical.
With respect to this through hole 91, in the surface 81 and the back side 82 of substrate, at first around through hole 91, inculating crystal layer 83,84 is set with sputtering method, be seed crystal with inculating crystal layer 83,84 then, and utilize to electroplate wait formation conductive layer 85,86.
Interconnect conductive layers constituted as mentioned above in the past.Open the 2004-165291 communique according to the Japanese documentation spy,, hole and sandblast so when its perforate, use, thereby have the problem that can not reduce to connect the aperture owing to used ceramic substrate.In addition, owing to need to engage two ceramic substrates, all manufacturing processes are numerous and diverse.
In addition, when using silicon substrate to form through hole, because the central portion of through hole is a convex, and from the surface or the back side inside, diameter is big more, so even want inculating crystal layer is located at the inside of through hole, also can't can both fully form inculating crystal layer up to inside.Therefore, make conductive layer begin growth from inculating crystal layer even provide electroplate to wait, conductive layer also can fully not grown up, so there is not conductive layer in the inside of through hole 91, promptly form so-called " hole " 92, thereby produce the problem that through hole 91 opens circuit or machining accuracy worsens.
Summary of the invention
The present invention makes in view of above-mentioned technical problem, and its purpose is to provide a kind of manufacturing process simple, and can not produce the interconnect conductive layers and the manufacture method thereof of hole in the inside of through hole.
Interconnect conductive layers of the present invention comprises: substrate, its have a surface with relative another surface, a surface, and have from a surface and connect to another surperficial through hole; Inculating crystal layer, it is set at the peristome of through hole of a surperficial side of substrate; Electroplate and use electrode layer, it is set to cover inculating crystal layer; And coating, it extends from electroplating with another surperficial side of electrode course, and fills through hole and form.
Interconnect conductive layers of the present invention comprises: inculating crystal layer, and it is set at the peristome of a surperficial side of through hole; Electroplate and use electrode layer, it is set to cover inculating crystal layer; And coating, it extends from electroplating with another surperficial side of electrode course, and fills through hole and form by electroplating, and therefore, can form coating reliably to another surperficial side from the inculating crystal layer of a surperficial side of substrate.
Consequently, can provide manufacturing process simple, and the inside of through hole can not produce the interconnect conductive layers of hole.
Through hole also can be the shape that central portion expands.In addition, inculating crystal layer, plating can be identical material with electrode layer and coating, also can be the materials that differs from one another.
In another aspect of this invention, the manufacture method of interconnect conductive layers comprises: the step of prepared substrate, described substrate have a surface with relative another surface, a surface; On substrate, form the step of through hole; Form the step of inculating crystal layer at the peristome of the through hole of a surperficial side; And form coating to fill the step of through hole to another surperficial side since the inculating crystal layer of a surperficial side, wherein, the inculating crystal layer since a surperficial side comprises with the step of filling through hole to another surface formation coating: the through hole of a closed surperficial side is electroplated with the step of electrode layer and the step of utilizing electrode layer formation coating to form.
In the manufacture method of interconnect conductive layers, form inculating crystal layer at the peristome of the through hole of a surperficial side of substrate, and begin to form coating to fill through hole to another surperficial side of substrate from this inculating crystal layer.Owing to form conductive layer from another surperficial side of a surperficial side direction of the substrate of through hole reliably by electroplating, so can not produce interruption in the inside of through hole.
Consequently, can provide manufacturing process simple, and the inside of through hole does not produce the manufacture method of the interconnect conductive layers of hole.
Preferably, the step of formation through hole comprises the formation step of the through hole that central portion expands.
And inculating crystal layer, plating can form with identical material with electrode layer and coating, also can form with the material that differs from one another.
According to a further aspect in the invention, interconnect conductive layers has the through hole that is set to the opposite side surface from a side surface; Through hole has first aperture area at a side surface, and have since a side surface to inside gradually less than the area of first aperture area, simultaneously, through hole has second aperture area on the opposite side surface, and has from opposite side surface beginning to inside gradually less than the area of second aperture area; In through hole, be provided with conductive layer.
Owing to have the surperficial through hole that with another surface beginning to inside gradually reduce of aperture area, so fill through hole with conductive layer easily from substrate.
Consequently, can provide manufacturing process simple, and the inside of through hole does not produce the interconnect conductive layers of hole.
Preferred first aperture area is different with second aperture area.
By changing aperture area, can independently set the wiring rule on two surfaces, thereby can strengthen the design freedom of wiring width and lead-in wire method in a surperficial side and another surperficial side.
More preferably, the through hole columned hole portion that has between side surface of substrate and opposite side surface that aperture area equates.
In another aspect of this invention, interconnect conductive layers has the through hole that is set to the opposite side surface from a side surface, through hole has first aperture area at a side surface, and have from a side surface to the opposite side surface, and in through hole, be provided with conductive layer gradually less than the area of first aperture area.
In another aspect of this invention, the manufacture method of interconnect conductive layers comprises: the step of prepared substrate, described substrate have a surface with relative another surface, a surface; By carrying out the step of etching formation through hole, this is etched with and makes aperture area carry out from a surface and another surperficial mode that begins to reduce gradually to inside of substrate; And the step that in through hole, forms conductive layer.
In the manufacture method of interconnect conductive layers, because so that aperture area is etched with the formation through hole from mode that a surface and another surface beginning of substrate reduces gradually to inside, so when forming conductive layer in through hole, portion does not have and interruptedly forms conductive layer within it.
Consequently, can provide manufacturing process simple, and the inside of through hole does not produce the manufacture method of the interconnect conductive layers of hole.
Preferably, in carrying out etching step, so that the different mode of size of the aperture area in the aperture area in the surface and another surface is carried out etching.
More preferably, also be included in the step that a surface of substrate and another form the hole that aperture area equates between surperficial.
According to a further aspect in the invention, the manufacture method of interconnect conductive layers comprises: the step of prepared substrate, described substrate have a surface with relative another surface, a surface; By carrying out the step of etching formation through hole, this is etched with and makes aperture area carry out to the mode that another surface reduces gradually from a surface of substrate; And the step that in through hole, forms conductive layer.
In addition, in carrying out etched step, preferably carry out dry ecthing.In addition, can form conductive layer by evaporation, plating or electroless plating.
Description of drawings
Figure 1A is the substep schematic diagram of manufacture method of the interconnect conductive layers of first execution mode;
Figure 1B is the substep schematic diagram of manufacture method of the interconnect conductive layers of first execution mode;
Fig. 1 C is the substep schematic diagram of manufacture method of the interconnect conductive layers of first execution mode;
Fig. 1 D is the substep schematic diagram of manufacture method of the interconnect conductive layers of first execution mode;
Fig. 2 is the schematic diagram of manufacture method of the interconnect conductive layers of second execution mode;
Fig. 3 A is a shape schematic diagram of using the through hole of third embodiment of the invention;
Fig. 3 B is a shape schematic diagram of using the through hole of third embodiment of the invention;
Fig. 4 A is the substep schematic diagram of manufacture method of the interconnect conductive layers of the 4th execution mode;
Fig. 4 B is the substep schematic diagram of manufacture method of the interconnect conductive layers of the 4th execution mode;
Fig. 4 C is the substep schematic diagram of manufacture method of the interconnect conductive layers of the 4th execution mode;
Fig. 4 D is the substep schematic diagram of manufacture method of the interconnect conductive layers of the 4th execution mode;
Fig. 5 is the sectional view of through hole of the interconnect conductive layers of the 5th execution mode;
Fig. 6 is the sectional view of through hole of the interconnect conductive layers of the 6th execution mode;
Fig. 7 is the stereogram with substrate of cross-sectional configuration shown in Figure 6;
Fig. 8 A is the sectional view of through hole of the interconnect conductive layers of the 7th execution mode;
Fig. 8 B is the schematic diagram of manufacturing step of through hole of the interconnect conductive layers of the 7th execution mode;
Fig. 9 is the schematic diagram of the problem points of interconnect conductive layers in the past.
Embodiment
(1) first execution mode
With reference to the accompanying drawings an embodiment of the invention are described.Figure 1A～Fig. 1 D is the substep schematic diagram of manufacturing process of the interconnect conductive layers of first embodiment of the invention.With reference to Figure 1A～Fig. 1 D, at first prepare to have the silicon substrate 10 at the surface 11 and the back side 12, and through hole 13 (Figure 1A) is set therein.This moment, through hole 13 can be with identical in the past as shown in the figure, and its central portion expand into convex and forms.Under this state, at first on substrate 10, comprise that the inside of through hole 13 forms not shown dielectric film.This dielectric film can be SiO
2, the dielectric film of SiN etc. can form by sputtering method, CVD or oxidation.
Then, be formed with in the back side of substrate 10 12 1 sides dielectric film through hole 13 around, form earlier the barrier layer (not having diagram) of Ti by sputter etc.On this barrier layer, form Cu inculating crystal layer (being the layer of matrix that flows through the electrode of electroplating current) 14 (Figure 1B) by sputter etc. then.Then, based on this Cu inculating crystal layer 14,12 1 sides begin to electroplate from the back side.Thereby carry out this plating until the back side 12 1 side closures of electroplating end joined through hole 13, thereby form the plating electrode layer (Fig. 1 C) that constitutes by Cu coating 15.
Then, use electrode layer 15 as electrode the plating of this Cu, 11 1 sides are carried out the plating of Cu to the surface.Like this, Cu coating is the growth of direction shown in the arrow in Fig. 1 D, thereby obtains coating 16 (Fig. 1 D).
Like this, according to present embodiment,, can not produce hole yet, thereby can make through hole 13 become the Cu conductive layer in inside even form male ports in the inside of through hole 13.
In addition, though in the above-described embodiment Ti is used as the barrier layer, also can omit.
(2) second execution modes
The following describes second execution mode.Fig. 2 is figure corresponding with Fig. 1 D in this execution mode, and its structure is basic identical.With reference to Fig. 2, in second execution mode, through hole 23 is set in silicon substrate 20, and this through hole 23 is filled with electrode layer 25 and coating 26 by inculating crystal layer 24, plating.
In the first embodiment, in silicon substrate, be provided with inculating crystal layer and the coating of Cu, but in the present embodiment, inculating crystal layer 24, plating are not limited to Cu with electrode layer 25 and coating 26, as long as can carry out the plating of Ni, Cr, Au, Ag etc., can select any materials.In addition, inculating crystal layer 24, plating can be changed mutually with the material of electrode layer 25 and coating 26.For example, also available Cu is as inculating crystal layer, and carries out the plating of Au as electroplating with electrode layer with this.
(3) the 3rd execution modes
The following describes the 3rd execution mode of the present invention.Fig. 3 is a shape schematic diagram of using the through hole of present embodiment.In first and second execution modes, apply the present invention in the through hole that central portion is expanded to convex, begin the through hole 32 that reduces gradually to the back side from the surface but the present invention also can be applicable to the diameter in columned through hole 31 (Fig. 3 A) and hole in substrate 30.
In the above-described embodiment, be that the example that silicon substrate is used as substrate is described, but be not limited to this, also can use the insulated substrate of glass substrate and sapphire substrate and so on.Do not need to form above-mentioned dielectric film in this case.
In the above-described embodiment, be to describe, but be not limited thereto that also available electroless plating is imbedded to use electroplating the situation of carrying out imbedding electric conducting material to through hole.
(4) the 4th execution modes
The following describes the 4th execution mode of the present invention.Fig. 4 A～Fig. 4 D is the substep schematic diagram of manufacturing process of the interconnect conductive layers of four embodiment of the invention.With reference to Fig. 4 A～Fig. 4 D, in the present embodiment, at first prepare to have the silicon substrate 40 (Fig. 4 A) at the surface 41 and the back side 45.Begin to carry out dry ecthing from surface 41 1 sides then, thereby form the diameter hole 42 that 41 beginnings reduce gradually to inside from the surface in a surperficial side in the precalculated position on the surface 41 of substrate 40.Specifically, the etched etching condition of appropriate combination isotropic etching and anisotropy carries out etching.
Then, a side forms hole 46 overleaf, and its diameter is that the back side 45 beginnings from substrate 40 reduce gradually to inside equally, and, make the two center of hole 42 and hole 46 at the cardinal principle central portion basically identical of substrate 40.
Like this, form through hole 49 in substrate 40, its diameter reduces (Fig. 4 B) from surface 41 and the back side 45 beginnings gradually to inside.
Under this state, at first on substrate 40, comprise that the inside of through hole 49 forms not shown dielectric film.This dielectric film can be SiO
2, the dielectric film of SiN etc. can form by sputtering method, CVD or oxidation.
Then on dielectric film, the inside by sputtering at through hole 49 and with the adjacent surface 41 of through hole 49 and the back side 45 on form inculating crystal layer 43 (Fig. 4 C) as the seed crystal of coating.At this moment, because through hole 49 is not to become big to inside like that in the past, so form inculating crystal layer 43 in the inside of through hole 49 and the peristome periphery at the surface 41 that is attached thereto and the back side 45 easily.
Then, on the basis of this inculating crystal layer 43,47, through hole 49 is electroplated or electroless plating, thus the conductive layer 44 (Fig. 4 D) of formation Cu etc.Consequently, can have the interconnect conductive layers of conductive layer with the formation of simple manufacturing process, and this conductive layer does not produce hole in the inside of through hole 49.
In the above-described embodiment, be that the situation that a through hole 49 is arranged is described, but the situation that is provided with a plurality of through holes 49 also is the same.
In addition, also can consider to form the through hole that same inside has inclination by wet etching.But if adopt wet etching, then the inclination meeting of through hole is excessive, thereby the shape that can't obtain expecting.On the contrary, if adopt dry ecthing, then control the inclination of through hole easily, thereby can access the inclination of expection.
(5) the 5th execution modes
The following describes the 5th execution mode of the present invention.Fig. 5 is the sectional view that the substrate of fifth embodiment of the invention is shown, and it is corresponding to Fig. 4 B of the 4th execution mode.In the 4th execution mode, be the both sides from silicon substrate 20 to be begun to carry out etched situation describe.In the present embodiment, as shown in Figure 5, form through hole 51 by only beginning to carry out etching from surface one side of silicon substrate 20, the diameter in this hole only begins to reduce gradually to inside from the surface or the back side one side of substrate 50.Then by the solid conductive material of the method identical, thereby make through hole 51 become the conductivity through hole at through hole 51 with Fig. 4 A～Fig. 4 D.
This moment is identical with the 4th execution mode, also forms inculating crystal layer and conductive layer based on this easily, and obtains the effect identical with the 4th execution mode.
(6) the 6th execution modes
The following describes other execution mode of the present invention.Fig. 6 is the sectional view of substrate 60 that the interconnect conductive layers of sixth embodiment of the invention is shown, and it is corresponding to Fig. 4 B in the 4th execution mode.
In this embodiment, though identical with the 4th execution mode, form diameter and begin the hole 63,64 that diminishes to inside from surface 61 1 sides of substrate 60 and the back side 62 1 sides respectively, different on surface 61 with diameter on the back side 62.
That is, with reference to Fig. 6, substrate 60 has thickness t, and the diameter of surface 61 1 sides is a, and the diameter of the back side 62 1 sides is b, and a＜b, and simultaneously, the degree of depth of hole 63 on internal direction of surface 61 1 sides is t1, and the degree of depth of hole 64 on internal direction of the back side 62 1 sides is t2.Consequently, form shoulder 68 in the inside of substrate 60.Identical with the 4th execution mode in addition, by beginning to carry out etching in inside with different diameters respectively with the back side 62 from surface 61, thereby both sides form through hole 69 at an arbitrary position, also can form the structure that shoulder 68 is not set as shown in phantom in FIG. thus.After the processing, fill up the inside of through hole 69 with conductive layer like this.
Fig. 7 is the stereogram with substrate 60 of cross-sectional configuration shown in Figure 6.With reference to Fig. 7, in this embodiment, owing to determine the diameter of through hole 69 in surface 61 1 sides and the back side 62 1 sides as mentioned above, so have the wiring zone 67 of Duoing than the back side 62 1 sides in surface 61 1 sides.Therefore the wiring rule of surface 61 1 sides and the back side 62 1 sides can be independently set, thereby the design freedom of wiring width and lead-in wire method can be strengthened in surface 61 1 sides.In addition overleaf in 62, owing to can design the peristome of through hole 39 with large scale, thus can carry out the cast of electroplate liquid well, the depth-width ratio when reducing to deep-cut etc., and can strengthen and connect wiring and handle window (Process Window).
In Fig. 7, wiring 65 is to carry out via the terminal 66b, the 66c that are located on liner 63b, the 63c in addition, and wherein said liner 63b, 63c are formed at the surface of imbedding the conductive layer in the hole 63.
(7) the 7th execution modes
The following describes the 7th execution mode of the present invention.Fig. 8 A is the schematic diagram of the cross-sectional configuration of the substrate 70 in the present embodiment.With reference to Fig. 8 A, in this embodiment, in the surface 71 and the back side 75 of substrate 70, through hole 76 has hemispheric peristome 72,74, and is provided with columned hole 73 at central portion.
Can be by through hole 76 be made as the cast that above-mentioned shape is improved electroplate liquid, and can expect to improve tack.In addition, can expect that the electroplating film that suppresses to adhere to peels off.
Execution mode with the front is identical then, finishes through hole by electroplating with conductive material filling through hole 76.
The following describes the manufacture method of the through hole 76 of present embodiment.Fig. 8 B is the operation schematic diagram that is used to form through hole 76 shown in Fig. 8 A.With reference to Fig. 8 B, on the surface 71 of substrate 70, place resist layer 77, and peristome is set in the precalculated position, carry out isotropic etching then.Form hemispheric peristome 72 in surface 71 1 sides thus.75 1 sides also form hemispheric peristome 74 equally, overleaf.Carry out anisotropy afterwards and be etched with the columned hole 73 of formation.
In addition, also can adopt the generation type in the hole cylindraceous in the present embodiment in each execution mode shown in front.
In the above-described embodiment, being that the situation of having used circle or columned through hole is described, but being not limited thereto, also can be rectangle or polygon.
In the above-described embodiment, be that the situation of utilizing plating to form conductive layer on inculating crystal layer is described, but be not limited thereto, also can only form inculating crystal layer.
In the above-described embodiment, be to carry out describing, but be not limited thereto, also can fill by electroless plating or vacuum evaporation to the situation of through hole filled conductive material to using to electroplate.
In the above-described embodiment, be that the formation that utilizes dry ecthing to carry out through hole is described, but be not limited thereto, also can utilize wet etching.
Industrial applicibility
In the manufacture method of interconnect conductive layers of the present invention, owing to open from a side of through hole substrate Beginning forms conductive layer to opposite side reliably by electroplating, so the method can be used as in through hole Section does not produce the manufacture method of the interconnect conductive layers of interruption and effectively utilizes.
Claims (8)
1. interconnect conductive layers comprises:
Substrate, its have a surface with relative another surface, a described surface, and have from a described surface and connect to another surperficial through hole;
Inculating crystal layer, it is set at the peristome of through hole of described one a surperficial side of described substrate;
Electroplate and use electrode layer, it is set to cover inculating crystal layer; And
Coating, it extends with described another the surperficial side of electrode course from described plating, and fills described through hole and form.
2. interconnect conductive layers as claimed in claim 1, wherein, described through hole is the shape that central portion expands.
3. interconnect conductive layers as claimed in claim 1, wherein, described inculating crystal layer, described plating are identical material with electrode layer and described coating.
4. interconnect conductive layers as claimed in claim 1, wherein, described inculating crystal layer, described plating are the material that differs from one another with electrode layer and described coating.
5. the manufacture method of an interconnect conductive layers comprises:
The step of prepared substrate, described substrate have a surface with relative another surface, a described surface;
Form the step of through hole at described substrate;
Form the step of inculating crystal layer at the peristome of the through hole of described one a surperficial side; And
Begin to form coating from the inculating crystal layer of described one a surperficial side, and fill the step of through hole to described another surperficial side,
Wherein, begin to form coating to described another surperficial side from the inculating crystal layer of described one a surperficial side, and the step of filling through hole comprises again: the through hole of closed described one a surperficial side is to form the step of electroplating with electrode layer; And utilize described electrode layer to form the step of coating.
6. the manufacture method of interconnect conductive layers as claimed in claim 5, wherein, the step that forms described through hole comprises the step that forms the through hole that central portion expands.
7. the manufacture method of interconnect conductive layers as claimed in claim 5, wherein, described inculating crystal layer, described plating are identical material with electrode layer and described coating.
8. the manufacture method of interconnect conductive layers as claimed in claim 5, wherein, described inculating crystal layer, described plating are the material that differs from one another with electrode layer and described coating.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004199785A JP4298601B2 (en) | 2004-07-06 | 2004-07-06 | Interposer and manufacturing method of interposer |
| JP199870/2004 | 2004-07-06 | ||
| JP199785/2004 | 2004-07-06 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810089719 Division CN101256999B (en) | 2004-07-06 | 2005-07-05 | Interposer and manufacturing method for the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1842914A CN1842914A (en) | 2006-10-04 |
| CN100413058C true CN100413058C (en) | 2008-08-20 |
Family
ID=35797727
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005800009842A Expired - Fee Related CN100413058C (en) | 2004-07-06 | 2005-07-05 | Interposer and interposer producing method |
| CN 200810089719 Expired - Fee Related CN101256999B (en) | 2004-07-06 | 2005-07-05 | Interposer and manufacturing method for the same |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810089719 Expired - Fee Related CN101256999B (en) | 2004-07-06 | 2005-07-05 | Interposer and manufacturing method for the same |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP4298601B2 (en) |
| CN (2) | CN100413058C (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8736066B2 (en) * | 2010-12-02 | 2014-05-27 | Tessera, Inc. | Stacked microelectronic assemby with TSVS formed in stages and carrier above chip |
| JP5809476B2 (en) * | 2011-07-29 | 2015-11-11 | 新明和工業株式会社 | Film forming apparatus and film forming method |
| JP2013077807A (en) * | 2011-09-13 | 2013-04-25 | Hoya Corp | Method for manufacturing substrate and method for manufacturing wiring board |
| JP6286169B2 (en) * | 2013-09-26 | 2018-02-28 | 新光電気工業株式会社 | Wiring board and manufacturing method thereof |
| JP6458429B2 (en) * | 2014-09-30 | 2019-01-30 | 大日本印刷株式会社 | Conductive material filled through electrode substrate and method for manufacturing the same |
| JP7022365B2 (en) * | 2017-03-24 | 2022-02-18 | 大日本印刷株式会社 | Through Silicon Via Board and Its Manufacturing Method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000150701A (en) * | 1998-11-05 | 2000-05-30 | Shinko Electric Ind Co Ltd | Semiconductor device, connection board used therefor, and manufacture thereof |
| JP2003078080A (en) * | 2001-08-30 | 2003-03-14 | Fujitsu Ltd | Thin film circuit board, manufacturing method therefor, via formed substrate and manufacturing method therefor |
| US6583058B1 (en) * | 1998-06-05 | 2003-06-24 | Texas Instruments Incorporated | Solid hermetic via and bump fabrication |
| JP2004047667A (en) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | Multilayer wiring board and its manufacturing method |
| JP2004158744A (en) * | 2002-11-08 | 2004-06-03 | Fujitsu Ltd | Selective insulating method and mounting substrate provided with through via |
-
2004
- 2004-07-06 JP JP2004199785A patent/JP4298601B2/en not_active Expired - Fee Related
-
2005
- 2005-07-05 CN CNB2005800009842A patent/CN100413058C/en not_active Expired - Fee Related
- 2005-07-05 CN CN 200810089719 patent/CN101256999B/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6583058B1 (en) * | 1998-06-05 | 2003-06-24 | Texas Instruments Incorporated | Solid hermetic via and bump fabrication |
| JP2000150701A (en) * | 1998-11-05 | 2000-05-30 | Shinko Electric Ind Co Ltd | Semiconductor device, connection board used therefor, and manufacture thereof |
| JP2003078080A (en) * | 2001-08-30 | 2003-03-14 | Fujitsu Ltd | Thin film circuit board, manufacturing method therefor, via formed substrate and manufacturing method therefor |
| JP2004047667A (en) * | 2002-07-11 | 2004-02-12 | Dainippon Printing Co Ltd | Multilayer wiring board and its manufacturing method |
| JP2004158744A (en) * | 2002-11-08 | 2004-06-03 | Fujitsu Ltd | Selective insulating method and mounting substrate provided with through via |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101256999A (en) | 2008-09-03 |
| JP2006024649A (en) | 2006-01-26 |
| JP4298601B2 (en) | 2009-07-22 |
| CN101256999B (en) | 2011-05-11 |
| CN1842914A (en) | 2006-10-04 |
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