CN100410871C - Digital signal processor applying skip type floating number operational method - Google Patents

Digital signal processor applying skip type floating number operational method Download PDF

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CN100410871C
CN100410871C CNB031330401A CN03133040A CN100410871C CN 100410871 C CN100410871 C CN 100410871C CN B031330401 A CNB031330401 A CN B031330401A CN 03133040 A CN03133040 A CN 03133040A CN 100410871 C CN100410871 C CN 100410871C
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number representation
representation
jump
data
great
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CN1570847A (en
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雷永群
陈玉铢
张佑齐
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MediaTek Inc
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MediaTek Inc
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Abstract

The present invention provides a digital signal processor which is used for processing a plurality of batches of digital data with a fixed point number representation or a skipping floating point number representation. The digital signal processor comprises a multiplying circuit, a displacement extracting device, a plurality of representation converting circuits and a calculating unit, wherein the multiplying circuit is used for multiplying two pieces of low-order digit digital data to generate one piece of high-order digit digital data; the displacement extracting device is electrically connected with the multiplying circuit, and is used for converting the high-order digit digital data with the skipping floating point number representation into a piece of high-order digit digital data with the fixed point number representation; each representation converting circuit converts a piece of digital data between the fixed point number representation and the skipping floating point number representation; the calculating unit is used for calculating the batches of digital data.

Description

Use the Digital System Processor of great-jump-forward floating point arithmetic method
Technical field
The present invention relates to a kind of Digital System Processor and correlation technique of handling many stroke numerals data, be particularly related to a kind of great-jump-forward floating point arithmetic method (Jumping Floating Point Arithmetic) of utilizing, many stroke numerals data made the Digital System Processor and the correlation technique of conversion and computing between a certain point number representation and a great-jump-forward floating number representation.
Background technology
Since nearly ten years, fast development along with very large scale integration technology and counter technology, the an urgent demand that bury at the real time digital signal place, electronic information industry released one after another various function patterns Digital System Processor (Digital Signal Processor, DSP).These Digital System Processors generally have advantages such as dirigibility is good, degree of accuracy is high, powerful.The application of Digital System Processor is very wide, yet in fact, a processor can not satisfy all or most application demands fully, and the design engineer all needs to take all factors into consideration according to factors such as the complexity of performance, cost, degree of integration, exploitation and power consumptions when selecting Digital System Processor.
Summary, Digital System Processor all are to be used for handling numerical data, but different Digital System Processors has different characteristics, are applicable to different application.General Digital System Processor can be divided into fixed point numerical expression (Fixed Point DSP) and floating-point numerical expression Digital System Processor (Floating Point DSP), and such differentiation is according to the pattern of the handled numerical data of Digital System Processor and corresponding operation method.Fixed point numerical expression Digital System Processor uses the fixed-point number operation method, handled numerical data adopts fixed-point number representation (Fixed Point Representation), " fixed-point number " is meant the stationkeeping of the radix point in numerical data, and the numerical data with fixed-point number representation is promptly looked the position of radix point wherein respectively, can be expressed as the decimal form between integer or-1.0 to+1.0.Floating-point numerical expression Digital System Processor then uses the floating point arithmetic method, handled numerical data adopts floating number representation (Floating PointRepresentation), and numerical tabular is shown as the form of a mantissa (Mantissa) and same index (Exponent): mantissa * 2 IndexThe floating point arithmetic method is a kind of than the complex calculations rule, utilize the floating number representation can realize numerical data is expanded to sizable Data Dynamic scope, therefore the broad numerical range and the character of pinpoint accuracy, declared publicly the huge market potential that floating-point numerical expression Digital System Processor is contained, but under the situation of considering reasons such as cost and power consumption, the application of fixed point numerical expression Digital System Processor on general consumption electronic products will be possessed firm advantage.
See also Fig. 1, Fig. 1 is the functional block diagram of known fixed point numerical expression Digital System Processor 10 1 embodiment.This (fixed point numerical expression) Digital System Processor 10 can be used to handle many numerical datas with fixed-point number representation, that is these numerical datas have comprised integer (Integer) and two kinds of expressions of decimal pattern, in addition, in the present embodiment, these numerical datas are according to the number of itself shared figure place, be divided into the numerical data of n position and the numerical data of 2n position, n is the integer greater than zero.Digital System Processor 10 includes a data receiver 12, a mlultiplying circuit (Multiplication Circuit) 16, one multiplication gearshift (Multiplication Shifter) 18,1 first gearshift 14, one second gearshift 24, selects computing module (Multiplexing Arithmetic Module) 20, one storage device (Storage Instrument) 22 and one data to write end 26.Data receiver 12 usefulness causes, one storer or other external circuit receive the numerical data of a most n position, data receiver 12 is also sent the numerical data of two n positions in the mlultiplying circuit 16 to, mlultiplying circuit 16 can multiply each other the numerical data with two n positions of fixed-point number representation, produce one and have the numerical data of the 2n position of fixed-point number representation, then be electrically connected in the multiplication gearshift 18 of mlultiplying circuit 16, according to this numerical data is the pattern of integer or decimal, suitably adjust the position of the radix point of the numerical data of 2n position after multiplying each other, produce first numerical data of a 2n position.Simultaneously, data receiver 12 is sent to the numerical data of a n position in first gearshift 14, first gearshift 14 will have the numerical data of this n position of fixed-point number representation, extend program (Sign Extension) through a basic sign, produce one and have second numerical data of the 2n position of fixed-point number representation.With the scale-of-two positive number (n=8) with one 8: (00010100) is converted to one 16 scale-of-two positive number (n=16) is example, as long as high byte is filled up zero just can, that is, eight positions of a high position are partly filled 0, become (00,000,000 00010100), but if during with two complement representation negatives, extended eight positions all will be filled out 1, for example one 8 scale-of-two negative (11101100) can utilize eight positions will extending all to fill 1 to obtain (1111111111101100).
Select computing module 20 to comprise a selecting arrangement 19 and an arithmetic element (Arithmetic Unit) 21, selecting arrangement 19 is electrically connected in first gearshift 14 and multiplication gearshift 18, be used between first numerical data of 2n position and second numerical data, selecting one output, when reality was implemented, selecting arrangement 19 can use a multiplexer (Multiplexer) to finish.Arithmetic element 21 is electrically connected in selecting arrangement 19, be used for receiving (the 2n position) first numerical data or second numerical data selected, and arithmetic element 21 comprises another input end, be used for receiving the 3rd numerical data of the 2n position of transmitting by storage device 22, thus, arithmetic element 21 can be carried out the function of various computings to the numerical data (the 3rd numerical data and first or second numerical data) of this a little 2n position, next, the 4th numerical data of the 2n position after arithmetic element 21 outputs are handled is to storage device 22, the function of storage device 22 promptly is used for storing through selecting the many stroke numerals data after computing module 20 is handled, and when reality was implemented, storage device 22 can be finished by an accumulator (Accumulator).At last, second gearshift 24 will have the digital data conversion of 2n position of fixed-point number representation for still having the numerical data of a n position of fixed-point number representation, and write end 26 by data this numerical data with n position of fixed-point number representation is write in aforesaid memory storage or other device.
The key concept and the framework of above-mentioned known technology about fixed point numerical expression Digital System Processor 10 have had relevant description in many known patent.People such as Kiuchi are at US Patent 5,884,092, in " Systemfor maintaining fixed-point data alignment within a combination CPU and DSPsystem ", under the framework of similar above-mentioned fixed point numerical expression Digital System Processor 10, numerical data at the integer pattern proposes a simple and easy correction method (Correction Process) especially, utilize the relevant information of instruction (Instruction) handled numerical data of prompting when the position, can avoid the displacement operation (Shift Operation) of unnecessary burden and increase the speed that operates.And also have many about the known patent of fixed-point number operation method, as people such as Takano at US Patent 5,524,089, notion with mantissa and index in the floating number representation in " Logarithm computing circuitfor fixed point numbers " is applied in the fixed-point number operation method, and be conceived on the transition operation of scale-of-two and decimal number value representation, in the hope of the area and the complexity of reduction interlock circuit.
By above-mentioned known technology as can be known, fixed point numerical expression Digital System Processor still exists the problem that some utmost points need improve when being commonly industry and accepting and use.The main target market of many now fixed point numerical expression Digital System Processors is built-in applied systems; the capacity of the storer in this application need be generally little; and the fixed point numerical expression Digital System Processor 10 of Fig. 1 is under the situation of the less storer fit applications of the capacity of planting therewith; during the fixed-point number computing of being correlated with, just often have quantization error (Quantization Error) and take place.Please consult Fig. 1 again, the numerical data of two n positions is after mlultiplying circuit 16 multiplies each other among Fig. 1, product is the numerical data of 2n position, again after a succession of processing, if second gearshift 24 will be the numerical data of n position with the digital data conversion with 2n position of fixed-point number representation, with in the storer that is stored in the n position time, numerical data in this 2n position is under the situation of decimal pattern, then must get n position higher in the numerical data of this 2n position, hang down the n position and cast out, and give up in the process of figure place in this time, make easily between the numerical data of the numerical data of the n position after the conversion and original 2n position and produce error.For example 48 of one (the binary law representations) under sexadecimal notation are: 0x004444ffffff, if utilize cast out lower 24 with after being converted to 24 numerical data, become 0x004444, numerical value 0x004444000000 after known fixed-point number operation method reduction obviously has huge difference with former numerical value again, promptly causes above-mentioned quantization error.This quantization error may cause on the digital signal size discontinuous, the distortion, with other bad effect, become the restriction of known fixed point numerical expression Digital System Processor 10 on usefulness.If the desire utilization increases the figure place of Digital System Processor or uses floating-point numerical expression Digital System Processor instead in the hope of improving quantization error, the thing followed is the significantly increase of hardware cost.In addition, program code that utilize to revise fixed point numerical expression Digital System Processor to be to reduce the method for quantization error, can increase program complexity and consume the operation efficiency of more Digital System Processor.
Summary of the invention
Therefore fundamental purpose of the present invention provides a kind of Digital System Processor that utilizes a great-jump-forward floating point arithmetic method, and provides a kind of novel great-jump-forward floating number representation to handle and many stroke numerals of computing data, to address the above problem.
In the present invention, we are based on known fixed-point number representation, and after the part key concept with reference to the floating number representation, a kind of one novel great-jump-forward floating number representation (Jumping FloatingPoint representation is proposed, JFP), and in the framework of Digital System Processor, introduce the notion of great-jump-forward floating number representation, corresponding computer hardware is set, when making a higher count digital data be converted to a lower-order digit numerical data, can finish with the mode of less repeats bits and change and be stored in the storer, and after when the lower-order digit numerical data read back original higher count digital data, can precisely also finish the effect of reduction again efficiently, just can under the situation that does not expend too much extra resource, reduce quantization error thus.
Purpose of the present invention is for providing a kind of Digital System Processor (Digital Signal Processor), be used for handling many stroke numerals data, these many stroke numerals data have a plurality of numeric expressions respectively, these a plurality of numeric expressions include a certain point number representation (Fixed Point Representation) and a great-jump-forward floating number representation (Jumping Floating Point representation) at least, this Digital System Processor includes a mlultiplying circuit (Multiplication Circuit), is used at least two lower-order digit numerical datas are multiplied each other producing a higher count digital data; One extraction gearshift (Extracting/Shifting Device) is electrically connected in this mlultiplying circuit, and a higher count digital data that is used for having this great-jump-forward floating number representation is converted to the higher count digital data with this fixed-point number representation; A plurality of representation change-over circuits (RepresentationConverter), each representation change-over circuit utilizes a great-jump-forward floating point arithmetic method (Jumping FloatingPoint Arithmetic), and a numerical data is changed between this fixed-point number representation and this great-jump-forward floating number representation; And an arithmetic element (Arithmetic Unit), be used for these many stroke numerals data of computing.
Another object of the present invention is for providing a kind of method that is used for a Digital System Processor, and a higher count digital data that is used for having the certain point number representation is converted to the lower-order digit numerical data with a great-jump-forward floating number representation.This method includes (a) order of magnitude according to this higher count digital data, this higher count digital data displacement enlargement (Magnifying Shift) N position that will have this fixed-point number representation, wherein N is the integer more than or equal to zero, and the value of N changes along with the order of magnitude of this higher count digital data; (b) after carrying out step (a), cast out the figure place of a predetermined number in this higher count digital data; And (c) after carrying out step (b), a tail end identification code (Tail Mark) is set, and have this lower-order digit numerical data of this great-jump-forward floating number representation with generation, wherein this tail end identification code is corresponding to the value of N.
Another object of the present invention is for providing a kind of Digital System Processor that is used for handling many stroke numerals data, these many stroke numerals data have a plurality of numeric expressions respectively, these a plurality of numeric expressions include a certain point number representation and a great-jump-forward floating number representation at least, this Digital System Processor includes a data receiver, is used for receiving a most lower-order digit numerical data; One mlultiplying circuit, be electrically connected in this data receiver, the two lower-order digit numerical datas that are used for having this fixed-point number representation multiply each other, generation one has a higher count digital data of this fixed-point number representation, the two lower-order digit numerical datas that perhaps will have this great-jump-forward floating number representation multiply each other, and generation one has a higher count digital data of this great-jump-forward floating number representation; One extraction gearshift is electrically connected in this mlultiplying circuit, and this higher count digital data that is used for having this great-jump-forward floating number representation is converted to the higher count digital data with this fixed-point number representation; One first representation change-over circuit (Representation Converter), be electrically connected in this data receiver, a lower-order digit digital data conversion that is used for having this great-jump-forward floating number representation is the higher count digital data with this fixed-point number representation, and a lower-order digit digital data conversion that perhaps will have this fixed-point number representation is the higher count digital data with this fixed-point number representation; One selects computing module (Multiplexing Arithmetic Module), is electrically connected in this first representation change-over circuit and extraction gearshift, is used for carrying out the function of selection and computing; One storage device is electrically connected in this selection computing module, is used for storing the many stroke numerals data after this selection computing module is handled; One second representation change-over circuit is electrically connected in this storage device, and a higher count digital data that is used for having this fixed-point number representation is converted to the lower-order digit numerical data with this great-jump-forward floating number representation; And one data write end, this lower-order digit numerical data that is used for having this great-jump-forward floating number representation writes a memory storage (Memory Device).
Description of drawings
Fig. 1 is the functional block diagram of an embodiment of known certain point number formula Digital System Processor;
Fig. 2 is the functional block diagram of an embodiment of the present invention's one Digital System Processor;
Fig. 3 is the synoptic diagram with numerical data of great-jump-forward floating number representation of the present invention;
Fig. 4 is the synoptic diagram of Fig. 3 great-jump-forward floating number representation one specific embodiment;
Fig. 5 is the synoptic diagram of another specific embodiment of Fig. 3 great-jump-forward floating number representation;
Fig. 6 is the process flow diagram of the present invention one method embodiment;
Fig. 7 is the process flow diagram of the detailed method embodiment of Fig. 6;
Fig. 8 is the process flow diagram of other method embodiment of the present invention;
Fig. 9 is the functional block diagram of an embodiment of part original paper in Fig. 2 Digital System Processor;
Figure 10 is the functional block diagram of a specific embodiment of Fig. 2 Digital System Processor; With
Figure 11 is the functional block diagram of another specific embodiment of Fig. 2 Digital System Processor.
The reference numeral explanation
10,30,50,70 Digital System Processors, 12,52,72 data receivers
14 first gearshifts, 16,36,56,76 mlultiplying circuits
18 multiplication gearshifts, 19,69,89 selecting arrangements
20,60,80 select computing module 21,31,61,81 arithmetic elements
22,62,82 storage devices, 24 second gearshifts
26,66,86 data write end 33 first representation change-over circuits
34 representation change-over circuits, 35 second representation change-over circuits
37,57,77 extraction equipments, 38,58,78 extraction gearshifts
39,59,79 gearshifts 53 the 3rd representation change-over circuit
55 the 4th representations are changed 73 the 5th representation change-over circuits
Circuit
The conversion of 75 the 6th representations
Circuit
Embodiment
Technical characterictic of the present invention is based on a great-jump-forward floating point arithmetic method (Jumping Floating PointArithmetic), can be with a numerical data at known fixed-point number representation and a great-jump-forward floating number representation (Jumping Floating Point representation of the present invention, JFP) change contingent quantization error when reducing the numerical value conversion between.Therefore (Digital Signal Processor DSP), then can handle and computing has the numerical data of fixed-point number representation and great-jump-forward floating number representation simultaneously and possess the Digital System Processor of the technology of the present invention feature.See also Fig. 2, Fig. 2 is the functional block diagram of an embodiment of the present invention's one Digital System Processor 30.As previously mentioned, Digital System Processor 30 of the present invention can be handled the numerical data with fixed-point number representation and great-jump-forward floating number representation, and in the present embodiment, numerical data can be divided into higher count digital data (can correspond to the numerical data of 2n position among Fig. 1) and lower-order digit numerical data (can correspond to the numerical data of n position among Fig. 1) again according to the number of figure place, and when reality is implemented, the figure place that numerical data had does not limit, two kinds of not only above-mentioned higher count digital data and lower-order digit numerical datas.Digital System Processor 30 includes a mlultiplying circuit (MultiplicationCircuit) 36, an extraction gearshift (Extracting/Shifting Device) 38, representation change-over circuit (Representation Converter) 34, one arithmetic element (Arithmetic Unit) 31.Mlultiplying circuit 36 can be used to two lower-order digit numerical datas are multiplied each other and produces a higher count digital data, and extraction gearshift 38 is electrically connected in mlultiplying circuit 36, and a higher count digital data that is used for having great-jump-forward floating number representation is converted to the higher count digital data with fixed-point number representation.Representation change-over circuit 34 comprises one first representation change-over circuit 33 and one second representation change-over circuit 35, first and second representation change-over circuit 33,35 all can be used great-jump-forward floating point arithmetic method of the present invention, respectively the numerical data that it received is changed between fixed-point number representation and great-jump-forward floating number representation.Arithmetic element 31 and extraction gearshift 38, the first representation change-over circuit 33, and the second representation change-over circuit 35 interconnect, can be used to computing and be sent to wherein numerical data, and be not defined as unfixed point number representation and great-jump-forward floating number representation by arithmetic element 31 handled numerical datas.
Please note, the quantity of representation change-over circuit 34 does not limit and (can not only comprise first and second representation change-over circuit 33,35), also the function of each representation change-over circuit 34 can be designed to " digital data conversion that will have the fixed-point number representation is the numerical data with great-jump-forward floating number representation " or " digital data conversion that will have great-jump-forward floating number representation is the numerical data with fixed-point number representation " respectively, thus, the representation change-over circuit 34 that can will have the particular conversion function, look practical situation and install to be arranged at and anyly in the Digital System Processor 30 of the present invention have this conversion to need part, receive the numerical data that also output has great-jump-forward floating number representation or fixed-point number representation.This has also declared publicly simultaneously, in the Digital System Processor 30 of above-mentioned present embodiment, first and second representation change-over circuit 33,35 is not fixed with the array mode that is connected of other inter-module, need not to link to each other with arithmetic element 31, can do flexible interconnecting with computing flow process and other nextport hardware component NextPort of numerical data as limiting among Fig. 2.For example, if user's desire will through arithmetic element 31 handle and output after a higher count digital data with this fixed-point number representation, be converted to a lower-order digit numerical data to write in the external memorizer, then can be designed to the second representation change-over circuit 35 to possess the function of " this higher count digital data with this fixed-point number representation is converted to the lower-order digit numerical data with great-jump-forward floating number representation of the present invention ", and because the technical characterictic that great-jump-forward floating point arithmetic method of the present invention has low quantization error, can make to write between the lower-order digit numerical data and original higher count digital data in the external memorizer that the error that is caused because of conversion minimizes.
After roughly understanding the basic framework of Digital System Processor of the present invention, technical characterictic for the function mode of certain understanding Digital System Processor of the present invention, just must disclose great-jump-forward floating number representation and great-jump-forward floating point arithmetic method proposed by the invention earlier in detail, and introduce how the corresponding hardware framework is set in the present invention to use great-jump-forward floating point arithmetic method, finish Digital System Processor with the complete technical characterictic of the present invention.Great-jump-forward floating number representation of the present invention is a kind of novel numeric expression between known fixed-point number representation and floating number representation, great-jump-forward floating number representation is based on the decimal form that in the fixed-point number representation numerical data is expressed as between-1.0 to+1.0, and quote the notion of floating number representation, use one to be used as the index (Exponent) of this numerical data, and this index is called tail end identification code (Tail Mark) in the present invention to several.Remaining position then is a mantissa (Mantissa) in the numerical data.The key concept of great-jump-forward floating number representation is: have the shared figure place of tail end identification code in the numerical data of great-jump-forward floating number representation, can adjust with the former numerical values recited of the numerical data before the conversion, when the former numerical value before the conversion is big, the tail end identification code is occupied less bits, and when former numerical value hour, the position of too much repeating can occupy the higher figure place place of former numerical value, and then allow the tail end identification code occupy than multidigit this moment, with the position of too much repeating in the former numerical data of a large amount of replacements.See also Fig. 3, Fig. 3 is the synoptic diagram of an embodiment with numerical data DA of great-jump-forward floating number representation of the present invention.This numerical data DA is made of a flag (Sign bit), the bit data that accounts for maximum figure places and a tail end identification code.As previously mentioned, the shared figure place of tail end identification code is not fixed; Flag is the most significant digit among the numerical data DA for this reason, judgement as sign symbol, when flag is 0, numerical data DA be on the occasion of, when flag was 1, numerical data DA then was a negative value, and less and when need judging the position of repeating in the former numerical data at former numerical value, promptly be to play (most significant digit of bit data) inferior to the next bit place of flag among the numerical data DA thus, will with flag have identical place value (1 or 0) the position) the position be considered as repetition the position.
Please later contrast Fig. 2, numerical data with representation shown in Figure 3 can correspond to the alleged lower-order digit numerical data with great-jump-forward floating number representation of the present invention of Fig. 2 embodiment, and as can be known by the description of Fig. 2, the numerical data DA of Fig. 3 promptly is the higher count digital data that has a fixed-point number representation by original, utilizes great-jump-forward floating point arithmetic method conversion back of the present invention and gets.Ask for an interview Fig. 4, Fig. 4 is the synoptic diagram of Fig. 3 great-jump-forward floating number representation one specific embodiment.The figure place of shown numerical data is made as 24 among Fig. 4 embodiment, and this representation that numerical data had of 24 is called one " deciding exponent number great-jump-forward floating number representation (Regular JFP) ", its a kind of in the great-jump-forward floating number representation of the present invention, situation is described below in detail.This numerical data of 24 is to be converted by a higher count digital data with fixed-point number representation in the present embodiment, and the figure place of this higher count digital data can be made as 48 or other and be high figure place than 24.For example, when if desire is converted to one 48 numerical data (having the fixed-point number representation) with pattern shown in Figure 4 one 24 s' numerical data, great-jump-forward floating point arithmetic method can be according to the order of magnitude of this numerical data of 48, with this numerical data displacement enlargement of 48 (Magnifying Shift) N position, the value of N changes along with the order of magnitude of this numerical data of 48, when the absolute value of this numerical data of 48 is healed big, the value of N is littler, and when absolute value more hour, the value of N is then bigger.Above-mentioned " deciding exponent number great-jump-forward floating number representation " comprises multi-component-level mode shifter, and fixing every component level mode shifter is wanted the figure place of displacement enlargement, in Fig. 4 embodiment, we are fixing to move 4 every single order displacement model multidigit, under the situation that displacement model is made as quadravalence (zeroth order S0 to the three rank S3), the quadravalence displacement model S0-S4 figure place of displacement enlargement respectively is 0,4,8,12.This kind is made as the representation of fixed value with the figure place of every component level displacement enlargement that mode shifter is desired, and is the basic technical features that present embodiment " is decided exponent number great-jump-forward floating number representation ".
Please continue to consult Fig. 4, and contrast Fig. 3 simultaneously as can be known, numerical data under each component level mode shifter all comprises a flag, the value of this flag is identical with flag in original 48 numerical data, and with 48 digital data conversion when having " deciding exponent number great-jump-forward floating number representation " 24 numerical data, utilize exactly other position in this flag and this 48 the numerical data is compared, with selected one specific displacement model and the N value corresponding with it.For asking the picture clear display, we are with the number (having represented four under the binary representation under sexadecimal notation) of a hexadecimal representation: 0x004444ffffff is an example, first three figure place 004 of sexadecimal notation has been represented 12 figure places 000000000010 under the binary representation, leftmost is flag, there are nine 0 after the flag, because these nine 0 is the position of repeating with flag, therefore contrast the result behind Fig. 4, displacement model then can be made as the second component level mode shifter S2, represented the conversion process in displacement enlargement 8 positions.Next, in order with 48 digital data conversion to be 24 numerical data, must add tail end identification code at last again by giving up 24 than the low level place corresponding to the second component level mode shifter S2.Note that as shown in Figure 4 the tail end identification code is the caudal end (lowest order place) that is arranged at 24 numerical data, its shared figure place is unfixing, and each component level mode shifter corresponds to different tail end identification codes respectively.Present embodiment is divided into quadravalence with displacement model, therefore utilize 3 positions (position 0, position 1, and position 2) to go at most as the tail end identification code, when former (48 numerical data) when numerical value is very big, great-jump-forward floating point arithmetic method is not done the operation of any displacement enlargement to former numerical value, only last position (position 0) put on 1 and served as a mark at it, is considered as zeroth order displacement model S0; And at the first component level mode shifter S1, former numerical value is little than zeroth order displacement model S0, therefore need behind 48 the original numerical data displacement enlargement 4 (be equal to and multiply by 24), 22 positions of getting the high bit place in the position 23 of 24 numerical data to the position 2 parts. again position 1 and position 0 are labeled as " 10 ", finish the numerical data that meets " deciding exponent number great-jump-forward floating number representation ", in like manner can analogize to the above-mentioned second component level mode shifter S2, and the 3rd component level mode shifter S3 is made as the tail end identification code " 000 " especially, and its special purpose will describe in detail in the back.If be example with 48 numerical data 0x004444ffffff more later, with 8 positions of its displacement enlargement, and by giving up 24 than the low level place, add tail end identification code (100) at last again after, promptly finish 24 numerical data with " deciding exponent number great-jump-forward floating number representation ": 0x4444fc.
Note that the tail end identification code among the present invention do not limit form, not spacing number is not also limit the position of its setting, only is the preferred embodiment among the present invention in the tail end identification code shown in Fig. 4.Yet, the design of the tail end identification code of present embodiment has many advantages, at first, and in displacement model of judging this number by the tail end identification code why during rank, can be checked by last position (position 0) of this number, be that 1 position can be separated the displacement model of reading this number easily by place value.For example, be all 0 if find the value of position 0, position 1, and the value of position 2 is 1, then this numerical data is the second component level mode shifter S2 as can be known, and its former number 8 positions that in the process of conversion, have been exaggerated displacement; If 2 value is all 0 to the position position 0 again, then this numerical data is the 3rd component level mode shifter S3 as can be known, and its former number has been omitted 12 positions of repeating in the process of conversion.Moreover, the position that no matter in transfer process, is omitted (as in the present embodiment by giving up 24 than the low level place) why, because the minimum value (00000 of any number in the binary representation ... 0) with maximal value (11111 ... 1) mean value is (10000 ... 0), therefore, (have only the most significant digit value is 1 to the pattern of this kind tail end identification code, all the other are 0) can represent the mean value of the figure place that in transfer process, is omitted, the value after the omission and the difference of original value are minimized, thus, when the numerical data that these is had Fig. 4 representation imposes partial arithmetic, the tail end identification code specially need not be rejected, be considered as holistic numerical value and the tail end identification code included in.Can guess and know, to be made as the purpose of " 000 " corresponding to the tail end identification code of the 3rd component level mode shifter S3 in the present embodiment, promptly be that to avoid former (48 numerical data) numerical value be 0 o'clock, any tail end identification code that contains place value 1 may cause mistake in computing, not making originally is that 0 numerical value is not 0 numerical data in generation through changing after.
Great-jump-forward floating number representation of the present invention also comprises one " indefinite exponent number great-jump-forward floating number representation (Non-Regular JFP) ", slightly be different from " deciding exponent number great-jump-forward floating number representation " shown in Figure 4, this kind representation is not fixed the figure place of the displacement enlargement that every component level mode shifter increased, and sees also Fig. 5.Fig. 5 is the synoptic diagram of another specific embodiment of Fig. 3 great-jump-forward floating number representation.The key concept of " indefinite exponent number great-jump-forward floating number representation " shown in Figure 5 is still identical with Fig. 4 embodiment, be still numerical data with this seniority (as 48) according to its absolute value displacement enlargement N position, and the absolute value of working as former number is bigger, the value of N is littler, when the absolute value of former number more hour, the value of N is then bigger, to omit the position of too much repetition, can keep how effective position simultaneously.Ask for an interview Fig. 5, present embodiment " deciding exponent number great-jump-forward floating number representation " also wraps quadravalence displacement model (N0-N3), and zeroth order displacement model N0 to the three component level mode shifter N3 respectively the figure place of displacement enlargement be 0,3,7,12, no longer as last embodiment (arithmetic series) design 0,4,8,12.Except the figure place of the defined displacement enlargement of each component level mode shifter and on-fixed increased by 4, the technical characterictic of present embodiment was all identical with Fig. 4 embodiment haply, and the function of flag and tail end identification code also can correspond to the description among Fig. 4 embodiment.
In fact, no matter be the embodiment of Fig. 4 or Fig. 5, the exponent number of displacement model is not defined as quadravalence, for example, in Fig. 4 embodiment, can add quadravalence displacement model, the 5th component level mode shifter ... or the like.Follow the key concept of " deciding exponent number great-jump-forward floating number representation ", can suppose that each component level mode shifter is fixed as the multiple of positive integer P, and the L rank are set altogether, L is one more than or equal to 0 integer, thus, 0 of zeroth order displacement model displacement enlargement, the first component level mode shifter displacement enlargement P position, up to the then scalable displacement of L component level mode shifter (L-1) * P position, as long as (L-1) value of * P is less than the total bit of former number.Certainly,, mean that the shared figure place of tail end identification code also must increase thereupon, could fully replace the position of the repetition of volume in the former numerical data if the exponent number of displacement model increases.In addition, no matter be embodiment from Fig. 4 or Fig. 5, all can find out when former numerical value is big more, the tail end identification code of occupying few more figure place is being represented and is being kept in the how former more numerical value effectively position, relative, former numerical value more hour, with the bigger situation of former numerical value by contrast, as if occupying more after the conversion, the tail end identification code of long number has kept less effective position, in fact, at former numerical value hour, the tail end identification code can be utilized and replace a large amount of positions of repeating, and has kept in the how former numerical value effective more effectively.Thus, great-jump-forward floating point arithmetic method of the present invention can be possessed more significance bit in the preceding higher count digital data of conversion when one (having the fixed-point number representation) higher count digital data (as above-mentioned 48 numerical data) is converted to (having a great-jump-forward floating number representation) lower-order digit numerical data (as 24 numerical data).That is, numerical data before and after conversion all has under the situation of identical total bit, compare with known fixed-point number representation, great-jump-forward floating number representation can make the computing of relevant Digital System Processor obtain higher degree of accuracy, also need not the too high complexity of floating number representation.
In sum, great-jump-forward floating point arithmetic method of the present invention is applied in the Digital System Processor as Fig. 2, be used for that a higher count digital data with fixed-point number representation is converted to one and have the great-jump-forward floating number representation lower-order digit numerical data of (comprise " deciding exponent number great-jump-forward floating number representation " and reach " indefinite exponent number great-jump-forward floating number representation "), method embodiment after the conclusion can consult Fig. 6, Fig. 6 is the process flow diagram of the present invention one method embodiment, includes the following step:
Step 100: beginning;
Step 102: set multi-component-level mode shifter, each component level mode shifter corresponds to different N value (N is the integer more than or equal to zero) respectively;
Step 104: according to the order of magnitude of this higher count digital data, a selected displacement model, and higher count digital data displacement enlargement (corresponding to this component level mode shifter) the N position that will have the fixed-point number representation, select the cardinal rule of displacement model and N value to be: when the absolute value of original higher count digital data is healed when big, the value of N is littler, when the absolute value of the absolute value of higher count digital data more hour, the value of N is then bigger, simultaneously, N value and displacement model selected is by other position in the higher count digital data and getting therewith of a flag relatively;
Step 106: cast out the figure place of a predetermined number in this higher count digital data, make this higher count digital data after giving up the figure place of this predetermined number, the figure place that it had is identical with the figure place of lower-order digit numerical data;
Step 108: (corresponding to selected displacement model and N value) the tail end identification code that is provided with has the lower-order digit numerical data of great-jump-forward floating number representation with generation;
Step 110: finish the conversion of great-jump-forward floating point arithmetic method.
Embodiment based on above-mentioned Fig. 4, and be foundation with the operating process described in Fig. 6, Fig. 7 has shown that the present invention is one to have a detailed method embodiment of 24 numerical data of great-jump-forward floating number representation with a digital data conversion of 48 with fixed-point number representation.See also Fig. 7, Fig. 7 is the process flow diagram of the detailed method embodiment of Fig. 6, comprises the following step:
Step 200: just begun to provide a numerical data of 48 with fixed-point number representation;
Step 202: whether the absolute value of judging this numerical data of 48 is less than 2 -(4*1)If,, then carry out step 204, if not, then proceed to step 208, a selected m value is 0, and displacement model is set at zeroth order displacement model N0;
Step 204: continue to judge that whether the absolute value of this numerical data of 48 is less than 2 -(4*2)If,, then carry out step 206, if not, then proceed to step 208, selected m value is 1, and displacement model is set at the first component level mode shifter N1;
Step 206: continue to judge that whether the absolute value of this numerical data of 48 is less than 2 -(4*3)If,, then carry out step 208, selected m value is 3, is set at the 3rd component level mode shifter N3, if not, then also proceeds to step 208, but selected m value is 2, is set at the second component level mode shifter N2;
Step 208: according to the order of magnitude of this numerical data of 48, matching step 202 is selected the m value to the running of step 206, and after the m value is selected, carry out step 210;
Step 210: this numerical data of 48 with fixed-point number representation is amplified 2 (4*m)Doubly, just with this numerical data displacement enlargement (4*m) of 48 position;
Step 212: cast out 24 last in this numerical data of 48, become one 24 numerical data;
Step 214: add the tail end identification code of a corresponding m value, when the m value is 0, the value of position 0 is 1; When the m value is 1, the value of position 0 is 0, and the value of position 1 is 1; When the m value is 2, the value of position 0 and position 1 is 0, and the value of position 2 is made as 1; When the m value is 3, position 0, position 1, and the value of position 2 all be made as 0;
Step 216: generation one has 24 numerical data of great-jump-forward floating number representation, finishes the conversion of great-jump-forward floating point arithmetic method.
Great-jump-forward floating point arithmetic method of the present invention a higher count digital data with fixed-point number representation is converted to one have the lower-order digit numerical data of great-jump-forward floating number representation in, this lower-order digit numerical data that also must will have great-jump-forward floating number representation reverts back the higher count digital data with fixed-point number representation, and just complete realization the present invention makes a numerical data technical characterictic of conversion between fixed-point number representation and great-jump-forward floating number representation.When reality is implemented, as long as above-mentioned program is operated with the notion of opposite (Reversed), when conversion, according to the tail end identification code, the lower-order digit numerical data is dwindled displacement (Minifying Shift) N position (N is the integer more than or equal to zero), and according to flag, the value of each in the decision N position, the figure place of augmenting a predetermined number simultaneously is in the lower-order digit numerical data, make this lower-order digit numerical data after augmenting the figure place of this predetermined number, the figure place that it had is identical with the figure place of the higher count digital data of being desired, certainly, the value of each in the figure place of being augmented must be identical with the value of flag, thus, can finish the purpose of reduction.At this, we continue with above-mentioned 24 numerical data with " deciding exponent number great-jump-forward floating number representation ": 0x4444fc (sexadecimal notation) is an example, if desire is converted to the reduction of this numerical data of 24 numerical data of (having the fixed-point number representation) 48, because last place value c of this numerical data of 24 in sexadecimal notation is corresponding to the place value (1100) of 4 under the binary representation, just corresponding to the position 0 among Fig. 4, the value of position 1 is all 0, and the value of position 2 is 1, be equal to the tail end identification code and be (100), after referring back to Fig. 4 embodiment, then this numerical data of decidable belongs to the second component level mode shifter S2, also representative when changing originally displacement enlargement 8.So, this number is dwindled 8 of displacements (is equal to divided by 2 8), and total bit augmented to 48 according to flag (its value is 0), can produce the numerical data 0x004444fc0000 of (having the fixed-point number representation) 48.
Compare as can be known with former several 0x004444ffffff of 0x4444fc, through the numerical value 0x004444fc0000 that restores after the great-jump-forward floating point arithmetic method of the present invention conversion still with former numerical value difference to some extent, but if the known fixed-point number operation method of simple use, 48 numerical data is given up the value (0x004444000000) that back 24 data (becoming 0x004444) restore and get to be compared, can find out that then great-jump-forward floating point arithmetic method of the present invention can effectively reduce the quantization error in the numerical value transfer process, when it is implemented on hardware, can under the situation that does not increase too many extra software and hardware resources, can store and handle numerical data and improve degree of accuracy with less space.
It is one to have a detailed method embodiment of 48 numerical data of fixed-point number representation with a digital data conversion of 24 with great-jump-forward floating number representation that Fig. 8 has described the invention described above.See also Fig. 8, Fig. 8 is the process flow diagram of other method embodiment of the present invention, comprises the following step:
Step 300: just begun to provide a numerical data of 24 with great-jump-forward floating number representation, next carried out step 302 and step 310 simultaneously;
Step 302: judge the value of position 0,, then carry out step 304 if the value of position 0 is 0; If the value of position 0 is 1, then proceed to step 308, a m value is made as 0, also be about to displacement model and be judged as zeroth order displacement model N0;
Step 304: continue to judge the value of position 1,, then carry out step 306 if the value of position 1 is 0; If the value of position 1 is 1, then proceed to step 308, the m value is made as 1, also be about to displacement model and be judged as the first component level mode shifter N1;
Step 306: continue to judge the value of position 2,, then carry out step 308, the m value is made as 3, also be about to displacement model and be judged to be the 3rd component level mode shifter N3 if the value of position 2 is 0; If the value of position 2 is 1, also proceed to step 308, a m value is made as 2, displacement model is judged as the second component level mode shifter N2;
Step 308: according to the tail end identification code in this numerical data of 24, matching step 302 obtains the m value to the inspection step of step 306, and after the m value is selected, carry out step 312;
Step 310: after this numerical data of 24, augment 24 0 value, become one 48 numerical data;
Step 312:,, dwindle 2 according to the m value of gained after step 308 with 48 numerical data of gained in the step 310 (4*m)Doubly, just this numerical data of 48 is dwindled displacement (4*m) position;
Step 314: generation one has 48 numerical data of fixed-point number representation, and 48 bit digital data with fixed-point number representation are returned in the 24 bit digital reductions of data that successfully will have great-jump-forward floating number representation.
When above-mentioned all methods of the present invention were applied to implement on the hardware, relevant embodiment can later consult Fig. 2.Because can having the numerical value of fixed-point number representation and great-jump-forward floating number representation therein, handles and computing (computing comprises mathematical operations such as addition subtraction multiplication and division) Digital System Processor 30 of Fig. 2 of the present invention, and can carry out conversion between fixed-point number representation and the great-jump-forward floating number representation form, meaning promptly, Digital System Processor 30 of the present invention can be handled under extremely low quantization error than the lower-order digit numerical data, therefore need not increase the figure place of Digital System Processor, need not use floating-point numerical expression Digital System Processor instead, also need not to revise under the situation of Digital System Processor 30 program codes, just can significantly increase the consistance between operation result and the correct result, and can store lower-order digit numerical data with an external memorizer than low capacity, reduce hardware cost with great-jump-forward floating number representation.
Please consult Fig. 2 embodiment again, in Digital System Processor 30, have three assemblies directly to involve great-jump-forward floating point arithmetic method of the present invention: extract gearshift 38, the first representation change-over circuit 33, reach the second representation change-over circuit 33,35.Wherein first and second representation change-over circuit 33,35 can be carried out the translation function between fixed-point number representation and the great-jump-forward floating number representation, the mode of its running can be fully with reference to above-mentioned Fig. 4 to Fig. 8 embodiment, and extraction gearshift 38 segments according to function, can distinguish again is an extraction equipment 37 and a gearshift 39, ask for an interview Fig. 9, Fig. 9 is the functional block diagram of an embodiment of Fig. 2 Digital System Processor 30 part original papers, include extraction equipment 37, gearshift 39, with mlultiplying circuit 36.If two lower-order digits (n position) numerical data in the input mlultiplying circuit 36 all has great-jump-forward floating number representation, in the process that multiplies each other, bit data as shown in Figure 3, can separate with the tail end identification code and to look it, therefore, mlultiplying circuit 36 can directly multiply each other two lower-order digits (n position) numerical data bit data separately.And this moment, two lower-order digit numerical datas were also sent in the extraction equipment 37, extract tail end identification code separately in this two lower-order digits number (n position) bit data, judge relevant information (as individual other displacement model and N value), then this relevant information is conveyed into gearshift 39, according to displacement model and the N value judged, a seniority (2n position) numerical data that data after will handling via mlultiplying circuit 36 be made corresponding radix point displacement, correct to draw (having the fixed-point number representation).
Circuit structure among Fig. 2 embodiment and on-fixed can adjust according to different demands, and therefore, next we propose the Digital System Processor of an ad hoc structure, fully disclose great-jump-forward floating point arithmetic method of the present invention cooperates utilization with computer hardware situation.See also Figure 10, Figure 10 is the functional block diagram of the specific embodiment of Fig. 2.The Digital System Processor 50 of Figure 10 includes a data receiver 52, a mlultiplying circuit 56, an extraction equipment 57, a gearshift 59, one the 3rd representation change-over circuit 53, a selection computing module 60, a storage device 62, one the 4th representation change-over circuit 55 and data and writes end 66.Data receiver 52 can receive many numerical datas with n position of great-jump-forward floating number representation, mlultiplying circuit 56 is electrically connected in data receiver 52, be used for receiving two numerical datas with n position of great-jump-forward floating number representation, mlultiplying circuit 56 also can multiply each other the numerical data of this two n position, generation has the numerical data of the 2n position of great-jump-forward floating number representation, after handling via extraction equipment 57 and gearshift 59 (extraction equipment 57 can merge be considered as an extraction gearshift 58) again, draw the 5th numerical data of 2n position with fixed-point number representation with gearshift 59.At the same time, the 3rd representation change-over circuit 53 that is electrically connected in data receiver 52 also receives one and has the numerical data of the n position of great-jump-forward floating number representation, according to the tail end identification code and the flag of the numerical data of this n position, the digital data conversion that is used for this n position is the 6th numerical data with 2n position of fixed-point number representation.Select computing module 60 to comprise a selecting arrangement 69 and an arithmetic element 61, selecting arrangement 69 is electrically connected in the 3rd representation change-over circuit 53 and gearshift 59, with cause 2n position the 5th, and the 6th numerical data in select one output, so selecting arrangement 69 can use a multiplexer (Multiplexer) to finish.Arithmetic element 61 is electrically connected in selecting arrangement 69, be used for receiving (the 2n position) the 5th numerical data or the 6th numerical data selected, and arithmetic element 61 comprises another input end, be used for receiving the 7th numerical data of the 2n position of transmitting by storage device 62, thus, arithmetic element 61 can be carried out the function of various computings to these (the 2n position) numerical datas (the 7th, first or second numerical data) with fixed-point number representation.Please note, present embodiment has emphasized that arithmetic element 61 handled numerical datas have fixed-point number and represent, its reason is: the process of a displacement enlargement when conversion of the numerical data with great-jump-forward floating number representation, therefore the position of its radix point is existing changes, make add, the complexity of subtraction is too high, therefore in the present embodiment all numerical datas are converted to the kenel with fixed-point number representation all earlier, send in the arithmetic element 61 in addition computing again.Part as for multiplication, then be easier to handle numerical data with great-jump-forward floating number representation, identical as described above, can respectively the bit data in the numerical data, tail end identification code separately be looked it, when multiplying each other, separately bit data in the two digital data is directly multiplied each other, and the position that utilizes tail end identification code compensation (Compensate) to adjust radix point at last again gets final product.
Next, the 8th numerical data of the 2n position after arithmetic element 61 outputs are handled is to storage device 62, the function of storage device 62 promptly is used for storing through selecting the many stroke numerals data after computing module 60 is handled, and when reality was implemented, storage device 62 can be finished by an accumulator (Accumulator).The digital data conversion that the 4th representation change-over circuit 55 will have the 2n position of fixed-point number representation is the numerical data with n position of great-jump-forward floating number representation, and writes end 66 by data this numerical data with n position of great-jump-forward floating number representation write in the aforesaid memory storage.
For the function of Fig. 1 embodiment is included in the embodiments of the invention, Digital System Processor of the present invention can be handled simultaneously have fixed-point number representation (comprising integer representation method (IntegerRepresentation)), and the data of great-jump-forward floating number representation, in ensuing embodiment, add a start-up control signal (Enabling Control Signal), to switch the function of the assembly that part is relevant with the technology of the present invention feature among Figure 10.See also Figure 11, Figure 11 is the functional block diagram of another specific embodiment of Fig. 2, be similar to Figure 10 embodiment, its Digital System Processor 70 also includes a data receiver 72, a mlultiplying circuit 76, an extraction equipment 77, a gearshift 79, one the 5th representation change-over circuit 73, a selection computing module 80, a storage device 82, one the 6th representation change-over circuit 75 and data and writes end 86.The the 5th and the 6th representation change-over circuit 73,75 can correspond to the 3rd and the 4th representation change-over circuit 53,55 among Figure 10.Most important technical characterictic is that extraction equipment 77, gearshift 79, the 5th representation change-over circuit 73 and the 6th representation change-over circuit 75 all can be connected at least one start-up control signal ES in the present embodiment, and this start-up control signal ES can be used to judge whether to start coupled extraction equipment 77, gearshift 79, the 5th and the 6th representation change-over circuit 73,75.When the numerical data of two n positions that mlultiplying circuit 76 receives has great-jump-forward floating number representation, start-up control signal ES will start extraction equipment 77 and gearshift 79, carry out the running described in Figure 10 embodiment, and when the numerical data of two n positions that mlultiplying circuit 76 is received has the fixed-point number representation, start-up control signal ES does not just start extraction equipment 77 and gearshift 79, after 76 of mlultiplying circuits merely multiply each other the numerical data of this two n position, produce one and have the numerical data of the 2n position of fixed-point number representation, this moment, extraction equipment 77 and gearshift 79 can be considered the multiplication gearshift 18 among the known embodiment of Fig. 1.In like manner, when start-up control signal ES starts the 5th representation change-over circuit 73, the running that the 5th representation change-over circuit 73 is carried out as the 3rd representation change-over circuit 53 among Figure 10, the digital data conversion that will have the n position of great-jump-forward floating number representation is the numerical data with 2n position of fixed-point number representation, but when start-up control signal ES does not start the 5th representation change-over circuit 73, the 5th representation change-over circuit 73 extends program (Sign Extension) via a known basic sign, the digital data conversion that will have the n position of fixed-point number representation is the numerical data with 2n position of fixed-point number representation, at this moment first gearshift 14 of functional equivalent in the known embodiment of Fig. 1 of the 5th representation change-over circuit 73.In like manner, when start-up control signal ES starts the 6th representation change-over circuit 75, the running that the 6th representation change-over circuit 75 is carried out as the 4th representation change-over circuit 55 among Figure 10, the digital data conversion that will have the 2n position of fixed-point number representation is the numerical data with n position of great-jump-forward floating number representation; When start-up control signal ES does not start the 6th representation change-over circuit 75, the 6th representation change-over circuit 75 will have the numerical data of the 2n position of fixed-point number representation and directly give up wherein n position, be converted into the numerical data of n position, at this moment second gearshift 24 of functional equivalent in the known embodiment of Fig. 1 of the 6th representation change-over circuit 76 with fixed-point number representation.
A disclosed novel great-jump-forward floating point arithmetic method and the great-jump-forward floating number representation of the present invention can fundamentally improved the error that produces when value bit is changed, when making a higher count digital data be converted to a lower-order digit numerical data, can finish conversion with the mode of less repeats bits, keep how effective bit value, do not sacrifice precision.And in the framework of Digital System Processor, introduce the notion of great-jump-forward floating number representation of the present invention, and after corresponding computer hardware is set, can be with numerical data to handle and to be stored in the storer than the kenel of lower-order digit, and after when the lower-order digit numerical data read back original higher count digital data, can precisely also finish the effect of reduction again efficiently, just can under the situation that does not expend too much extra resource, reduce quantization error significantly thus.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of patent of the present invention.

Claims (33)

1. Digital System Processor, be used for handling at least one stroke numeral data, these at least one stroke numeral data have a plurality of numeric expressions respectively, these a plurality of numeric expressions include a certain point number representation and a great-jump-forward floating number representation at least, this great-jump-forward floating number representation is expressed as the decimal form with this numerical data, and use one to be used as the index of this numerical data to several, and other position is a mantissa in this numerical data, this Digital System Processor includes:
One mlultiplying circuit, being used at least two lower-order digit numerical datas are multiplied each other produces a higher count digital data;
One extraction gearshift, be electrically connected in this mlultiplying circuit, be used for extracting the index of the numerical data of great-jump-forward floating number representation, judge displacement model and shift value, a higher count digital data that will have this great-jump-forward floating number representation is converted to the higher count digital data with this fixed-point number representation;
A plurality of representation change-over circuits, each representation change-over circuit utilize a great-jump-forward floating point arithmetic method, should at least one stroke numeral data in arbitrary numerical data between this fixed-point number representation and this great-jump-forward floating number representation, change; And
One arithmetic element is used for these at least one stroke numeral data of computing.
2. Digital System Processor as claimed in claim 1, it also comprises a storage device, is electrically connected in this arithmetic element, is used for storing these at least one stroke numeral data.
3. Digital System Processor as claimed in claim 1, wherein this great-jump-forward floating point arithmetic method higher count digital data of being used for having this fixed-point number representation is converted to the lower-order digit numerical data with this great-jump-forward floating number representation, and this lower-order digit digital data conversion that perhaps will have this great-jump-forward floating number representation is this higher count digital data with this fixed-point number representation.
4. Digital System Processor as claimed in claim 3, wherein this great-jump-forward floating point arithmetic method is according to the order of magnitude of this higher count digital data, this higher count digital data displacement enlargement N position that will have this fixed-point number representation, and give up the figure place of predetermined number, one tail end identification code is set again, have this lower-order digit numerical data of this great-jump-forward floating number representation with generation, wherein N is the integer more than or equal to zero.
5. Digital System Processor as claimed in claim 4, wherein the value of N changes along with the order of magnitude of this higher count digital data, heals greatly when the absolute value of this higher count digital data, and the value of N is littler; When the absolute value of this higher count digital data is littler, the value of N is bigger.
6. Digital System Processor as claimed in claim 4, wherein this great-jump-forward floating point arithmetic method includes a plurality of displacement models, and each mode shifter corresponds to different N values respectively.
7. Digital System Processor as claimed in claim 6, wherein each numerical data comprises a flag, the selected and corresponding N value of displacement model by in relatively this flag and this higher count digital data other and get.
8. Digital System Processor as claimed in claim 7, wherein this great-jump-forward floating point arithmetic method is according to this tail end identification code and this flag, and this lower-order digit digital data conversion that will have this great-jump-forward floating number representation is this higher count digital data with this fixed-point number representation.
9. Digital System Processor as claimed in claim 4, wherein in this extraction gearshift, when this two lower-order digits numerical data of this mlultiplying circuit of input all has this great-jump-forward floating number representation, this extraction gearshift is according to the tail end identification code with this two lower-order digits numerical data of this great-jump-forward floating number representation, and this higher count digital data that will have this great-jump-forward floating number representation is converted to this higher count digital data with this fixed-point number representation.
10. Digital System Processor as claimed in claim 1, wherein this extraction gearshift and this a plurality of representation change-over circuits are connected at least one start-up control signal, are used for judging whether respectively to start this extraction gearshift and this a plurality of representation change-over circuits.
11. Digital System Processor as claimed in claim 1, wherein this arithmetic element is used for computing and has these at least one stroke numeral data of this fixed-point number representation.
12. Digital System Processor as claimed in claim 1, it also includes:
One data receiver is used for receiving at least one stroke numeral data; And
One data write end, and at least one lower-order digit numerical data that is used for having this great-jump-forward floating number representation writes a memory storage.
13. method that is used for a Digital System Processor, a higher count digital data that is used for having the certain point number representation is converted to the lower-order digit numerical data with a great-jump-forward floating number representation, this great-jump-forward floating number representation is expressed as the decimal form with this numerical data, and use one to be used as the index of this numerical data to several, other position is a mantissa in this numerical data, and this method includes:
(a) according to the order of magnitude of this higher count digital data, will have this higher count digital data displacement enlargement N position of this fixed-point number representation, wherein N is the integer more than or equal to zero, and the value of N changes along with the order of magnitude of this higher count digital data;
(b) after carrying out step (a), cast out the figure place of a predetermined number in this higher count digital data; And
(c) after carrying out step (b), a tail end identification code is set, have this lower-order digit numerical data of this great-jump-forward floating number representation with generation, wherein this tail end identification code is corresponding to the value of N.
14. method as claimed in claim 13, wherein the absolute value when this higher count digital data is bigger, and the value of N is littler; When the absolute value of this higher count digital data is littler, the value of N is bigger.
15. method as claimed in claim 13, it also comprises:
(d) in step (a), a plurality of displacement models are set, each mode shifter corresponds to different N values respectively;
(e) after carrying out step (d), according to the order of magnitude of this higher count digital data, a selected displacement model and corresponding N value will have the N position that this higher count digital data displacement enlargement of this fixed-point number representation should correspondence; And
(f) in step (c) and after carrying out step (e), a tail end identification code corresponding to this displacement model is set.
16. method as claimed in claim 15, wherein this higher count digital data comprises a flag, and the value of N and this displacement model selected is to be got by other position in relatively this flag and this higher count digital data.
17. method as claimed in claim 16, wherein this lower-order digit numerical data comprises this flag. and have this lower-order digit numerical data of this great-jump-forward floating number representation can be according to this tail end identification code and this flag, reduction becomes this higher count digital data with this fixed-point number representation.
18. method as claimed in claim 13, it also comprises: (g) after carrying out step (c), this lower-order digit numerical data that will have this great-jump-forward floating number representation writes in the memory storage.
19. method that is used for a Digital System Processor, a lower-order digit digital data conversion that is used for having a great-jump-forward floating number representation is the higher count digital data with certain point number representation, this lower-order digit numerical data that wherein has this great-jump-forward floating number representation comprises a tail end identification code, this great-jump-forward floating number representation is expressed as the decimal form with this numerical data, and use one to be used as the index of this numerical data to several, other position is a mantissa in this numerical data, and this method includes:
According to this tail end identification code, this lower-order digit numerical data is dwindled displacement N position, wherein N is the integer more than or equal to zero; And
The figure place of augmenting a predetermined number is in this lower-order digit numerical data.
20. method as claimed in claim 19, wherein this higher count digital data comprises a flag, and this method also comprises:
According to this flag, determine in this N position the value of each; And
According to this flag, the value of each in the figure place of this predetermined number that decision is augmented.
21. method as claimed in claim 19, wherein this tail end identification code includes a plurality of displacement models, and each mode shifter corresponds to different N values respectively, and this method also comprises: according to this tail end identification code, and a selected displacement model and corresponding N value.
22. Digital System Processor that is used for handling at least one stroke numeral data, these at least one stroke numeral data have a plurality of numeric expressions respectively, these a plurality of numeric expressions include a certain point number representation and a great-jump-forward floating number representation at least, this great-jump-forward floating number representation is expressed as the decimal form with this numerical data, and use one to be used as the index of this numerical data to several, other position is a mantissa in this numerical data, and this Digital System Processor includes:
One data receiver is used for receiving at least one lower-order digit numerical data;
One mlultiplying circuit, be electrically connected in this data receiver, the two lower-order digit numerical datas that are used for having this fixed-point number representation multiply each other, generation one has a higher count digital data of this fixed-point number representation, the two lower-order digit numerical datas that perhaps will have this great-jump-forward floating number representation multiply each other, and generation one has a higher count digital data of this great-jump-forward floating number representation;
One extraction gearshift, be electrically connected in this mlultiplying circuit, be used for extracting the index of the numerical data of great-jump-forward floating number representation, judge displacement model and shift value, this higher count digital data that will have this great-jump-forward floating number representation is converted to the higher count digital data with this fixed-point number representation;
One first representation change-over circuit, be electrically connected in this data receiver, a lower-order digit digital data conversion that is used for having this great-jump-forward floating number representation is the higher count digital data with this fixed-point number representation, and a lower-order digit digital data conversion that perhaps will have this fixed-point number representation is the higher count digital data with this fixed-point number representation;
One selects computing module, is electrically connected in this first representation change-over circuit and extraction gearshift, is used for carrying out the function of selection and computing;
One storage device is electrically connected in this selection computing module, is used for storing at least one stroke numeral data after this selection computing module is handled;
One second representation change-over circuit is electrically connected in this storage device, and a higher count digital data that is used for having this fixed-point number representation is converted to the lower-order digit numerical data with this great-jump-forward floating number representation; And
One data write end, and this lower-order digit numerical data that is used for having this great-jump-forward floating number representation writes a memory storage.
23. Digital System Processor as claimed in claim 22, wherein each numerical data comprises a flag.
24. Digital System Processor as claimed in claim 23, wherein each lower-order digit numerical data with this great-jump-forward floating number representation also comprises a tail end identification code.
25. Digital System Processor as claimed in claim 24, wherein this first representation change-over circuit is according to this tail end identification code and this flag with this lower-order digit numerical data of this great-jump-forward floating number representation, and this lower-order digit digital data conversion that will have this great-jump-forward floating number representation is this higher count digital data with this fixed-point number representation.
26. Digital System Processor as claimed in claim 24, wherein this extraction gearshift is according to the tail end identification code of this two lower-order digits numerical data that has this great-jump-forward floating number representation in this mlultiplying circuit, and this higher count digital data that will have this great-jump-forward floating number representation is converted to this higher count digital data with this fixed-point number representation.
27. Digital System Processor as claimed in claim 22, wherein this second representation change-over circuit is according to the order of magnitude of this higher count digital data, this higher count digital data displacement enlargement N position that will have this fixed-point number representation, and give up the figure place of predetermined number, one tail end identification code is set again, have this lower-order digit numerical data of this great-jump-forward floating number representation with generation, wherein N is the integer more than or equal to zero.
28. Digital System Processor as claimed in claim 27, wherein the value of N changes along with the order of magnitude of this higher count digital data, heals greatly when the absolute value of this higher count digital data, and the value of N is littler; When the absolute value of this higher count digital data is littler, the value of N is bigger.
29. Digital System Processor as claimed in claim 22, wherein this extraction gearshift, this first representation change-over circuit and this second representation change-over circuit are connected at least one start-up control signal, are used for judging whether respectively to start this extraction gearshift, this first representation change-over circuit and this second representation change-over circuit.
30. Digital System Processor as claimed in claim 29, wherein when this start-up control signal started this first representation change-over circuit, this lower-order digit digital data conversion that this first representation change-over circuit will have this great-jump-forward floating number representation was this higher count digital data with this fixed-point number representation; When this start-up control signal did not start this first representation change-over circuit, this lower-order digit digital data conversion that this first representation change-over circuit will have this fixed-point number representation was this higher count digital data with this fixed-point number representation.
31. Digital System Processor as claimed in claim 29, wherein when this start-up control signal started this second representation change-over circuit, this higher count digital data that this second representation change-over circuit will have this fixed-point number representation was converted to this lower-order digit numerical data with this great-jump-forward floating number representation; When this start-up control signal did not start this second representation change-over circuit, this higher count digital data that this second representation change-over circuit will have this fixed-point number representation was converted to this lower-order digit numerical data with this fixed-point number representation.
32. Digital System Processor as claimed in claim 22, wherein this selection computing module is used for selecting and at least one higher count digital data with this fixed-point number representation of computing.
33. Digital System Processor as claimed in claim 22, wherein these a plurality of numeric expressions also include an integer representation method.
CNB031330401A 2003-07-23 2003-07-23 Digital signal processor applying skip type floating number operational method Expired - Fee Related CN100410871C (en)

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