CN100407419C - High depth-width ratio open and its manufacturing method - Google Patents
High depth-width ratio open and its manufacturing method Download PDFInfo
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- CN100407419C CN100407419C CN2005101184145A CN200510118414A CN100407419C CN 100407419 C CN100407419 C CN 100407419C CN 2005101184145 A CN2005101184145 A CN 2005101184145A CN 200510118414 A CN200510118414 A CN 200510118414A CN 100407419 C CN100407419 C CN 100407419C
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- layer
- contact
- contact hole
- width ratio
- falling
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Abstract
A method for preparing an opening with high depth-width ratio includes forming a photo-resist pattern with an opening on interlayer dielectric layer and setting said opening right above conduction region, using photo-resist pattern as etching hard mask and contact hole etch-stop layer as dry etch-stop layer, dry-etching said interlayer dielectric layer through opening anisotropy to form top portion of contact hole, removing off photo-resist pattern then dry-etching contact hole etch-stop layer through contact hole top portion isotropy to form widened bottom of contact hole for exposing more area of conduction region.
Description
Technical field
The present invention relates to a kind of method of making the contact hole of semiconductor element, relate in particular to the opening of a kind of making high-aspect-ratio (aspect ratio＞30) or the method for contact hole, the bottom of opening or contact hole can be widened, reduce its contact resistance by this.
Background technology
Along with the progress of semiconductor technology, the microminiaturization of microelectronic element has entered into the deep-submicron grade, and the interval between the big more expression element of the density of the semiconductor element on the one chip is also just more little, and this makes that the making of contact hole is more and more difficult.At present, in dielectric layer, dig out diameter smoothly,, be still the direction that industry is made great efforts to expose the conductive region of the enough areas in below less than 0.1 micron high-aspect-ratio (aspect ratio＞30) contact hole.
The existing contact hole of making all is to utilize the etching mask of photoresist layer as etching below dielectric layer, yet, because photoresist consumption easily in etching environment, therefore, toward contact other etching mask of must arranging in pairs or groups, just can finish the etching of high-aspect-ratio contact hole.And if the photoresist layer is thickened, but the resolution can lose exposure the time, owing to be diameter less than 0.1 micron contact hole pattern, the requirement of its exposure accuracy and precision is strict more.In addition, the macromolecule accessory substance of photoresist layer and etching plasma generation also can impact contact etch.
See also Fig. 1 to Fig. 4, what it illustrated is existing skill is made the high-aspect-ratio contact hole on Semiconductor substrate generalized section.As shown in Figure 1, be formed with MOS transistor element 20 on Semiconductor substrate 10, it includes drain/source zone 12, grid 14 and be located at clearance wall 16 on grid 14 sidewalls.MOS transistor element 20 is also with shallow-channel insulation zone 24 electrical isolation.
On MOS transistor element 20 and Semiconductor substrate 10 surfaces, be coated with contact etch stop layer (contact etch stop layer, CESL) 32, as silicon nitride; Be coated with interlayer dielectric (ILD) layer 34 on contact etch stop layer 32, its thickness is about 2500 dust to the 6000 Izod right sides.Above ILD layer 34, be anti-reflecting layer 36, and be photoresist layer 40 on anti-reflecting layer 36.Utilize photoetching process, in photoresist layer 40, form opening 42.
As shown in Figure 2, then utilize photoresist layer 40, via opening 42 etching anti-reflecting layers 36 and ILD layer 34, up to contact etch stop layer 32, to form opening 52 as etching mask.The etching of aforesaid ILD layer 34 is to utilize anisotropic dry etch technology.
Subsequently, as shown in Figure 3, utilize photoresist layer 40 and anti-reflecting layer 36 again, carry out secondary anisotropic dry etch technology,, so promptly form contact hole 62 via opening 52 etching contact etch stop layers 32 as etching mask.At last, as shown in Figure 4, the remaining etching mask in ILD layer 34 top is removed.
The method that above-mentioned existing skill forms contact hole still has many shortcomings to wait to improve.At first, existing skill etching ILD layer 34 and contact etch stop layer 32 are to continue to carry out under the state of not removing photoresist layer 40, this macromolecule accessory substance that makes photoresist and etching gas produce accumulates in the contact hole, make contact hole profile after the etching present the aspect of downward convergent, thus, the area that the conductive region of below is exposed might be not enough, causes the rising of contact resistance.In addition, existing skill owing to select the deficiency of ratio, can cause damage to the ILD layer in the contact hole in etching contact etch stop layer 32, causes the distortion of contact hole profile.
Hence one can see that, and the method that existing skill forms the high-aspect-ratio contact hole still has many shortcomings to wait to improve, and particularly needs a kind of manufacture method that can reduce the contact holes contact resistance, can not have influence on the contact hole profile that is formed on the ILD layer segment simultaneously again.
Summary of the invention
Main purpose of the present invention is to provide a kind of method for manufacturing contact hole of improvement, with the formation font of falling T, high-aspect-ratio contact hole on Semiconductor substrate, and reduces contact resistance.
According to a preferred embodiment of the invention, the present invention discloses a kind of method of making high depth-width ratio open or contact hole, comprise semi-conductive substrate is provided, has conductive region on it, be covered in the contact etch stop layer on this Semiconductor substrate and this conductive region, and be covered in the interlayer dielectric layer on this contact etch stop layer; On this interlayer dielectric layer, form a photoresist pattern, and this photoresist pattern comprises an opening, its be positioned at this conductive region directly over; Utilize this photoresist pattern as etch hard mask, and utilize this contact etch stop layer to stop layer, carry out anisotropic dry etch technology,, form contact hole first half position via this this interlayer dielectric layer of opening etching for dry ecthing; Remove this photoresist pattern; And carry out isotropic dry etch technology, via this contact hole first half position this contact etch stop layer of isotropic dry etch, and form bottom the contact hole of widening, expose this conductive region of larger area, wherein this contact hole first half position and this contact hole of widening bottom constitutes this high-aspect-ratio contact hole.
In order to make those skilled in the art can further understand feature of the present invention and technology contents, see also following about detailed description of the present invention and accompanying drawing.Yet accompanying drawing is only for reference and aid illustration usefulness, is not to be used for the present invention is limited.
Description of drawings
What Fig. 1 to Fig. 4 illustrated is existing skill is made the high-aspect-ratio contact hole on Semiconductor substrate generalized section;
What Fig. 5 to Fig. 8 illustrated is the present invention makes the high-aspect-ratio contact hole on Semiconductor substrate generalized section;
Fig. 9 illustrates is the enlarged diagram of the bottom of the contact hole shown in the dashed region after finishing metal plug and inserting among Fig. 8.
The main element symbol description
10 Semiconductor substrate, 12 drain/source zones
14 grids, 16 clearance walls
20 MOS transistor elements, 24 shallow-channel insulation zones
32 contact etch stop layers, 34 interlayer dielectric layers
36 anti-reflecting layers, 40 photoresist layers
42 openings, 52 openings
62 contact holes, 66 contact holes
80 dashed region, 92 barrier layers
94 metal levels
Embodiment
See also Fig. 5 to Fig. 8, what it illustrated is the present invention makes high depth-width ratio open on Semiconductor substrate generalized section.Below, so-called " depth-to-width ratio " is meant the ratio of the contact hole degree of depth and contact hole diameter, and alleged herein " high-aspect-ratio " general reference depth-to-width ratio is greater than 30.Opening can refer to contact hole, interlayer hole or groove.Hereinafter, the present invention embodiment of making high depth-width ratio open on Semiconductor substrate explains with contact hole.
What need emphasize is, the preferred embodiment that this paper lifted is to describe as example with the MOS transistor element, yet, it will be understood by those skilled in the art that the present invention also can be used in other enforcement environment that needs the high-aspect-ratio contact hole, for example at the high-aspect-ratio contact hole that needs on the word line or on metal interconnecting to form.
As shown in Figure 5, be formed with MOS transistor element 20 on Semiconductor substrate 10, it includes drain/source zone 12, grid 14 and be located at clearance wall 16 on grid 14 sidewalls.MOS transistor element 20 is also with shallow-channel insulation zone 24 electrical isolation.The metal silicide layer that also can comprise the surface in drain/source zone 12, for example nickel silicide layer (not shown).On MOS transistor element 20 and Semiconductor substrate 10 surfaces, be coated with contact etch stop layer (contact etch stop layer, CESL) 32, as silicon nitride, its thickness is about 200 dust to the 1000 Izod right sides; Be coated with interlayer dielectric (ILD) layer 34 on contact etch stop layer 32, its thickness is about 2500 dust to the 6000 Izod right sides.
Above ILD layer 34 anti-reflecting layer 36, silicon oxynitride (silicon oxy-nitride) for example, its thickness is about 200 dust to the 600 Izod right sides, is preferably 300 dusts; And be photoresist layer 40 on anti-reflecting layer 36.Utilize photoetching process equally, form opening 42 in photoresist layer 40, its diameter D is about about 0.1 micron.
As shown in Figure 6, then utilize photoresist layer 40, via opening 42 etching anti-reflecting layers 36 and ILD layer 34, up to contact etch stop layer 32, to form opening 52 as etching mask.According to a preferred embodiment of the invention, the etching of aforesaid ILD layer 34 is to utilize anisotropic dry etch technology, and with C
4F
6/ O
2/ Ar or C
5F
8/ CO/O
2/ Ar is as etching gas.Because during etching ILD layer 34, the macromolecule accessory substance that photoresist and etching gas produce can accumulate in the contact hole, makes etching after-opening 52 profiles present convergent a little.
As shown in Figure 7, according to a preferred embodiment of the invention, then earlier remaining photoresist layer 40 is divested.In another embodiment, anti-reflecting layer 36 is also removed in the lump.Wherein, divest photoresist layer 40 and can utilize the oxygen gas plasma ashing method, then with existing wet-cleaned technology clean wafers surface.
As shown in Figure 8, after removing photoresist, then carry out isotropism (isotropic) dry etching process, with CH
2F
2/ O
2/ Ar or CHF
3/ O
2/ Ar is as etching gas, and reaction cabin pressure is controlled under the condition more than the 30mTorr, via opening 52 isotropic etching contact etch stop layers 32, so forms the contact hole 66 with contact hole bottom of widening.
Anisotropy that it should be noted that dry etching process mainly is relevant with reaction cabin pressure, if reduce reaction cabin pressure, can make dry etching process than the tool anisotropic properties, otherwise,, can make dry etching process than the tool isotropic characteristics if improve reaction cabin pressure.Contact hole bottom in order to go out to widen with isotropic etching via opening 52 the present invention is characterized in CH
2F
2/ O
2/ Ar is as etching gas, and reaction cabin pressure is controlled under the condition more than the 30mTorr carries out.Because the bottom of contact hole is widened, the area that also makes 12 surfaces, drain/source zone, below come out increases, and reduces contact resistance by this.
See also Fig. 9, it illustrates is the enlarged diagram of contact hole bottom after finishing metal plug and inserting of dashed region 80 among Fig. 8.As shown in Figure 9, after finishing metal plug and inserting, the contact hole bottom presents the font of falling T profile.According to a preferred embodiment of the invention, to insert be to carry out ald (atomic layer deposition, ALD) technology earlier to aforesaid metal plug, at contact hole 66 inwall deposition of thin barrier layers 92, for example titanium/titanium nitride is followed, depositing metal layers 94 fills up contact hole 66.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (40)
1. high depth-width ratio open comprises:
Semi-conductive substrate has a conductive region on it;
One contact etch stop layer covers on this conductive region;
One interlayer dielectric layer covers on this contact etch stop layer;
The one contact hole first half is located in this interlayer dielectric layer, and wherein this contact hole first half has a little tapered profile; And
The one contact hole bottom of widening is located in this contact etch stop layer, and is exposed this conductive region, and wherein this contact hole first half is connected with this contact hole of widening bottom, and constitutes the contact hole of a font of falling T.
2. high depth-width ratio open as claimed in claim 1, wherein this conductive region is a drain/source zone of MOS transistor element.
3. high depth-width ratio open as claimed in claim 2 wherein has a metal silicide layer on this drain/source zone.
4. high depth-width ratio open as claimed in claim 1, wherein this conductive region is an area of grid of MOS transistor element.
5. high depth-width ratio open as claimed in claim 1 wherein also has an anti-reflecting layer on this interlayer dielectric layer.
6. high depth-width ratio open as claimed in claim 5, wherein the thickness of this anti-reflecting layer is 200 dust to 600 dusts.
7. high depth-width ratio open as claimed in claim 5, wherein this anti-reflecting layer comprises silicon oxynitride.
8. high depth-width ratio open as claimed in claim 1, wherein this etching stopping layer comprises silicon nitride.
9. high depth-width ratio open as claimed in claim 1, wherein this interlayer dielectric layer comprises undoped silicon oxygen layer or doping silica layer.
10. method of making high depth-width ratio open comprises:
Semi-conductive substrate is provided, has a conductive region on it, be covered in the etching stopping layer on this Semiconductor substrate and this conductive region, and be covered in the interlayer dielectric layer on this etching stopping layer;
On this interlayer dielectric layer, form a photoresist pattern, and this photoresist pattern comprises a perforate, its be positioned at this conductive region directly over;
Utilize this photoresist pattern as an etch hard mask, and to utilize this etching stopping layer be that a dry ecthing stops layer, carry out an anisotropic dry etch technology,, form an opening first half via this this interlayer dielectric layer of perforate etching;
Remove this photoresist pattern; And
Carry out an isotropic dry etch technology, via this this etching stopping layer of opening first half etching, and form an open bottom of widening, and expose this conductive region of larger area, wherein this opening first half and this open bottom of widening constitute this high depth-width ratio open.
11. the method for making high depth-width ratio open as claimed in claim 10, wherein this conductive region is a drain/source zone of MOS transistor element.
12. the method for making high depth-width ratio open as claimed in claim 11 wherein has a metal silicide layer on this drain/source zone.
13. the method for making high depth-width ratio open as claimed in claim 10, wherein this conductive region is an area of grid of MOS transistor element.
14. the method for making high depth-width ratio open as claimed in claim 10 wherein also has an anti-reflecting layer on this interlayer dielectric layer.
15. the method for making high depth-width ratio open as claimed in claim 14, wherein the thickness of this anti-reflecting layer is 200 dust to 600 dusts.
16. the method for making high depth-width ratio open as claimed in claim 14, wherein this anti-reflecting layer comprises silicon oxynitride.
17. the method for making high depth-width ratio open as claimed in claim 10, wherein this anisotropic dry etch technology is to utilize C
4F
6/ O
2/ Ar or C
5F
8/ CO/O
2/ Ar is as an etching gas.
18. the method for making high depth-width ratio open as claimed in claim 10, wherein this isotropic dry etch technology is to utilize CH
2F
2/ O
2/ Ar or CHF
3/ O
2/ Ar is as an etching gas, and its reaction cabin pressure is controlled at more than the 30mTorr.
19. the method for making high depth-width ratio open as claimed in claim 10, wherein this etching stopping layer comprises silicon nitride.
20. the method for making high depth-width ratio open as claimed in claim 10, wherein this interlayer dielectric layer comprises undoped silicon oxygen layer or doping silica layer.
21. the method for making high depth-width ratio open as claimed in claim 10, wherein after removing this photoresist pattern, other has and carries out a wet-cleaned technology.
22. the method for making high depth-width ratio open as claimed in claim 10, wherein the thickness of this interlayer dielectric layer is 2500 dust to 6000 dusts.
23. the method for making high depth-width ratio open as claimed in claim 10, wherein the thickness of this etching stopping layer is 200 dust to 600 dusts.
24. the font of falling a T contact element comprises:
Semi-conductive substrate has a conductive region, is covered in the contact etch stop layer on this Semiconductor substrate and this conductive region on it, and is covered in the interlayer dielectric layer on this contact etch stop layer;
One has the contact hole first half of a little tapered profile, is formed in this interlayer dielectric layer;
The one contact hole bottom of widening is formed in this contact etch stop layer, and exposes this conductive region, and wherein this contact hole first half and this contact hole of widening bottom constitutes the font of falling a T contact hole;
One ald approaches barrier layer, covers on the inwall of this font of falling T contact hole; And
One metal level fills up this contact hole.
25. the font of falling T contact element as claimed in claim 24, wherein this conductive region is a drain/source zone of MOS transistor element.
26. the font of falling T contact element as claimed in claim 25 wherein has a metal silicide layer on this drain/source zone.
27. the font of falling T contact element as claimed in claim 24, wherein this conductive region is an area of grid of MOS transistor element.
28. the font of falling T contact element as claimed in claim 24, wherein this contact etch stop layer comprises silicon nitride.
29. the font of falling T contact element as claimed in claim 24, wherein the thickness of this contact etch stop layer is 200 dust to 600 dusts.
30. the font of falling T contact element as claimed in claim 24, wherein the thickness of this interlayer dielectric layer is 2500 dust to 6000 dusts.
31. a method that forms the font of falling T contact element comprises:
Semi-conductive substrate is provided, has a conductive region on it, a contact etch stop layer is covered on this conductive region, and an interlayer dielectric layer is covered on this contact etch stop layer;
On this interlayer dielectric layer, form a photoresist pattern, and this photoresist pattern comprises an opening, its be positioned at this conductive region directly over;
Utilize this photoresist pattern as an etch hard mask, and to utilize this contact etch stop layer be that a dry ecthing stops layer, carry out an anisotropic dry etch technology,, form the contact hole first half with a little tapered profile via this this interlayer dielectric layer of opening etching;
Carry out an isotropic dry etch technology, via this this contact etch stop layer of contact hole first half etching, and form a contact hole bottom of widening, and expose this conductive region of larger area, wherein this contact hole first half and this contact hole of widening bottom constitutes the font of falling a T contact hole;
Carry out a technique for atomic layer deposition, deposition one thin barrier layer on an inwall of this font of falling T contact hole; And
In this font of falling T contact hole, fill up a metal level.
32. the method for the formation font of falling T contact element as claimed in claim 31 wherein before carrying out this isotropic dry etch technology, is removed this photoresist pattern.
33. the method for the formation font of falling T contact element as claimed in claim 31, wherein this conductive region is a drain/source zone of MOS transistor element.
34. the method for the formation font of falling T contact element as claimed in claim 33 wherein has a metal silicide layer on this drain/source zone.
35. the method for the formation font of falling T contact element as claimed in claim 31, wherein this conductive region is an area of grid of MOS transistor element.
36. the method for the formation font of falling T contact element as claimed in claim 31, wherein this anisotropic dry etch technology is to utilize C
4F
6/ O
2/ Ar or C
5F
8/ CO/O
2/ Ar is as an etching gas.
37. the method for the formation font of falling T contact element as claimed in claim 31, wherein this isotropic dry etch technology is to utilize CH
2F
2/ O
2/ Ar or CHF
3/ O
2/ Ar is as an etching gas, and its reaction cabin pressure is controlled at more than the 30mTorr.
38. the method for the formation font of falling T contact element as claimed in claim 31, wherein this contact etch stop layer comprises silicon nitride.
39. the method for the formation font of falling T contact element as claimed in claim 31, wherein the thickness of this contact etch stop layer is 200 dust to 600 dusts.
40. the method for the formation font of falling T contact element as claimed in claim 31, wherein the thickness of this interlayer dielectric layer is 2500 dust to 6000 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101184145A CN100407419C (en) | 2005-10-28 | 2005-10-28 | High depth-width ratio open and its manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2005101184145A CN100407419C (en) | 2005-10-28 | 2005-10-28 | High depth-width ratio open and its manufacturing method |
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| Publication Number | Publication Date |
|---|---|
| CN1956184A CN1956184A (en) | 2007-05-02 |
| CN100407419C true CN100407419C (en) | 2008-07-30 |
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| CN2005101184145A Expired - Fee Related CN100407419C (en) | 2005-10-28 | 2005-10-28 | High depth-width ratio open and its manufacturing method |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456676A (en) * | 2012-05-31 | 2013-12-18 | 无锡华润上华科技有限公司 | Contact silicon recess etching method |
| CN108751123B (en) * | 2018-05-21 | 2022-05-20 | 赛莱克斯微系统科技（北京）有限公司 | Method for forming contact window |
| CN114256136B (en) * | 2020-09-22 | 2024-03-26 | 长鑫存储技术有限公司 | Contact window structure, metal plug, forming method of metal plug and semiconductor structure |
| US11929280B2 (en) | 2020-09-22 | 2024-03-12 | Changxin Memory Technologies, Inc. | Contact window structure and method for forming contact window structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010006245A1 (en) * | 1999-12-28 | 2001-07-05 | Takashi Yunogami | Manufacturing method of semiconductor integrated circuit device |
| CN1438681A (en) * | 2002-02-10 | 2003-08-27 | 台湾积体电路制造股份有限公司 | Method for removing stop-layer |
| US20040077178A1 (en) * | 2002-10-17 | 2004-04-22 | Applied Materials, Inc. | Method for laterally etching a semiconductor structure |
| US20050023600A1 (en) * | 2000-01-17 | 2005-02-03 | Samsung Electronics, Co. Ltd | NAND-type flash memory devices and methods of fabricating the same |
| US20050035460A1 (en) * | 2003-08-14 | 2005-02-17 | Horng-Huei Tseng | Damascene structure and process at semiconductor substrate level |
-
2005
- 2005-10-28 CN CN2005101184145A patent/CN100407419C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20010006245A1 (en) * | 1999-12-28 | 2001-07-05 | Takashi Yunogami | Manufacturing method of semiconductor integrated circuit device |
| US20050023600A1 (en) * | 2000-01-17 | 2005-02-03 | Samsung Electronics, Co. Ltd | NAND-type flash memory devices and methods of fabricating the same |
| CN1438681A (en) * | 2002-02-10 | 2003-08-27 | 台湾积体电路制造股份有限公司 | Method for removing stop-layer |
| US20040077178A1 (en) * | 2002-10-17 | 2004-04-22 | Applied Materials, Inc. | Method for laterally etching a semiconductor structure |
| US20050035460A1 (en) * | 2003-08-14 | 2005-02-17 | Horng-Huei Tseng | Damascene structure and process at semiconductor substrate level |
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| CN1956184A (en) | 2007-05-02 |
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