CN100407182C - Apparatus and method for ordering transaction beats in a data transfer - Google Patents
Apparatus and method for ordering transaction beats in a data transfer Download PDFInfo
- Publication number
- CN100407182C CN100407182C CN2006101059489A CN200610105948A CN100407182C CN 100407182 C CN100407182 C CN 100407182C CN 2006101059489 A CN2006101059489 A CN 2006101059489A CN 200610105948 A CN200610105948 A CN 200610105948A CN 100407182 C CN100407182 C CN 100407182C
- Authority
- CN
- China
- Prior art keywords
- request
- data
- bus
- ordering
- order
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Abstract
A microprocessor including a cache memory and bus interface logic. The bus interface logic is interfaced with request signals and data signals and includes a request interface and a response interface. The request interface provides a request via the request signals for a data transaction in which the request specifies a selected burst order. The response interface stores data received via the data signals into the cache memory according to the selected burst order. The request interface may specify the selected burst order by configuring a field of a request packet during a request phase of the data transaction. The selected burst order may selected from any of several different data transaction orderings, including an interleaved order, a linear order, a nibble linear order and a custom order. The microprocessor may further include instruction logic which provides an instruction to the bus interface logic specifying the selected burst order.
Description
Technical field
The present invention relates to the microprocessor issued transaction, be specifically related to a kind of apparatus and method that are used for transmitting in data ordering transaction beats, it has solved because the cache line of non-the best reads to sort and has caused the problem of the dwelling period (stall cycle) that caused by microprocessor.
Background technology
In the current microprocessor such as the microprocessor of x86 compatibility, on system bus, be accomplished to the issued transaction of storer/from the issued transaction (promptly reading and write issued transaction) of storer.These issued transaction comprise request stage and data (i.e. response) stage.During the described request stage, provide the address and the transaction type of issued transaction by the address signal group.Described address signal group generally includes address bus, one group of corresponding address gating signal and asks bus.During described data phase, transmit data corresponding to issued transaction by data signal group.Described data signal group generally includes data strobe signal, response bus (type of indication response) and the bus control signal of data bus, one group of correspondence.In a specific conventional arrangement, described data signal group comprises about 72 signals.Quadruple (quad-pumped) issued transaction is supported in many traditional configurations, wherein, only in several cycles (for example two clock period) of bus or system clock, transmit whole cache line 8 quad words of 64 byte cache-lines (for example for) by bus.During this transmission type, data strobe signal is provided to indicate the validity of each quad word beat on data bus, so that transmit several beats during each bus clock cycle.
In the processor of x86 compatibility, the described request stage is made up of two subs: request A and request B.During request A sub, on described address signal group, emit (put out) issued transaction address and transaction type.During sub B, on described address signal group, emit other data that are associated with issued transaction, such as the attribute and the length thereof of issued transaction (for example the combination that writes to storer writes).
When load is arranged (for example data read request), transmitting critical quad word (promptly at the quad word that its address is provided on the address signal group) during the first beat A during the request A stage, and coming the remaining quad word that sorts for remaining beat B-H according to staggered ordering agreement.For transmission from the cache line of storer, staggered ordering quad word is the artefact of the older memory configurations scheme that can obtain from the DRAM storehouse that substitutes every a quad word (or according to the data entity of any size of bus architecture---for example double word), has got rid of thus usually and obtains the waiting status that two continuation addresses are associated from same DRAM storehouse.Though got rid of waiting status by using staggered ordering in older DRAM design, the improvement of DRAM has made system designer that the ordering of other types can be provided, such as linear ordering as described below.
The current state of the burst tranmission techniques on data bus allows the only transmission ordering of single type.For example, a kind of processor configuration allows staggered ordering, and the configuration of different processors allows linear ordering.The inventor has observed in most of the cases, and from data proximity (proximity), linear ordering is best.Therefore, the system bus of linear ordering provides data to minimize owing to cache line reads the mode that the processing that causes stops.But, though linear ordering may be best in many cases, and in other cases, be very harmful (causing a plurality of streamlines stops) when critical quad word when being the last quad word rather than first quad word.From the data proximity, linear ordering has maximized the quantity that stops, and staggered ordering can provide superior performance.
Therefore, expectation provides a kind of protocol, and the part that its allows the request stage that reads as cache line dynamically specific data entity transmits ordering.Also expectation provides dynamically to specify and transmits ordering, keeps the apparatus and method with existing and traditional bus protocol compatibility simultaneously.And expectation provides that a kind of be used for stipulating can be for the technology of the customization data entity transportation protocol of the dynamic appointment of transmission of cache line or other types.
Summary of the invention
Microprocessor according to one embodiment of the present of invention comprises cache memory and bus interface logic circuit.Described bus interface logic circuit is connected with data-signal with request signal, and comprises request interface and response interface.Request interface is via for the request signal of data transactions and request is provided, and wherein said request interface is specified selected burst order by the field of configuration request packet during the request stage of described data transactions.Response interface will arrive cache memory via the data storage that data-signal receives according to selected burst order.
The described request interface can be specified selected burst order by the field of configuration request packet during the request stage of data transactions.Can select selected burst order from several different data transactions orderings, described several different data transactions orderings are such as staggered ordering, linear ordering, nibble (nibble) linear ordering and customization ordering.Microprocessor can also comprise command logic circuitry, and it provides instruction to specify selected burst order to the bus interface logic circuit.
Request interface can comprise the request logical circuit of specifying selected burst order and be couple to a plurality of request impact dampers of request logical circuit and connection request signal.In one embodiment, the described request logical circuit is by the pre-configured next selected burst order of specifying during initialization.In another embodiment, during initialization, programme the described request logical circuit to specify selected burst order.
Cache bus and ordering logical circuit that response interface can comprise the response buffer that is connected with data-signal, couple with response buffer and cache memory.Described ordering logic circuits coupled is to cache bus, and the data storage that is used for will receiving via response buffer according to selected burst order is to cache memory.Described ordering logical circuit can comprise staggered logical circuit, according to staggered ordering with data storage in cache memory; The linear logic circuit, according to linear ordering with data storage in cache memory; Nibble linear logic circuit, according to the nibble linear ordering with data storage in cache memory; With the customized logic circuit, according to customization ordering and with data storage in cache memory.
Microprocessor Interface system according to one embodiment of the present of invention comprises system bus, microprocessor and the bus agent with request bus and data bus.Microprocessor comprises cache memory, request logical circuit and responsing logic circuit.The request logic circuits coupled is to the described request bus, be provided for the request of the appointment of data transactions for the selected burst order of described data transactions on the described request bus, the field of configuration request packet is to specify described selected burst order and the described request grouping is provided on the described request bus.Responsing logic circuit is connected to cache memory and data bus, and according to selected burst order with the data storage that receives from data bus to cache memory.Bus agent is couple to system bus, receives request, and is provided for the data of data transactions on data bus according to selected burst order.Bus agent can comprise the bus interface logic circuit, and it is configured to be used for the dynamic burst ordering.The field that the request logical circuit can be designed configuration request packet to be specifying selected burst order, and provides the request grouping on the request bus.
Comprise according to one embodiment of the present of invention a kind of method of sorting data beat in data transactions and to use selected burst order to dispose request for data transactions, comprise the field of configuration request packet or according in interleaved order, linear precedence, one that selects in nibble linear precedence and the customization order is come configuring request, the request that will be used for data transactions during request stage is provided to system bus, during the data phase of the correspondence of data transactions, receive data, and store data according to selected burst order from system bus.
Described method can comprise the field of configuration request packet.Described method can comprise according in staggered ordering, linear ordering, nibble linear ordering and the customization ordering selected one come configuring request.Described method can comprise the load instructions that is provided for specifying selected burst order.Described method can comprise uses selected burst order to come pre-configured request logical circuit.Described method can comprise according to selected burst order programming request logical circuit when initialization.Described method can comprise according to selected one in staggered ordering, linear ordering, nibble linear ordering and the customization ordering stores data.
Description of drawings
With reference to following explanation and accompanying drawing, it is clearer that benefit of the present invention, characteristics and advantage will become, wherein:
Fig. 1 is the simplified block diagram of conventional microprocessor interface system;
Fig. 2 is illustrated in the mutual sequential chart of signal of carrying out the data phase of data transactions with reference to being used in the described data signal group of conventional microprocessor interface system of Fig. 1;
Fig. 3 is the figure that diagram is used for the table of the staggered ordering agreement of 8 data entity 0-7 of burst transmission on the system bus of Fig. 1;
Fig. 4 is diagram according to the table of the quad word ordering of the several values of the signal of the REQ bus of one exemplary embodiment of the present invention of supporting the dynamic burst ordering and corresponding request B grouping;
Fig. 5 is the figure of the table of diagram linear ordering agreement;
Fig. 6 is the figure of the table of diagram nibble linear ordering agreement;
Fig. 7 is the figure of the table of diagram exemplary customized ordering agreement;
Fig. 8 is according to making comprising of one exemplary embodiment of the present invention microprocessor can realize the block scheme of the microprocessor of the bus interface that dynamic burst sorts; And
Fig. 9 according to one exemplary embodiment of the present invention, use the microprocessor of Fig. 8 and be configured to support the simplified block diagram of Microprocessor Interface system of the bus agent of dynamic burst ordering.
Embodiment
Following explanation is used to make the one of ordinary skilled in the art can set up and use the present invention who provides in the environment of application-specific and requirement thereof.But, be obvious for the various modifications of preferred embodiment for the one of ordinary skilled in the art, and can be applied to other embodiment in the General Principle of this definition.Therefore, the present invention is not intended to be limited to specific embodiment shown here and described, but meets and principle disclosed herein and novel feature the wideest consistent scope.
The inventor has been noted that the cache line of microprocessor reads non-best (staller) cycle that is stopped of sorting and causing of issued transaction.Therefore, the inventor has developed the transaction beats that is used for dynamically sorting in the data transmission, keep simultaneously and existing and traditional bus protocol compatibility, and be used to specify for the dynamic apparatus and method of the customization data entity transportation protocol of appointment of the transmission of cache line or other types, this further specifies below with reference to Fig. 1-9.
Fig. 1 is the simplified block diagram of conventional microprocessor interface system 100.Described Microprocessor Interface system 100 comprises microprocessor 101 and the bus agent 103 that is connected with system bus 105.The known any amount of dissimilar bus agent of bus agent 103 expression those skilled in the art is such as Memory Controller, main frame/PCI (Peripheral Component Interconnect) bridge, chipset etc.Described system bus 105 comprises the signal that is used to carry out data transactions, comprising bi-directional address bus A, BDB Bi-directional Data Bus DATA and a plurality of control signal.In the graphic embodiment of institute, the A bus have be shown as A[35:3] 33 signals, the DATA bus have be shown as DATA[63:0] 64 signals, but should be appreciated that the signal that can have any right quantity according to concrete configuration and the described address of structure and data bus.Those skilled in the art can understand, and do not need minimum significant address signal (A[2:0]) to allow the transmitting data with quad word granularity, and this is the current state of this area.
Described control signal comprises: differential clocks bus B CLK[1:0]; Bi-directional address gate bus ADSTB[1:0] (validity of the address of indication on the A bus); Two-way request (REQ) bus, it has the signal REQ[4:0 of the transaction type that appointment asks] (the storer quad word that for example, memory code reads, memory data reads, memory lines writes, have a byte enable writes); A pair of data strobe bus DSTBP[3:0] and DSTBN[3:0]; BDB Bi-directional Data Bus busy signal DBSY (by the entity identification that data are provided on the DATA bus); Ready for data signal DRDY (by any device identification that data were provided during all clock period of transmitting data by the DATA bus); With response bus RS[2:0], it provides the type (for example no datat, normal data, implicit write-back) of the issued transaction response of just finishing on the DATA bus.In graphic embodiment, the RS bus have be shown as RS[2:0] 3 signals, and assert by bus agent 103.
In fact in all current microprocessors, provide the signal that is used for conventional microprocessor interface system 100 that is illustrated with less variation.Some processors are multiplexing address and data on same sets of signals, and therefore the control signal that indicates whether to exist data or address is provided.Other microprocessors use the control signal of different addresses or data-bus width or other name.And, can be than multiplexing address and/or data on by traditional Microprocessor Interface system 100 graphic those littler bus size.Be important to note that all basically processors all provide the signal of communicating by letter with bus agent, with the issued transaction of which kind of type of indication request, the parameter of that issued transaction, and transmission/reception data.
In comprising the current microprocessor of microprocessor 101, can be configured in that (8 quad words that for example are used for 64 byte cache-lines) transmit data on the basis of cache line according to " quadruple (quad-pumped) ".When transmitting whole cache line, use bus clock signal BCLK[1:0] two cycles in cache line, transmit 8 quad words that are associated.Therefore, at bus clock BCLK[1:0] each cycle during transmit four quad words, so explained descriptor " quadruple ".During such data transmit, data strobe bus DSTBP[3:0 is provided], DSTBN[3:0] signal with the validity of beat of each quad word of indication on data bus, so that during single bus clock, transmit 4 beats (each " beat " comprises 64 bits of DATA bus).
Fig. 2 is illustrated in the mutual sequential chart of signal of carrying out the data phase of data transactions with reference to being used in the conventional microprocessor interface system 100 described data signal group of Fig. 1.The operation of the such issued transaction in the microprocessor of x86 compatibility has been described in many lists of references and in the respective signal of this name, one of them is book " the The Unabridged of Tom Shanley
4IA32 Processor Genealogy, first published ".For the sake of clarity, the identification of control signal is shown as logic low, but those skilled in the art should be appreciated that also and can indicate identification by logic high.Differential bus clock BCLK[1:0] cycle be illustrated in the top of sequential chart, wherein, make with dashed lines that BCLK[1 is shown], and BCLK[1] with BCLK[0] opposite polar switching.
As mentioned above, the current state of this area provides the DATA bus of 64 bits, and it is supported in bus clock BCLK[1:0] two cycles go up transmission during the data phase of the cache line of 64 bytes.The transmission of the single quad word on 64 bit data bus (i.e. eight bytes) is called as a beat, and at bus clock BCLK[1:0] each cycle during transmit 4 beat A-D, E-H.When load is arranged (during data read request), transmitting critical quad word (being the quad word that its address is provided) during the first beat A during the request A stage on the address signal group, and according to staggered ordering agreement for the remaining beat B-H remaining quad word that sorts.
Fig. 3 is the figure that diagram is used for the table 300 of the staggered ordering agreement of 8 data entity 0-7 of burst transmission on system bus 105.Be used to send staggered ordering from the quad word of the cache line of storer and be the artificial effect that to obtain from the DRAM storehouse that substitutes every the older memory configurations scheme of a quad word (or according to the data entity of bus-structured any size---for example double word), got rid of thus and obtain the waiting status that two continuation addresses are associated usually from same DRAM storehouse.Though by using the staggered waiting status of having got rid of in older DRAM design, DRAM improves and makes system designer that the ordering of other types can be provided, such as linear ordering or other orderings that will describe afterwards.
The legacy system of carrying out the burst transmission on data bus only allows the transmission ordering of single type.For example, a kind of processor configuration allows graphic staggered ordering in table 300.The inventor observes in most of the cases, is best from the linear ordering of data proximity.Therefore, the system bus of linear ordering transmits data to minimize owing to cache line reads the mode that the processing that causes stops.Though linear ordering may be best in many cases, be very harmful (promptly causing a plurality of streamlines stops) in some cases.For example, consider that wherein quad word 7 is transmission of the cache line of critical quad word.From the data proximity, linear ordering has maximized the quantity that stops.For this situation, perhaps staggered ordering is better.
Therefore, expectation provides a kind of protocol, its allow as a part that is used for the request stage that cache line reads dynamically the specific data entity transmit ordering.Also expectation provides dynamically to specify and transmits ordering, keeps the apparatus and method with existing and traditional bus protocol compatibility simultaneously.And expectation provides a kind of technology that is used for stipulating the customization data entity transportation protocol of the dynamic appointment that can transmit for cache line or other types.Bus protocol according to one embodiment of the present of invention is suitable for as above with reference to the described compatible bus structure of current x86-of using request A and request B grouping via the REQ bus of Fig. 1 and 2.And, ask the DSZ field of B grouping that the dynamic appointment that happens suddenly and sort is provided according to the agreement of one embodiment of the present of invention by using, it has used REQ[4:3 described herein] signal.
Fig. 4 is diagram according to the REQ[4:3 of the REQ bus of one exemplary embodiment of the present invention of supporting the dynamic burst ordering] table 400 of the quad word ordering of the several values of signal and corresponding request B grouping.The residual signal REQ[2:0 of REQ bus] be illustrated as " X " value, being used to indicate them is unspecified or " haveing nothing to do " value.Append to " B " expression binary value of described value.As shown in table 400, REQ[4:3] to be set to the 00B request be the nibble linear ordering corresponding to the ordering of reading transmission of regulation to signal, as shown in the table 600 of Fig. 6.REQ[4:3] to be set to 01B request be linear ordering corresponding to the ordering of reading transmission of regulation to signal, as shown in the table 500 of Fig. 5.REQ[4:3] signal is set to 11B and specifies the ordering of reading transmission corresponding to regulation to interlock, as shown in the table 300.With REQ[4:3] signal is set to 10B to specify the ordering of reading transmission corresponding to regulation is the customization ordering, shown in the table 700 of Fig. 7.In response to according to transaction request of the present invention, come the mode of transmitted data entity to carry out the Remaining Stages that reads issued transaction with sequencing schemes according to appointment.
Table 700 illustrates the exemplary customized sequencing schemes that is used for 8 data entity 0-7 of burst transmission on system bus 105 according to one embodiment of the present of invention.It will be apparent to those skilled in the art that, consider any ordering that can imagine of data entity according to the customization ordering of embodiments of the invention, to comprise the transmission of specific purposes, wherein be less than the whole piece cache line and be transmitted, and wherein double transmit one or more entities.Should be noted that described staggered, linearity and nibble linear ordering adopt the AD HOC that those skilled in the art understood.For staggered ordering, in ordering subsequently, exchange the order of each quad word or many combinations to quad word or four quad words.For example, for the numbering of second quad word wherein 1 be critical quad word be numbered " 1 " second ordering, with quad word 1 and quad word 0 exchange, with quad word 3 and quad word 2 exchanges, or the like.For linear quad word ordering, described ordering is similar to first-in first-out (FIFO) formation, and wherein, first is reordered into the rearmost position.Therefore, if quad word is critical quad word, then quad word 0 is reordered into last position (being 1-2-3-4-5-6-7-0), and if quad word 2 are critical quad words, then quad word 1 is resequenced to rearmost position (2-3-4-5-6-7-0-1), or the like.The nibble linear ordering is similar to linear ordering, except handling quad word with four grouping.On the other hand, customization ordering be by the deviser or by the user according to specific implementation and definite any ordering.
Fig. 8 is according to making comprising of one exemplary embodiment of the present invention microprocessor 800 can realize the block scheme of the microprocessor 800 of the bus interface logic circuit 801 that dynamic burst sorts.Bus interface logic circuit 801 is couple to system bus 105, and system bus 105 comprises DATA bus (signal D[63:0]) and REQ bus (signal REQ[4:0]).Microprocessor 800 comprises command logic circuitry 803, and being used for provides instruction via instruction bus (INS BUS) 805 to bus interface logic circuit 801.Microprocessor 800 comprises data caching 807, and it is couple to cache memory bus 809.Instruction such as loading and storage instruction is provided to bus interface logic circuit 801 from command logic circuitry 803.Bus interface logic circuit 801 produces the corresponding requests of system bus 105 via the REQ bus, and via the DATA bus to/from system bus 105 transmitted data entity (for example quad word).
In operation, when bus interface logic circuit 801 received load instructions on instruction bus 805, the field in described instruction was specified the burst order of corresponding load operation.Perhaps, the request logical circuit 811 in bus interface logic circuit 801 is configured to always specify a specific burst order during the initialization of microprocessor 800 (for example reset or power up).In another embodiment, during initialization, BIOS instruction configuration or programming described request logical circuit 811.In one embodiment, request logical circuit 811 comprises one or more machine particular register making up admissible burst order, and can configuration and customization sequence list (for example by shown in the customization sequencing table 700).In one embodiment, originally on one's body or via a side bus (not shown), during system initialization, send the configuration of microprocessor 800 and the type of the order that provided at system bus to system bus 105 or the bus agent on it such as I2C bus etc.
Thereafter, any one embodiment according to the foregoing description, when when specifying load operation from the instruction of command logic circuitry 803, request logical circuit 811 disposes the DSZ field of the request B grouping of regulation transaction request according to the burst order of appointment, and the request impact damper 813 that is provided to and asks logical circuit 811 to couple it.Request impact damper 813 sends request B grouping on the REQ of system bus 105 bus.Request logical circuit 811 and request impact damper 813 jointly form request interface 814, and request interface 814 provides the request for data transactions, and selected burst order is specified in wherein said request.
When the data phase of issued transaction takes place, be provided at the data entity of the correspondence of burst transmitting from system bus 105 to the response buffer 815 of microprocessor 800, the response buffer 815 of described microprocessor 800 externally connects the DATA bus, and in inner connection cache bus 809.According to the burst ordering of transaction type, one of four example sequence process logic circuit components correctly provide the data entity that is received via cache bus 809 to data caching 807.The exemplary process logic circuit component comprises staggered logical circuit 817, linear logic circuit 819, nibble linear logic circuit 821 and customized logic circuit 823, and each is couple to cache memory bus 809.If named order is interlocked, then staggered logical circuit 817 provides described data entity when data entity arrives data caching 807.Response buffer 815 and ordering logical circuit 817,819,821 and 823 together form response interface 824, it according to selected burst order with the data storage that received in data caching 807.If named order is linear, then linear logic circuit 819 provides described data entity when data entity arrives data caching 807.If named order is the nibble linearity, then nibble linear logic circuit 821 provides described data entity when data entity arrives data caching 807.If named order customizes, then customized logic circuit 823 provides described data entity when data entity arrives data caching 807.In one embodiment, receive in each of processor logic elements at described four sequencing table is provided.In another embodiment, specified order in bus interface logic circuit 801.In the 3rd embodiment, described order is programmed during initialization in machine particular register (not shown), and is provided to bus interface logic circuit 801.
Fig. 9 is the simplified block diagram according to the Microprocessor Interface system 900 of one exemplary embodiment of the present invention.Described Microprocessor Interface system 900 is similar to traditional Microprocessor Interface system 100, except microprocessor 101 is replaced with microprocessor 800, and bus agent 103 is replaced with bus agent 900.System bus 105 is comprised being used for microprocessor 800 is connected with bus agent 900.According to one exemplary embodiment of the present invention, microprocessor 800 comprises bus interface logic circuit 801, and it makes microprocessor 800 can realize the dynamic burst ordering.According to one exemplary embodiment of the present invention, bus agent 900 comprises bus interface logic circuit 901, and it makes bus agent 900 can realize the dynamic burst ordering.Bus interface logic circuit 901 is configured to and bus interface logic circuit 801 compatibilities, to provide via the request B grouping that provides on aforesaid REQ bus according to the quad word on the DATA bus of ordering by the burst ordering of bus interface logic circuit 801 appointments.
According to one embodiment of the present of invention be used for being particularly useful for to embed in the apparatus and method that data transmit ordering transaction beats use because customization burst transmission order can be configured and the cache line that is used for optimizing the application-specific of carrying out on embedded processor is filled.The present invention also provides the advantage for operating system, can carry out specific known application thus, so that stop to carry out the burst transmission to transmit the minimum that causes owing to cache line.
Though understand the present invention quite in detail with reference to some preferable specific pattern, other pattern and conversion also are possible with admissible.Those skilled in the art should understand, and they can easily use disclosed design and specific embodiment to be used as designing or revise to be used to the basis of other structures of carrying out identical purpose of the present invention under the prerequisite that does not break away from the spirit and scope of the present invention defined by the appended claims.
This requires No. 60/700692 U.S. Provisional Application of submission on July 19th, 2005, and the rights and interests of No. 11/379166 U.S.'s formal application case of what submission on April 18th, 2006, at this it is quoted as a reference.
The application relates to the U.S. Patent application of following common pending trial, and they all have common surrenderee and common inventor.
Sequence number submission date denomination of invention
11/,364,704 2/28/2006 are used for the apparatus and method that sparse line writes issued transaction
11/,363,826 2/28/2006 are used to enable the microprocessor dress that the variable-width data transmit
Put and method
11/,369,896 3/7/2006 are used for the apparatus and method of quadruple address bus
11/,374,663 3/13/2006 flexible width data protocols
Claims (13)
1. microprocessor comprises:
Cache memory; And
The bus interface logic circuit is connected with data-signal with request signal, comprising:
Request interface provides request via the request signal that is used for data transactions, and wherein said request interface is specified selected burst order by the field of configuration request packet during the request stage of described data transactions;
Response interface is couple to described cache memory, and the data storage that described response interface will receive via described data-signal according to described selected burst order is in described cache memory.
2. according to the microprocessor of claim 1, wherein from staggered ordering, linear ordering, nibble linear ordering and the described selected burst order of customization sequencing selection.
3. according to the microprocessor of claim 1, also comprise command logic circuitry, provide instruction to specify described selected burst order to described bus interface logic circuit.
4. according to the microprocessor of claim 1, wherein said request interface comprises the request logical circuit of specifying described selected burst order and is couple to the described request logical circuit and is connected the request impact damper of described request signal.
5. according to the microprocessor of claim 4, comprising following both one of:
The described request logical circuit is by the pre-configured next described selected burst order of specifying during described microprocesser initialization;
Programming described request logical circuit is to specify described selected burst order during initialization.
6. according to the microprocessor of claim 1, wherein said to answering interface to comprise:
The response buffer that is connected with described data-signal;
The cache bus that couples with described response buffer and described cache memory; And
The ordering logical circuit is couple to described cache bus, the data that storage receives via described response buffer in described cache memory according to described selected burst order.
7. according to the microprocessor of claim 6, wherein said ordering logical circuit comprises:
Staggered logical circuit, according to staggered ordering with data storage in described cache memory;
The linear logic circuit, according to linear ordering with data storage in described cache memory;
Nibble linear logic circuit, according to the nibble linear ordering with data storage in described cache memory; And
The customized logic circuit, according to customization ordering and with data storage in described cache memory.
8. Microprocessor Interface system comprises:
System bus comprises: request bus and data bus;
Microprocessor comprises:
Cache memory;
The request logical circuit, be connected to the described request bus, be provided for the request of the appointment of data transactions for the selected burst order of described data transactions on the described request bus, the field of configuration request packet is to specify described selected burst order and the described request grouping is provided on the described request bus; And
Responsing logic circuit is connected to described cache memory and described data bus, according to described selected burst order with the data storage that receives from described data bus to described cache memory; And
Bus agent is couple to described system bus, and described bus agent receives described request, and the described data that will be used for described data transactions according to described selected burst order are provided to described data bus.
9. according to the Microprocessor Interface system of claim 8, wherein said bus agent comprises the bus interface logic circuit that is configured to be used for the dynamic burst ordering.
10. according to the Microprocessor Interface system of claim 8, wherein said selected burst order is one that selects in interleaved order, linear precedence, nibble linear precedence and customization order.
11. the method for a sorting data beat in data transactions comprises:
Use selected burst order to dispose request, comprise the field of configuration request packet or come configuring request according to one that in interleaved order, linear precedence, nibble linear precedence and customization order, selects for data transactions;
The request that will be used for data transactions during request stage is provided to system bus;
During the data phase of the correspondence of data transactions, receive data from system bus; And
Store data according to selected burst order.
12., also comprise following thrin according to the method for claim 11:
Load instructions is provided, and it specifies selected burst order;
Use selected burst order to come pre-configured request logical circuit;
Logical circuit is asked in programming when initialization according to selected burst order.
13. according to the method for claim 11, store data wherein said comprising according to one that selects in interleaved order, linear precedence, nibble linear precedence and customization order according to selected burst order storage data.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US70069205P | 2005-07-19 | 2005-07-19 | |
| US60/700,692 | 2005-07-19 | ||
| US11/379,166 | 2006-04-18 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1892633A CN1892633A (en) | 2007-01-10 |
| CN100407182C true CN100407182C (en) | 2008-07-30 |
Family
ID=37597512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006101059489A Active CN100407182C (en) | 2005-07-19 | 2006-07-19 | Apparatus and method for ordering transaction beats in a data transfer |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100407182C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2008234059A (en) * | 2007-03-16 | 2008-10-02 | Fujitsu Ltd | Data transfer device and information processing system |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5255378A (en) * | 1989-04-05 | 1993-10-19 | Intel Corporation | Method of transferring burst data in a microprocessor |
| US5640517A (en) * | 1993-06-22 | 1997-06-17 | Dell Usa, L.P. | Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order |
| US5644788A (en) * | 1994-10-28 | 1997-07-01 | Cyrix Corporation | Burst transfers using an ascending or descending only burst ordering |
| US5860128A (en) * | 1996-10-01 | 1999-01-12 | Intel Corporation | Method and apparatus for sampling data from a memory |
| US6032225A (en) * | 1995-12-18 | 2000-02-29 | Texas Instruments Incorporated | Microprocessor system with burstable, non-cacheable memory access support |
| US6405280B1 (en) * | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
| CN1567279A (en) * | 2003-06-20 | 2005-01-19 | 上海奇码数字信息有限公司 | Data transmission method and data transmission system |
| US20050066114A1 (en) * | 1995-10-19 | 2005-03-24 | Barth Richard Maurice | Protocol for communication with dynamic memory |
-
2006
- 2006-07-19 CN CN2006101059489A patent/CN100407182C/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5255378A (en) * | 1989-04-05 | 1993-10-19 | Intel Corporation | Method of transferring burst data in a microprocessor |
| US5640517A (en) * | 1993-06-22 | 1997-06-17 | Dell Usa, L.P. | Method and apparatus for masters to command a slave whether to transfer data in a sequential or non-sequential burst order |
| US5644788A (en) * | 1994-10-28 | 1997-07-01 | Cyrix Corporation | Burst transfers using an ascending or descending only burst ordering |
| US20050066114A1 (en) * | 1995-10-19 | 2005-03-24 | Barth Richard Maurice | Protocol for communication with dynamic memory |
| US6032225A (en) * | 1995-12-18 | 2000-02-29 | Texas Instruments Incorporated | Microprocessor system with burstable, non-cacheable memory access support |
| US5860128A (en) * | 1996-10-01 | 1999-01-12 | Intel Corporation | Method and apparatus for sampling data from a memory |
| US6405280B1 (en) * | 1998-06-05 | 2002-06-11 | Micron Technology, Inc. | Packet-oriented synchronous DRAM interface supporting a plurality of orderings for data block transfers within a burst sequence |
| CN1567279A (en) * | 2003-06-20 | 2005-01-19 | 上海奇码数字信息有限公司 | Data transmission method and data transmission system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1892633A (en) | 2007-01-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4083987B2 (en) | Communication system with multi-level connection identification | |
| US10270447B2 (en) | Apparatus for configurable interface and associated methods | |
| AU625084B2 (en) | Data processing system with means to convert burst operations into memory pipelined operations | |
| EP0321156A2 (en) | Data transfer controller | |
| US7054986B2 (en) | Programmable CPU/interface buffer structure using dual port RAM | |
| US7818546B2 (en) | Pipeline processing communicating adjacent stages and controls to prevent the address information from being overwritten | |
| CN102971795A (en) | Method and apparatus for concurrently reading a plurality of memory devices using a single buffer | |
| CN1819554B (en) | Data processing system and data interfacing method thereof | |
| US20120096199A1 (en) | Bus system including id converter and converting method thereof | |
| US6799304B2 (en) | Arbitration within a multiport AMBA slave | |
| US6742058B2 (en) | Memory controller having a multiplexer selecting either second set of input signals or converted signals from first set of input signals by a bus mode input | |
| CN100407182C (en) | Apparatus and method for ordering transaction beats in a data transfer | |
| US7069352B2 (en) | Serial peripheral interface and related methods | |
| US7062588B2 (en) | Data processing device accessing a memory in response to a request made by an external bus master | |
| US6754760B1 (en) | Programmable interface for a configurable system bus | |
| TW508492B (en) | Method and system for partitioning configured address space | |
| US7590787B2 (en) | Apparatus and method for ordering transaction beats in a data transfer | |
| JP3477306B2 (en) | Extended input / output interface | |
| EP0362425B1 (en) | Input/output controller incorporating address mapped input/output windows and read ahead/write behind capabilities | |
| KR100487199B1 (en) | Apparatus and method for data transmission in dma | |
| CN116745753A (en) | Tag for request packets on a network communication link | |
| US8498165B2 (en) | Data outputing method of memory circuit and memory circuit and layout thereof | |
| US8510478B2 (en) | Circuit comprising a microprogrammed machine for processing the inputs or the outputs of a processor so as to enable them to enter or leave the circuit according to any communication protocol | |
| TW579462B (en) | Data write circuit | |
| CN100461142C (en) | Microprocessor apparatus, processor bus system and method of performing a sparse write transaction |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |